WinCE.NET下串口驱动开发设计

嵌入式开发是跟具体硬件平台密切相关的,硬件驱动是开发的基础,介绍了Win CE.NET下工作在中断模式的串口驱动的开发,重点讲述了流设备驱动的加载过程、中断处理、分层串口驱动的设计及其中断相关的函数设计。     

Experience from design and application of the top-level system of the process control system of nuclear power-plant

Consideration was given to the design of the top-level system of the nuclear power-plant process control system with regard for the impact on its safety. This system is aimed at centralizing process instrumentation and control. The top-level system is a sophisticated hardware complex supported by the computer-aided design and adjustment system and intended for integrating all subsystems of the process control system. The top-level system executes the informational, control, service, and auxiliary functions of the nuclear power-plant process control system. Consideration was given to the structure of the top-level system, the structure of its software, and the principles of design providing high performance of the top-level system.     

一种支持H．264和AVS的帧内预测器设计

为了使多标准视频解码器中的帧内预测器能够支持H.264和AVS两种视频标准,在对H.264和AVS两标准中的帧内预测计算模式进行分析,并对各模式计算公式之间相似性进行分析的基础之上,提出了一种支持H.264和AVS两种标准的,可配置的帧内预测值计算硬件架构。该架构由于将大部分预测模式的计算放到一个可配置的计算单元中进行,从而大大减少了芯片资源的浪费。为了提高处理速度,可采用4个相同的可配置的计算单元并行计算,一次计算出4个像素点的预测值。实验结果表明,该硬件架构在FPGA上占用10371个LUTs,频率可以达到150MHz。     

Codesign of embedded systems: status and trends

Ever increasing embedded system design complexity combined with a very tight time-to-market window has revolutionized the embedded-system design process. The concurrent design of hardware and software has displaced traditional sequential design. Further, hardware and software design now begins before the system architecture (or even the specification) is finalised. System architects, customers, and marketing departments develop requirement definitions and system specifications together. System architects define a system architecture consisting of cooperating system functions that form the basis of concurrent hardware and software design. Interface design requires the participation of both hardware and software developers. The next step integrates and tests hardware and software-this phase consists of many individual steps. Reusing components taken from previous designs or acquired from outside the design group is a main design goal to improve productivity and reduce design risk. It is argued that new methodologies and AD tools support an integrated hardware software codesign process     

基于NiosⅡ的视频采集与DVI成像研究及实现

采用FPGA作为视频采集控制和图像处理芯片,配置NiosⅡ软核,在FPGA片内完成图像处理和图像显示控制,简化了硬件电路和软件程序的设计。在FPGA片内编写视频采集时序,并配置NiosⅡ控制软核,模拟视频数据经视频解码芯片输出ITU-RBT.656格式数据送入FPGA,通过时序控制和NiosⅡ软核把视频解码数据依序存储在SSRAM中,并进行裁剪、交织、颜色处理。     

基于OMRON——E6B2编码器的玻管切割控制器设计

介绍一种基于OMRON-E6B2编码器的石英玻璃管切割控制器的设计方法,利用ATmega16单片机作为控制中枢,从硬件和软件两方面阐述了控制器的设计思路,对硬件原理图和程序框图作了简捷的描述。本设计为石英玻璃管的切割控制提供了一种有效的方法,实践证明,设计的控制器具有较高的实用价值,能够完成对石英玻璃管切割过程的准确控制,从而提高产品的质量,产生可观的经济效益。     

基于FPGA的H．264变换量化的高性能的硬件实现

针对H．264视频标准中一个功能频繁调用的变换量化模块，提出了一种高性能的FPGA硬件实现方法。并完成了其硬件原型的设计。该硬件原型包含了从残差形成到宏块重建的变换量化全过程。其可以构成DSP的协处理器，用于完成H．264实时编解码。该硬件原型根据算法特点和数据流特点，采用了流水线控制策略和分时复用技术，同时合理利用FPGA片内资源，从而提高了系统性能。仿真结果表明。该设计能满足高清数字视频的实时处理应用。     

基于FPGA的视频采集及转换系统设计

基于数字图像处理技术和FPGA（现场可编程门阵列）技术,针对高精度单色CCD视频传感器1010_M的输出规范,结合高速视频接口标准的需求,设计并实现了一种视频采集及转换系统。系统重点介绍了视频采集及转换系统硬件电路结构,软件设计流程,主要相关电路设计和FPGA逻辑设计,并给出测试结果。     

基于多代理系统的软硬件协同设计

为使软硬件协同设计过程更具分布性、自主性及并行性,在软硬件协同设计中引入多代理(MAS)技术,提出软硬件协同设计的MAS模型,包括系统描述Agent、软硬件划分及映射Agent、软硬件设计Agent、协同通信Agent、性能评估Agent和硬件系统测试Agent的构建和应用。采用多个目标代理映射、协商的方法协调整个协同设计过程。实际应用表明,该方法能优化系统级芯片设计方案、软硬件结构和功能,并提高系统整体性能。     

用XYZ／E语言描述和验证硬件的行为

本文考虑用时态逻辑语言ＸＹＺ／Ｅ描述硬件行为的可行性．作为实例，用ＸＹＺ／Ｅ语言描述了一个基于微处理器的容错计算机系统，这种描述可以在ＸＹＺ系统上执行，从而可对系统进行模拟．特别有意义的是利用ＸＹＺ／ＶＥＲＩ验证子系统对所期望的性质进行了形式化证明．本文还将ＸＹＺ／Ｅ描述与相应的ＶＨＤＬ（ＶＨＳＩＣｈａｒｄｗａｒｅｄｅｓｃｒｉｐｔｉｏｎｌａｎｇｕａｇｅ）描述进行了比较．从中可以看出时态逻辑语言的描述具有其独特的优点.     

Evaluation of user interfaces: EVADIS II— a comprehensive evaluation approach

Abstract

As a result of the importance of the usability approach in system development and the EC's ‘Directive concerning the minimum safety and health requirements for VDT workers’ (EWG 1990), there is an accepted need for practical evaluation methods for user interfaces. The usability approach and the EC Directive are not restricted to user interface design, as they include the design of appropriate hardware and software, as well as organization, job, and task design. Therefore system designers are faced with many, often conflicting, requirements and need to address the question, ‘How can usability requirements comprehensively be considered and evaluated in system development?’ Customers buying hardware and software and introducing them into their organization ask, (How can I select easy-to-use hardware and software?’ Both designers and customers need an evaluation procedure that covers all the organizational, user, hard- and software requirements. The evaluation method, EVADIS.II, we present in this paper overcomes characteristic deficiencies of previous evaluation methods. In particular, it takes the tasks, the user, and the organizational context into consideration during the evaluation process, and provides computer support for the use of the evaluation procedure.     

微机非线性励磁控制器的实现及应用

本文结合一个电厂的发电机励磁系统的具体实全离发电机励磁原理,详细描述了微机非线性励磁控制的硬件结构设计、处理过程及可靠性设计,对比自动励磁调节器阐明了微机非线性励磁控制器性能特点。应用效果。     

Interfacing the hardware API with a feature-based operating system family

Multiprocessor systems on a chip (MPSoCs) are a popular class of course-grained parallel computer architectures, which are very useful, because they support re-use of legacy software components and application-specific tailoring of hardware structures at the same time. Furthermore, model-driven design frameworks for MPSoCs such as Xilinx’ EDK or our own LavA-framework facilitate very fast system development. However, in this paper we argue that these design frameworks are not ideal from the development process perspective. Instead, we propose a software-centric approach that is based on the hardware API concept. The API is a representation of hardware components on the software level, which is generated from a hardware meta-model. It allows us to automatically derive a hardware structure based on access patterns in software, revealed by a static code analysis. This trick reduces the number of hardware details the developer needs to deal with and avoids configuration inconsistencies between the hardware and software levels by design. Furthermore, we present how the development process can benefit from the hardware API, when the API is interfaced with a configurable operating system.     

基于嵌入式开发平台的串口网关及视频采集传输解决方案

本文针对嵌入式系统的特点,以高性价比的32位ARM嵌入式处理器AT91SAM9G20为硬件核心,搭建了硬件平台。作者首先介绍了硬件平台的设计过程,然后研究了嵌入式Linux的软件开发环境的构建。最后,结合具体的实际应用需求,开发了基于多串口联网的服务程序,并给出基于本平台的视频监控系统的解决方案,实现了该研发平台的应用价值。     

基于S3C2410的触摸屏及其组态系统的设计与实现

主要介绍基于S3C2410的触摸屏及其组态系统的构建过程,包括硬件平台的设计,系统软件的设计以及组态软件系统的设计。硬件平台设计提出了整个硬件平台的架构,系统软件的设计阐述了引导加载程序,嵌入式Linux以及根文件系统的设计过程;组态系统的设计包括PC端的画面编辑软件和触摸屏端的画面运行系统的设计。     

Hardware assisted high-level debugging

Hardware assistance has long been used for logic level and functional unit level hardware debugging, as well as for machine language level software debugging. Such hardware assistance includes probes to detect signals, comparators to identify matches with expected patterns, buffers to record selected events, and independent logic and software to analyze and interpret the observed events. It can also include the ability to generate selected signals to stimulate the object being debugged and the ability to isolate it from normal changes so its state can be examined. Through knowledge of the data structures and algorithms used by the operating systems, and the runtime representation, register usage, and code bursts produced by compilers, it is possible to take advantage of such hardware assistance in high-level debugging. High-level debugging here refers to debugging in terms of abstractions supported by the operating system and programming languages, as well as user defined abstractions built on top of these. This paper discusses design considerations behind a project to build such a hardware assisted high-level debugger.     

机器人控制软件的图形化编程系统设计

提出了一种基于图形化编程的机器人软件系统的总体结构设计,包括软件结构的总体设计思路,主要处理从流程图式的图形化结构到类C语言的转换,再将这种类C语言翻译转换为下位机所能识别的目标代码,经过串口通讯下载到下位机中,完成上位机和下位机的信息交互.提出的设计方法和思路已经过严格的测试和检测,实际应用表明,该系统具有较好的灵活性,稳定性和实用性.     

Hardware/software co-design for particle swarm optimization algorithm

This paper presents a hardware/software (HW/SW) co-design approach using SOPC technique and pipeline design method to improve design flexibility and execution performance of particle swarm optimization (PSO) for embedded applications. Based on modular design architecture, a Particle Updating Accelerator module via hardware implementation for updating velocity and position of particles and a Fitness Evaluation module implemented either on a soft-cored processor or Field Programmable Gate Array (FPGA) for evaluating the objective functions are respectively designed to work closely together to carry out the evolution process at different design stages. Thanks to the design flexibility, the proposed approach can tackle various optimization problems of embedded applications without the need for hardware redesign. To further improve the execution performance of the PSO, a hardware random number generator (RNG) is also designed in this paper in addition to a particle re-initialization scheme to promote exploration search during the optimization process. Experimental results have demonstrated that the proposed HW/SW co-design approach for PSO algorithms has good efficiency for obtaining high-quality solutions for embedded applications.     

基于单片机与TA8435h的步进电机控制系统

介绍了一种云台控制装置,阐明了驱动芯片TA 8435h细分控制的原理,描述了系统硬件构成,并给出了电路原理图;着重介绍了利用单片机控制驱动芯片工作的硬件设计方法以及硬件的设计过程,给出了驱动程序的设计过程,对Peclo协议做了详细的阐述,包括peclo协议的格式和编译流程。该设计有效地应用在负载转动装置系统中。