Graph-based iterative decoding algorithms for parity-concatenatedtrellis codes

We construct parity-concatenated trellis codes in which a trellis code is used as the inner code and a simple parity-check code is used as the outer code. From the Tanner-Wiberg-Loeliger (1981, 1996) graph representation, several iterative decoding algorithms can be derived. However, since the graph of the parity-concatenated code contains many short cycles, the conventional min-sum and sum-product algorithms cannot achieve near-optimal decoding. After some simple modifications, we obtain near-optimal iterative decoders. The modifications include either (a) introducing a normalization operation in the min-sum and sum-product algorithms or (b) cutting the short cycles which arise in the iterative Viterbi algorithm (IVA). After modification, all three algorithms can achieve near-optimal performance, but the IVA has the least average complexity. We also show that asymptotically maximum-likelihood (ML) decoding and a posteriori probability (APP) decoding can be achieved using iterative decoders with only two iterations. Unfortunately, this asymptotic behavior is only exhibited when the bit-energy-to-noise ratio is above the cutoff rate. Simulation results show that with trellis shaping, iterative decoding can perform within 1.2 dB of the Shannon limit at a bit error rate (BER) of 4×10^-5 for a block size of 20000 symbols. For a block size of 200 symbols, iterative decoding can perform within 2.1 dB of the Shannon limit     

Iterative Viterbi decoding, trellis shaping, and multilevelstructure for high-rate parity-concatenated TCM

We define and apply a new algorithm called the iterative Viterbi decoding algorithm (IVA) to decode a high-rate parity-concatenated TCM system in which a trellis code is used as the inner code and a simple parity-check code is used as the outer code. With trellis shaping, the IVA can achieve a performance 1.25 dB away from the Shannon limit at a BER of 3×10^-5 with low complexity. By augmenting the system with a binary BCH code, the error floor can be reduced to 10^-9 with very little additional cost     

Adaptive differential detection using linear prediction for M-aryDPSK

This paper proposes a novel adaptive differential detection scheme (adaptive DD), which can significantly reduce the irreducible bit-error rate (BER) of M-ary DPSK due to Doppler spread by the adaptive linear prediction of the reference signal. The predictor coefficient is adapted to changing channel conditions by using the recursive least-square (RLS) algorithm. A phase sequence estimation based on the M-state Viterbi algorithm (VA) and another based on the decision feedback algorithm (DFA) are presented. A theoretical BER analysis is presented for adaptive DD-DFA. BER performances of 2 and 4DPSK in Rayleigh fading channels are evaluated by computer simulations. When the RLS forgetting factor of β=1 is used, simulation results show that the irreducible BER of 4DPSK can be reduced to 7.2×10^-5 (3.9×10 ^-4) for VA (DFA) while conventional DD offers 3.9×10 ^-3 when f_DT_b (maximum Doppler frequency times bit duration)=0.01 and average E_b/N₀ (signal energy per bit-to-additive white Gaussian noise (AWGN) power spectrum density ratio)=60 dB, where most errors are produced by Doppler spread. Adaptive DD is also effective in AWGN channels-simulations show that for the case of 4DPSK, a performance gain of 1.2 (0.7) dB is achieved over conventional DD for VA (DFA) at BER=10^-3     

Proposal for Beyond 100-Gb/s Optical Transmission Based on Bit-Interleaved LDPC-Coded Modulation

An iterative bandwidth-efficient coded modulation scheme based on bit-interleaving low-density parity-check (LDPC) codes, and M-ary differential phase-shift keying is proposed. A bit-interleaved LDPC-coded scheme, carrying 3 bits/symbol, provides the coding gain of 8.3 dB at a bit-error rate (BER) of 10^-7. The expected coding gain at BER of 10^-12 is 12.8 dB. Possible applications include 100G Ethernet, and high-speed (>100 Gb/s) long-haul transmission     

Simple MAP acceleration using pre-decoding for punctured turbo code

A simple algorithm that accelerates maximum a posteriori (MAP) decoding of a punctured turbo code is proposed. A turbo code consists of a data bit stream and a plurality of parity bit streams, some of which possibly had components removed by puncturing. The proposed method performs pre-decoding and re-encoding to find omitted parity symbols of the received sequence. This protocol provides a turbo-coded system of between rate-1/2 and rate-1/3. Simulation results show that the proposed algorithm reduces the number of iterations, which is equivalent to the decoding delay, to 50% for approaching a bit error rate (BER) of approximately 3.38 times 10^-3 at 1.0 dB.     

Probabilistic construction of large constraint length trellis codesfor sequential decoding

Probabilistic algorithms are given for constructing good large constraint length trellis codes for use with sequential decoding that can achieve the channel cutoff rate bound at a bit error rate (BER) of 10^-5-10^-6. The algorithms are motivated by the random coding principle that an arbitrary selection of code symbols will produce a good code with high probability. One algorithm begins by choosing a relatively small set of codes randomly. The error performance of each of these codes is evaluated using sequential decoding and the code with the best performance among the chosen set is retained. Another algorithm treats the code construction as a combinatorial optimization problem and uses simulated annealing to direct the code search. Trellis codes for 8 PSK and 16 QAM constellations with constraint lengths v up to 20 are obtained. Simulation results with sequential decoding show that these codes reach the channel cutoff rate bound at a BER of 10^-5-10^-6 and achieve 5.0-6.35 dB real coding gains over uncoded systems with the same spectral efficiency and up to 2.0 dB real coding gains over 64 state trellis codes using Viterbi decoding     

Improved LDPC-based short-range frequency-hopping wireless communication system

In short-range wireless communication system(SWCS),the complex scenarios make its transmission face the diverse interference,and lower hardware resource leads to its limited anti-interference capability.To achieve the reliable transmission,a frequency-hopping-based SWCS (FH-SWCS)with improved LDPC (I-LDPC) code was constructed.In FH-SWCS,a low-complexity check-sum updating(LCU)algorithm was proposed to reduce the amount of computation.LCU-based multi-threshold bit flipping (LCU-MTBF) algorithm was given to increase the reliability of bit-flipping, improving decoding performance and reduce the complexity of decoding.The simulation results demonstrate that LCU is suitable for multiple hard decisions decoding algorithm,and it can reduce the computational complexity of original decoding algorithm without affecting its performance.When BER is 10^?5,and iterations number is 5,0.15dB performance gain can be achieved,and the number of additions algorithm can be reduced about 40% in LCU-MTBF.In FH-SWCS with I-LDPC,when BER is 10^?4,and SNR is 15dB,the performance gain about 7dB can be achieved to improve the anti-interference of the system effectively.     

Approaching Shannon's capacity limit by 0.2 dB using simple Hammingcodes

The authors show that the Shannon capacity limit for the additive white Gaussian noise (AWGN) channel can be approached within 0.27 dB at a bit error rate (BER) of 10^-5 by applying long but simple Hamming codes as component codes to an iterative turbo-decoding scheme. In general, the complexity of soft-in/soft-out decoding of binary block codes is rather high. However, the application of a neurocomputer in combination with a parallelization of the decoding rule facilitates an implementation of the decoding algorithm in the logarithmic domain which requires only matrix additions and multiplications. But the storage requirement might still be quite high depending on the interleavers used     

Iterative Viterbi algorithm for concatenated multidimensional TCM

A novel compound code is designed for the multidimensional (M-D) Wei (1987) trellis code combined with a simple parity-check code. Using the iterative Viterbi decoding algorithm, we can achieve a remarkable performance improvement with low computational complexity. Simulation results show that at a bit error rate (BER) of 3.7 × 10^-6 about 2.2-dB additional net gain has been obtained over the conventional scheme of the 4-D 16-state Wei code at a spectral efficiency of 6.7871 bit/T     

An implementation of a CMA adaptive array for high speed GMSKtransmission in mobile communications

The hardware implementation of an adaptive array as a technique for compensating multipath fading in mobile communications is described. The number of the antenna elements is four. The target communication system is modulated by 256 kbps Gaussian-filtered minimum shift keying (MSK) and has a time-division multiplexing (TDM) architecture with 24 time slots. Based on the digital beamforming concept, all of the signals and the array weights are digital-signal processed. The constant modulus algorithm (CMA) is employed for weight optimizing. In an additive white Gaussian noise channel, this system has 5.6-dB gain in an energy-per-bit-to-noise-density ratio at a bit error rate (BER) of 1.0×10^-3, compared with a single antenna system. The result of the basic field test shows that the gain at a BER of 1.0×10^-3 reaches 22.3 dB in a nonselective, slow Rayleigh fading channel given a 5 Hz maximum Doppler shift     

A 0.18-$muhbox m$CMOS Analog Min-Sum Iterative Decoder for a (32,8) Low-Density Parity-Check (LDPC) Code

Current-mode circuits are presented for implementing analog min-sum (MS) iterative decoders. These decoders are used to efficiently decode the best known error correcting codes such as low-density parity-check (LDPC) codes and turbo codes. The proposed circuits are devised based on current mirrors, and thus, in any fabrication technology that accurate current mirrors can be designed, analog MS decoders can be implemented. The functionality of the proposed circuits is verified by implementing an analog MS decoder for a (32,8) LDPC code in a 0.18-mum CMOS technology. This decoder is the first reported analog MS decoder. For low signal to noise ratios where the circuit imperfections are dominated by the noise of the channel, the measured error correcting performance of this chip in steady-state condition surpasses that of the conventional floating-point discrete-time synchronous MS decoder. When data throughput is 6 Mb/s, loss in the coding gain compared to the conventional MS decoder at BER of 10^-3 is about 0.3 dB and power consumption is about 5 mW. This is the first time that an analog decoder has been successfully tested for an LDPC code, though a short one     

Near-optimum decoding of product codes: block turbo codes

This paper describes an iterative decoding algorithm for any product code built using linear block codes. It is based on soft-input/soft-output decoders for decoding the component codes so that near-optimum performance is obtained at each iteration. This soft-input/soft-output decoder is a Chase decoder which delivers soft outputs instead of binary decisions. The soft output of the decoder is an estimation of the log-likelihood ratio (LLR) of the binary decisions given by the Chase decoder. The theoretical justifications of this algorithm are developed and the method used for computing the soft output is fully described. The iterative decoding of product codes is also known as the block turbo code (BTC) because the concept is quite similar to turbo codes based on iterative decoding of concatenated recursive convolutional codes. The performance of different Bose-Chaudhuri-Hocquenghem (BCH)-BTCs are given for the Gaussian and the Rayleigh channel. Performance on the Gaussian channel indicates that data transmission at 0.8 dB of Shannon's limit or more than 98% (R/C>0.98) of channel capacity can be achieved with high-code-rate BTC using only four iterations. For the Rayleigh channel, the slope of the bit-error rate (BER) curve is as steep as for the Gaussian channel without using channel state information     

一种适用于Turbo译码的新型迭代停止算法

针对Turbo码迭代译码延时大的问题,本文提出了一种加速译码的新型迭代停止方法,该方法利用了两个分量译码器输出的对数似然比LLR(Logarithm Likelihood Ratio)的统计特性,简称为LCB(LLR Characters Based)算法.同现存的经典停止准则相比,在相同的比特误码率性能下,新方法有效的降低了译码平均迭代次数,加速了Turbo码译码,可应用于流媒体信号传输系统.     

Early detection and trellis splicing: reduced-complexity iterativedecoding

The bit-error rate (BER) performance of new iterative decoding algorithms (e,g,, turbodecoding) is achieved at the expense of a computationally burdensome decoding procedure. We present a method called early detection that can be used to reduce the computational complexity of a variety of iterative decoders. Using a confidence criterion, some information symbols, state variables, and codeword symbols are detected early on during decoding. In this way, the computational complexity of further processing is reduced with a controllable increase in the BER. We present an easily implemented instance of this algorithm, called trellis splicing, that can be used with turbodecoding. For a simulated system of this type, we obtain a reduction in the computational complexity of up to a factor of four, relative to a turbodecoder that obtains the same increase in the BER by performing fewer iterations     

Reducing average number of turbo decoding iterations

The average number of decoding iterations in a turbo decoder is reduced by incorporating CRC error detection into the decoding iteration process. Turbo decoding iterations are stopped when CRC decoding determines that there is no error in the decoded data sequence. Computer simulations assuming a turbo-coded W-CDMA mobile radio reverse link under frequency selective Rayleigh fading demonstrate that when the maximum number of iterations is 8, the average number of decoding iterations can be reduced to 1/4 at BER=10^-6     

Experimental Demonstration of Concatenated LDPC and RS Codes by FPGAs Emulation

The concatenation of low-density parity-check and Reed-Solomon codes for forward error correction has been experimentally demonstrated for the first time in this letter. Using a 2-bit soft-decision large-scale integration and high-speed field-programmable gate arrays, a net coding gain of 9.0 dB was achieved with 20.5% redundancy with four iterative decoding for an input bit-error rate of 8.9 times 10^-3 at 31.3 Gb/s.     

1.3-$mu$m Amplifier-Free All-Optical 2R Regenerator Using Two-Mode Injection-Locked Distributed Feedback Laser Diode

This study presents a novel and cost-effective 1.3-mum all-optical 2R regenerator based on a two-mode injection-locked distributed feedback laser diode. The proposed 2R regenerator, with 14.13-dB small signal gain, has achieved an amplifier-free 10-Gb/s straight line transmission over 60 km while keeping the power penalty less than 0.84 dB at bit-error rate (BER) =10^-9. In addition, properties like BER degradation, output extinction ratio, gain, and data-rate transparency are also experimentally investigated     

On combined equalization and decoding of multilevel codedmodulation

We describe an approach to combined equalization and decoding of multilevel block-coded modulation. This approach has better performance than conventional, concatenated equalization and decoding. The proposed structure uses a simple iterative scheme to decode and equalize multilevel block-coded modulation based on decision feedback. We show via computer simulation that the combined scheme gives a performance gain of up to 0.8 dB at a bit-error rate of 10^-4     

BER performance of CMA adaptive array for high-speed GMSK mobilecommunication-a description of measurements in central Tokyo

This paper describes the performance of an adaptive array as a countermeasure to multipath fading for a 256 kbps Gaussian-filtered minimum shift keying (GMSK) mobile communication system operating in the 1.5 GHz band. An adaptive array having four antenna elements is implemented using the digital beam forming concept. The constant modulus algorithm (CMA) is employed for the adaptation process to ease the implementation. Measurements in central Tokyo of the bit error rate (BER) performance and an array pattern arising in the multipath environment are presented. Analysis of the array pattern confirms that the array succeeds in directing nulls to the delayed signals. BER performance shows an improvement in E_b/N₀, compared with that of a single antenna system, of 17.5 to 22 dB at a BER of 1.0×10^-2 in a frequency-selective fading channel     

Turbo码概率-代数联合解码算法

Turbo码采用修正的BAHL et al.算法实现解码.这是一种基于软值的概率迭代解码算法.本文在保持Turbo码迭代软解码算法优点的基础上,充分利用Turbo码编码器结构这一确知条件,结合代数解码原理,提出了一种Turbo码概率-代数联合解码算法.该算法结合了概率解码和代数解码的优点,又有效避免了误差传播的发生,使Turbo码的纠错性能在原经典算法的基础上得到进一步的提高.该算法不仅为降低Turbo码的比特误码率和误差地板值提供了一种新的研究途径,而且因其更好的纠错性能而具有十分明显的实用价值.仿真实验结果显示,在比特误码率(BER)为10^-3~10^-4时,与经典Turbo码解码算法相比,采用该算法能获得0.1dB左右的编码增益.