Mechanism and detection of poly gate leakage with nonvisual defects by voltage contrast inspection

The research aims at nonvisual defects causing the poly gate leakage failure and the corresponding inline voltage-contrast (VC) inspection. Electron beam inspection (EBI) begins to be frequently used for scanning either SRAM or DRAM cell area in nano-scaled technologies. The research, furthermore, extends EBI to logical area of an ASIC product and proposes an inline detectable methodology for gate leakages. Extreme tiny and nonvisual residues could happen during gate etch processes by the step height between active area (AA) and shallow trench isolation (STI), and the tiny defects are difficult to be located even some of those did lead to chip probe (CP) test failure. The subsequent implant processes would punch through those tiny poly residues, make the residue being conductive, and finally electrons on the gate would leak to the ground through the residue. Those nonvisual residues act as bridges for gate leakages. EBI with designed positive charging modes was applied into the series of implement steps and found the leakage by a significant voltage contrast signal post the source/drain implantation. The bright VC of the gate poly implied the leakage electrons charging on the gate. A series of process experiments based on the model for reducing leakages was tested and quickly verified by the EBI in front end of the line. An optimal process integration condition was soon carried out with a significant chip yield enhancement.     

Leakage Current Reduction Techniques for 7T SRAM Cell in 45 nm Technology

In this paper the impact of gate leakage on 7T static random access memory (SRAM) is described and three techniques for reducing gate leakage currents and sub threshold leakage currents are examined. In first technique, the supply voltage is decreased. In the second techniques the voltage of the ground node is increased. While in third technique the effective voltage across SRAM cell Vd = 0.348V and Vs = 0.234V are observed. In all the techniques the effective voltage across SRAM cell is decreased in stand-by mode using a dynamic self controllable voltage level (SVL) switch. Simulation results based on cadence tool for 45 nm technology show that the techniques in which supply voltage level is reduced is more efficient in reducing gate leakage than the one in which ground node voltage is increased. Result obtained show that 437 FA reductions in the leakage currents of 7T SRAM can be achieved.     

The device characteristics of missing LDD implantation via nanoprobing techniques for localized failure analysis

In the recent years, localization of subtle defects has required device electrical data. Nanoprobing systems based on scanning electron microscopy (SEM) or atomic force microscopy (AFM) have become a significant tool for device measurement in failure analysis (FA) Labs. Failure Analysts can use electrical characteristics to isolate failure location in the metal–oxide–semiconductor field-effect-transistor (MOSFET). The missing lightly doped drain (LDD) implant is an example of a critical failure mechanism for the MOSFET and cell in the SRAM which is localized using nanoprobing. In this article, device data analysis and theoretical deductions are discussed related to missing LDD doping. Device data is used to propose a full set of characteristic for missing LDD. The simulation from a mature tool is able to support the electrical characteristics. The capability and challenge of the following physical FA to reveal the defect are also discussed.     

SRAM版图布局方向对产品失效率的影响

静态随机存储器(SRAM)是集成电路中重要的存储结构单元。由于其制备工艺复杂、关键尺寸较小、对设计规则的要求最为严格,因此SRAM的质量是影响芯片良率的关键因素。针对一款微控制单元(MCU)芯片的SRAM失效问题,进行逻辑地址分析确认失效位点,通过离子聚焦束(FIB)切片及扫描电子显微镜(SEM)分析造成失效的异常物理结构,结合平台同类产品的设计布局对比及生产过程中光刻工艺制程的特点,确认失效的具体原因。对可能造成失效的工艺步骤或参数设计实验验证方案,根据验证结果制定相应的改善措施,通过良率测试及SEM照片确认改善结果,优化工艺窗口。当SRAM中多晶硅线布局方向与测试单元中一致时,工艺窗口最大,良率稳定;因此在芯片设计规则中明确SRAM结构布局方向,对于保证产品的良率具有重要意义。     

Low voltage FE-STEM for characterization of state-of-the-art silicon SRAM

Low voltage (30 kV) field emission scanning transmission electron microscopy (FE-STEM) has been employed in the characterization of state-of-the-art semiconductor static random access memory (SRAM) using specimens prepared at several different thicknesses (70-180 nm). A focused ion beam (FIB) system, a FIB-SEM compatible specimen holder and an in-lens FE-SEM have been employed for alternating between FIB milling and SEM/ STEM imaging. As a result, ion implanted atom damage during manufacturing, grains in aluminium interconnects, poly silicon gates, thin metal barriers and a thin gate oxide layer were observed by low voltage FE-STEM. STEM, in-lens FESEM, FIB     

Device-Optimization Technique for Robust and Low-Power FinFET SRAM Design in NanoScale Era

In this paper, we propose a methodology to model and optimize FinFET devices for robust and low-power SRAMs. We propose to optimize the gate sidewall offset spacer thickness to simultaneously minimize leakage current and drain capacitance to on-current ratio in FinFET. With the source/drain extension doping controlled at the outer edges of the spacer, the thickness of the spacer determines the channel length. Optimization reduces the sensitivity of the device threshold voltage to the fluctuations in silicon thickness (by 32%) and gate length (by 73%). Our analysis shows that optimization of spacer thickness results in 65% reduction in SRAM cell leakage and improves cell read-failure probability (by 200 X) compared to conventional FinFET SRAM. Access time of an SRAM cell designed with optimized devices is comparable to conventional SRAM. We also compared the optimized-spacer-thickness SRAM cell with one designed using longer gate length and minimum-spacer-thickness transistors. The long-channel-device-based SRAM cell is marginally robust than optimized SRAM; however, increased gate-edge direct-tunneling leakage and parasitic capacitances degrade the power consumption and access time.     

Subtle gate oxide defect elimination to improve the reliability of a 32M-bit SRAM product

Tiny defects may escape from in-line defect scan and pass WAT (Wafer Acceptance Test), CP (Chip Probing), FT (Final Test) and SLT (System Level Test). Chips with such kind of defects will cause reliability problem and impact revenue significantly. It is important to catch the defects and derive the prevention strategy earlier in the technology development stage. In this paper, we investigate an SRAM with tiny defects which passed in-line defect scan, WAT, CP and FT but failed in HTOL (High Temperature Operation Life) test, one of the product reliability qualification items. FA (Failure Analysis) reveals gate oxide missing defect is the root cause. The goal is to pass reliability qualification and release product into production on schedule. The failure mechanism, optimization of gate oxide process, enhancement of defect scan and testing methodology will be introduced. Experiment results show very good HTOL performance by the combination of process and testing optimization.     

Flex-pass-gate SRAM for static noise margin enhancement using FinFET-based technology

We propose a flex-pass-gate SRAM (Flex-PG SRAM), which is a FinFET-based SRAM to enhance both the read and write margins independently. The flip-flop in the Flex-PG SRAM consists of usual FinFETs, while its pass gates consist of double-“independent”-gate FinFETs, i.e., “four-terminal”- (4T-) FinFETs. A 4T-FinFET has a variable threshold voltage controlled by the second gate voltage. This function enables the Flex-PG SRAM to optimize the current drivability in the pass gates according to operational conditions of read and write. This results in enhancement of both the read and write margins. TCAD simulations revealed that the Flex-PG SRAM increases the read margin by 71 mV without the cell size penalty and decrease in the write margin, even when its 6σ tolerance is ensured. Also, a half-cell experiment proved its feasibility.     

A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications

In sub-100-nm generation, gate-tunneling leakage current increases and dominates the total standby leakage current of LSIs based on decreasing gate-oxide thickness. Showing that the gate leakage current is effectively reduced by lowering the gate voltage, we propose a local dc level control (LDLC) for SRAM cell arrays and an automatic gate leakage suppression driver (AGLSD) for peripheral circuits. We designed and fabricated a 32-kB 1-port SRAM using 90-nm CMOS technology. The six-transistor SRAM cell size is 1.25 /spl mu/m/sup 2/. Evaluation shows that the standby current of 32-kB SRAM is 1.2 /spl mu/A at 1.2 V and room temperature. It is reduced to 7.5% of conventional SRAM.     

Design and Analysis of Two Low-Power SRAM Cell Structures

In this paper, two static random access memory (SRAM) cells that reduce the static power dissipation due to gate and subthreshold leakage currents are presented. The first cell structure results in reduced gate voltages for the NMOS pass transistors, and thus lowers the gate leakage current. It reduces the subthreshold leakage current by increasing the ground level during the idle (inactive) mode. The second cell structure makes use of PMOS pass transistors to lower the gate leakage current. In addition, dual threshold voltage technology with forward body biasing is utilized with this structure to reduce the subthreshold leakage while maintaining performance. Compared to a conventional SRAM cell, the first cell structure decreases the total gate leakage current by 66% and the idle power by 58% and increases the access time by approximately 2% while the second cell structure reduces the total gate leakage current by 27% and the idle power by 37% with no access time degradation.     

Nonvolatile SRAM cell using different capacitance loading

A simple and novel nonvolatile SRAM (NVSRAM) cell is proposed. NVSRAM cell can be achieved by adding only one nonvolatile device with split floating gates to a conventional SRAM cell. It acts as a conventional SRAM cell under normal operation. SRAM cell data are programmed to the nonvolatile device by hot electron injection. At power up, data are restored using different capacitance loading resulting from the split floating gate. The operations have been confirmed by circuit simulation. The NVSRAM cell is symmetric, and therefore has better retention characteristics than other NVSRAM cells     

Performance Comparison of FA,PSO and CS application in SINR Optimisation for LCMV Beamforming Technique

A beamforming technique called Linearly Constraint Minimum Variance (LCMV) allows directing a radiation beam towards the desired direction to minimise interference of the signal through weight vectors that are computed by LCMV. Generally, to achieve a favourable beam shape, LCMV’s weights are not exactly steered towards the user’s direction. In addition, traditional methods are not equipped well to seamlessly improve the weights of LCMV. This paper employs Particle Swarm Optimisation (PSO), Firefly Algorithm (FA) and Cuckoo Search (CS) to optimise the weights of LCMV. The key anticipated goal in LCMV optimisation is the power reduction on the interferences’ side to achieve a favourable beam shape and better SINR output. A common metaheuristic algorithm is Particle Swarm Optimisation (PSO), which deals with the social behaviour of creatures such as bird flocking. A population and attraction-based algorithm is employed in Firefly algorithm; the flashing characteristics of fireflies are the inspiration of the swarm intelligence metaheuristic algorithm. Also, a novel equation-based nature inspired algorithm is Cuckoo Search (CS), which is based on the brood parasitism of a few cuckoo species combined with the so-called Lévy flights. Based on simulation results, FA showed enhanced ability to precisely determine power allocation’s optimal direction when compared with CS and PSO. Thus, better SINR results could be achieved with FA. For SINR optimisation using the LCMV technique, the effectiveness of CS in comparison with FA and PSO algorithms was simulated employing MATLAB^®.     

Chaotic oscillations in electron beam with virtual cathode in external magnetic field

This article presents the results of a numerical study of external magnetic field influence on the conditions and mechanisms of virtual cathode (VC) formation in a relativistic electron beam. It also considers other related issues, e.g. peculiarities of nonlinear dynamics of electron beam with VC under changed external magnetic field, different mechanisms of VC oscillation chaotisation leading to complication of vircator system dynamics and appearance of multi-frequency VC oscillations. General systemic mechanism of VC oscillation chaotisation has been identified which is connected with formation of electronic patterns in electron beam whose interaction in the common field of spatial charge determines appearance of additional inner feedback. Transition from chaotic to periodical oscillation regime is found to be connected with destroying the mechanism of secondary electronic structures (electron bunches) formation. Besides, the influence of extent of screening of electron gun from magnetic field is discussed.     

Power Optimization for SRAM and Its Scaling

With technology scaling, there is a strong demand for smaller cell size, higher speed, and lower power in SRAMs. In addition, there are severe constraints for reliable read-and-write operations in the presence of increasing random variations that significantly degrade the noise margin. To understand these tradeoffs clearly and find a power-delay optimal solution for scaled SRAM, sequential quadratic programming is applied for optimizing 6-T SRAM for the first time. The use of analytical device models for transistor currents and formulate all the cell-operation requirements as constraints in an optimization problem. Our results suggest that, for optimal SRAM cell design, neither the supply voltage (V_dd) nor the gate length (L_g) scales, due to the need for an adequate noise margin amid leakage and threshold variability and relatively low dynamic activity of SRAM. This is true even with technology scaling. The cell area continues to scale despite the nonscaling gate length (L_g) with only a 7% area overhead at the 22-nm technology node as compared to simple scaling, at which point a 3-D structure is needed to continue the area-scaling trend. The suppression of gate leakage helps to reduce the power in ultralow-power SRAM, where subthreshold leakage is minimized at the cost of increase in cell area     

具有应变沟道及EOT 1.2nm高性能栅长22nm CMOS器件

深入研究了亚30nm CMOS关键工艺技术，特别是提出了一种新的低成本的提高空穴迁移率的技术--Ge预非晶化S/D延伸区诱生沟道应变技术，它使栅长90nm pMOS空穴有效迁移率在0.6MV/cm电场下提高32%. 而且空穴有效迁移率的改善，随器件特征尺寸缩小而增强. 利用零阶劳厄线衍射的大角度会聚束电子衍射分析表明，在沟道区相应的压应变为-3.6%. 在集成技术优化的基础上，研制成功了高性能栅长22nm应变沟道CMOS器件及栅长27nm CMOS 32分频器电路（其中分别嵌入了57级/201级环形振荡器）, EOT为1.2nm,具有Ni自对准硅化物.     

New method for boron removal from silicon by electron beam injection

A new method for boron removal from silicon using electron beam injection (EBI) is proposed. After thermal oxidation on monocrystalline silicon (100) wafer at 1000 °C for 1 h, EBI was used to induce thermal and negative charging effects to enhance boron diffusion in the oxide film and the silicon substrate. This facilitates boron removal from the silicon substrate. The boron concentration in samples was measured by secondary ion mass spectrometry. The results show that EBI reduced the boron concentration in the silicon substrate by 4.83%.     

Technologies for electron beam direct writing

Development time of semiconductor devices which have a large volume of pattern data and fine feature size can be remarkably reduced by a high speed on-line system and an erase electron beam direct writing technology.Pattern data which is performed by a CAD system is converted by a VAX/780 and transmitted to an electron beam exposure system (EBES) through a communication controller at the speed of 1 Mbit/sec.Overlay accuracy less than 0.2 μm is obtained by scanning the alignment marks located at the periphery of a silicon wafer. The marks are fabricated by etching the silicon substrate to 2 μm depth.Radiation effects induced by electron beam irradiation is examined by Monte Carlo simulation.In production of ECL (emitter coupled logic) gate arrays using electron beam direct writing technology, the surface of the silicon nitride (SiN) interlevel insulation layer is coated with a thin conductive layer of TiW in order to avoid the charging phenomenon and the radiation damage caused by electron beam irradiation.     

Analysis and design of low power SRAM cell using independent gate FinFET

Scaling of bulk MOSFET faces great challenges in nanoscale integration technology by producing short channel effect which leads to increased leakage. FinFET has become the most promising substitute to bulk CMOS technology because of reducing short channel effect. Dual-gate FinFET can be designed either by shorting gates on either side for better performance or both gates can be controlled independently to reduce the leakage and hence power consumption. A six transistor SRAM cell based on independent-gate FinFET technology is described in this paper for simultaneously reducing the active and standby mode power consumption. A work is focused on the independent gate FinFET technology as this mode provides less power consumption, less area consumption and low delay as compared to other modes. Leakage current and power consumption in independent gate FinFET is compared with tied gate or shorted gate FinFET SRAM cell. Moreover, delay has been estimated in presented SRAM cells. Further, leakage reduction technique is applied to independent gate FinFET 6T SRAM cell.     

Measurements of gate voltage dependence of electron mobility inδ-doped HFET's

The results of the measurements of the gate voltage dependence of the electron mobility in heterostructure field effect transistors (HFETs) using a split C-V technique are discussed. This method allows one to deduce this dependence without making any assumptions about other parameters such as the threshold voltage. The dependence of the electron mobility in the HFET channel on the gate voltage depends on the heterointerface quality. In some samples, the mobility increases with the increase of the gate voltage. In other samples (grown on a different molecular beam epitaxy machine), the mobility drops to nearly a half of its maximum value at high gate voltages. This means that, in these samples, the electron mobility is strongly dependent on the transverse electric field (similar to analogous behavior in p- and n-channel MOSFETs)     

Leakage Minimization of SRAM Cells in a Dual-$V_t$ and Dual-$T_{rm ox}$ Technology

Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicrometer regime. As a result, reducing the subthreshold and tunneling gate leakage currents has become one of the most important criteria in the design of VLSI circuits. This paper presents a method based on dual- V t and dual- T _ox assignment to reduce the total leakage power dissipation of static random access memories (SRAMs) while maintaining their performance. The proposed method is based on the observation that read and write delays of a memory cell in an SRAM block depend on the physical distance of the cell from the sense amplifier and the decoder. Thus, the idea is to deploy different configurations of six-transistor SRAM cells corresponding to different threshold voltage and oxide thickness assignments for the transistors. Unlike other techniques for low-leakage SRAM design, the proposed technique incurs neither area nor delay overhead. In addition, it results in a minor change in the SRAM design flow. The leakage saving achieved by using this technique is a function of the values of the high threshold voltage and the oxide thickness, as well as the number of rows and columns in the cell array. Simulation results with a 65-nm process demonstrate that this technique can reduce the total leakage power dissipation of a 64 times 512 SRAM array by 33% and that of a 32 times 512 SRAM array by 40%.