SiO_2/SiC界面陷阱对SiC MOSFET开关损耗的影响

位于SiO_2/SiC界面处密度较高的陷阱,不仅俘获SiC MOSFET沟道中的载流子,而且对沟道中的载流子形成散射、降低载流子的迁移率,因而严重影响了SiC MOSFET的开关特性。目前商业化的半导体器件仿真软件中迁移率模型是基于Si器件开发,不能体现SiO_2/SiC界面处的陷阱对沟道中载流子的散射作用。通过引入能正确反映界面陷阱对载流子作用的迁移率模型,利用半导体器件仿真软件研究了界面陷阱对SiC MOSFET动态特性的影响。结果表明,随着界面陷阱密度的增加,SiC MOSFET开通过程变慢,开通损耗增加,而关断过程加快,关断损耗减小;但是由于沟道载流子数量的减少、导通电阻的增加,总损耗是随着界面陷阱密度的增加而增加。     

常关型亚微米沟道1200V SiC MOSFET

<正>南京电子器件研究所基于自主12um外延和76.2 mm(3英寸)SiC圆片加工工艺,通过介质刻蚀沟道自对准技术,在国内率先实现了导通电流大于5 A的SiC DMOSFET,阻断电压大于1 200 V,阈值电压5 V。     

高电流增益SiC BMFET功率特性的优化研究

研究了栅电流及结构参数对SiC双极模式场效应晶体管(BMFET)功率特性的影响。仿真研究的结果表明,SiC BMFET器件的开态电阻和电流增益都会随着栅电流的上升而显著下降。沟道掺杂浓度越低,沟道宽度越窄,双极模式调制器件开态电阻的效果越明显,但同时电流增益会降低。相比于单极模式SiC结型场效应晶体管(JFET),SiC BMFET可以显著提升器件的FOM优值,降低器件功率特性对结构参数的敏感度,同时降低了常关型器件的设计难度。     

对表面势为基础的MOSFET片电荷模型的基本检验

本文完成了对多种表面势为基础的MOSFET片电荷(charge-sheet)模型反型层电荷和沟道电流计算的基本检验.相对于以基本的MOSFET器件物理为基础的Pao-Sah模型结果,大多数片电荷模型在不同的工作区域内都会出现不同程度的反型层电荷计算误差.为了模拟沟道电流,MOSFET片电荷模型必须使用一个半经验的沟道电流方程.这个近似会导致沟道电流方程和反型层电荷方程之间物理上的不自恰,从而使计算的沟道电流结果与Pao-Sah模型相比有近10%的误差.这些基本的检验结果表明:为了保持基本的MOSFET器件物理内容和Pao-Sah模型的高精度,以表面势为基础的片电荷模型还需要一些根本的器件物理改进和进一步的模型精度提高.     

SiO2/4H-SiC界面氮化退火

通过1 300℃高温干氧热氧化法在n型4H-SiC外延片上生长了厚度为60 nm的SiO2栅氧化层.为了开发适合于生长低界面态密度和高沟道载流子迁移率的SiC MOSFET器件产品的栅极氧化层退火条件,研究了不同退火条件下的SiO2/SiC界面电学特性参数.制作了MOS电容和横向MOSFET器件,通过表征SiO2栅氧化层C-V特性和MOSFET器件I-V特性,提取平带电压、C-V磁滞电压、SiO2/SiC界面态密度和载流子沟道迁移率等电学参数.实验结果表明,干氧氧化形成SiO2栅氧化层后,在1 300℃通入N2退火30 min,随后在相同温度下进行NO退火120 min,为最佳栅极氧化层退火条件,此时,SiO2/SiC界面态密度能够降低至2.07×1012 cm-2·eV-1@0.2 eV,SiC MOSFET沟道载流子迁移率达到17 cm2·V-1·s-1.     

SiC新一代电力电子器件的进展(续)

5 SiC JFETSiC JFET利用p-n结耗尽区来控制沟道电流,可全面开发SiC的高温性能,适合高温高功率开关。SiC JFET通常是常开的,关断需加负栅压,其具有本征安全的栅驱动控制。SiC JFET具有低开关损耗、高开关频率的特点。1999年,P.Friedrichs等人[46]研发了第一代4H-SiC JFET,浪涌电流能力为200 A/cm2,到2004年经历三代SiC JFET技术     

具有温度稳定性的SiC CMOS运算放大器的设计

设计了具有温度稳定性的SiC CMOS运算放大器.根据所希望的IDSat(ZTC)和任一节点泄漏电流为零的原则设计偏置电路;输入采用差分输入,同时按照泄漏电流匹配的原则,合理选取Dcomp的面积.Si MOS器件电源电压为5 V,采用TSMC 0.25 μm工艺制作.当温度从300 K变化到600 K时,SiC 运放的增益和相位裕度的变化率分别为2.5%和3.3%,而Si电路的增益从300 K的64 dB降到-80 dB,失去电路的稳定性.但是,由于SiC MOS器件沟道迁移率低,导致器件的跨导低于相同尺寸下的Si器件,所以其开环增益也小于相同结构和尺寸的Si运算放大器.     

多晶硅TFT热载流子效应的模拟研究

热载流子效应引起的器件电学特性退化会严重影响电路的工作性能。文章结合多晶硅薄膜晶体管沟道电流的理论模型,讨论了热载流子效应与界面陷阱的关系。沟道载流子在大的漏电场牵引下,运动到漏结附近获得很大的能量从而成为热载流子。如果热载流子能量超过Si-SiO2界面势垒高度,会注入到栅氧层或陷落到界面陷阱,使阈值电压和沟道电流发生退化现象。同时,对多晶硅薄膜晶体管输出特性进行了模拟分析,模拟结果与理论模型基本一致。     

栅控二极管R-G电流法表征SOI-MOS器件埋氧层界面陷阱的敏感性分析

通过数值模拟手段,用归一化的方法研究了界面陷阱、硅膜厚度和沟道掺杂浓度对R-G电流大小的影响规律.结果表明:无论在FD还是在PD SOI MOS器件中,界面陷阱密度是决定R-G电流峰值的主要因素,硅膜厚度和沟道掺杂浓度的影响却因器件的类型而异.为了精确地用R-G电流峰值确定界面陷阱的大小,器件参数的影响也必须包括在模型之中.     

SiC-MOS界面优化的工艺验证及MOSFET电学特性仿真拟合

SiC因其优越的电学特性,已发展成为高压功率器件领域的翘楚。然而,SiC与SiO₂界面存在高密度界面态,使得SiC MOSFET沟道迁移率远低于SiC材料本身的体迁移率,大大约束了SiC材料本身电学性能的发挥。为改善反型层沟道迁移率,不同功率器件厂商采用了不同的栅极氧化工艺,所实现的栅极氧化层界面态密度各有不同,现有的功率器件仿真软件提供的多种界面态能级分布模型都需要芯片厂商实际的流片数据作为支撑,这对功率器件上游设计人员产生了阻碍。基于此,文章通过流片测试数据,结合TCAD仿真软件给出了一种用于SiC MOSFET器件仿真的界面态能级分布模型。利用给出的界面态能级分布模型,与实际产品对比,仿真得出的I-V曲线与测试曲线基本重合。     

超高压器件界面电荷诱发击穿电压退化的改善

本研究提出了一种创新的P型表面掺杂工程技术,可专门应用于仿真程序时,优化布局中具交互指叉(interdigital)几何图案的器件结构内,不同区域的PN结反向击穿电压退化现象。如:超高压器件的源极中心(Source Center)、漏极中心(Drain Center)、或是平坦区(flat region)。超高压器件的工艺中,PN结反向击穿电压的退化往往归咎于界面陷阱电荷(interface-trapped charge)。而在硅晶圆阶段中,由于封装等级(package level)可靠度测试(reliability test)所带来的热应力,亦可使击穿电压退化与电流拥挤(current crowding)等现象浮现。因此,在优化的过程中,为了保有器件的高击穿电压特性,吾人藉由改变P型表面掺杂的二维几何设计,同时也利用静电放电测试(ESD test),来观察界面陷阱电荷,在器件遭受静电放电攻击后的分布变化。本研究最终针对具备最大长度结构(length structure)的P型表面掺杂,在击穿电压操作范围内,以及静电放电测试中,如何得到更佳的稳定性,作深入探讨。     

一种用于分离pMOS器件热载流子应力下氧化层陷阱电荷和界面陷阱电荷对阈值电压退化作用的方法

在电荷泵技术的基础上,提出了一种新的方法用于分离和确定氧化层陷阱电荷和界面陷阱电荷对pMOS器件热载流子应力下的阈值电压退化的作用,并且这种方法得到了实验的验证.结果表明对于pMOS器件退化存在三种机制:电子陷阱俘获、空穴陷阱俘获和界面陷阱产生.需要注意的是界面陷阱产生仍然是pMOS器件热载流子退化的主要机制,不过氧化层陷阱电荷的作用也不可忽视.     

一种用于分离pMOS器件热载流子应力下氧化层陷阱电荷和界面陷阱电荷对阈值电压退化作用的方法

在电荷泵技术的基础上,提出了一种新的方法用于分离和确定氧化层陷阱电荷和界面陷阱电荷对p MOS器件热载流子应力下的阈值电压退化的作用,并且这种方法得到了实验的验证.结果表明对于p MOS器件退化存在三种机制:电子陷阱俘获、空穴陷阱俘获和界面陷阱产生.需要注意的是界面陷阱产生仍然是p MOS器件热载流子退化的主要机制,不过氧化层陷阱电荷的作用也不可忽视.     

Snapback应力对90nm nMOSFET栅氧化层完整性的影响

基于测试对snapback应力引起的栅氧化层损伤特性和损伤位置进行了研究．研究发现应力期间产生的损伤引起器件特性随应力时间以近似幂指数的关系退化．应力产生的氧化层陷阱将会引起应力引起的泄漏电流增加，击穿电荷减少，也会造成关态漏泄漏电流的退化．栅氧化层损伤不仅在漏区一侧产生，而且也会在源区一侧产生．热空穴产生的三代电子在指向衬底的电场作用下向Si-SiO2界面移动，这解释了源区一侧栅氧化层损伤的产生原因．     

Snapback应力对90nm nMOSFET栅氧化层完整性的影响

基于测试对snapback应力引起的栅氧化层损伤特性和损伤位置进行了研究.研究发现应力期间产生的损伤引起器件特性随应力时间以近似幂指数的关系退化.应力产生的氧化层陷阱将会引起应力引起的泄漏电流增加,击穿电荷减少,也会造成关态漏泄漏电流的退化.栅氧化层损伤不仅在漏区一侧产生,而且也会在源区一侧产生.热空穴产生的三代电子在指向衬底的电场作用下向Si-SiO2界面移动,这解释了源区一侧栅氧化层损伤的产生原因.     

Source and drain resistance determination for MOSFET's

A new method has been developed for determining the source and drain resistances of MOSFET's from 2-D process and device modeling. The method connects the current predicted from a standard drain current formula to an approximate current computed from the output of a 2-D device simulator. This approximate current is compared with the exact current calculated from the 2-D device simulator to locate the effective edges of the inversion channel. The source/drain resistance for use in the standard formula is then computed from the quasi-Fermi levels at these effective channel edges. Good agreement is obtained with source/drain resistances extracted from experimental ID-VG data.     

A new empirical nonlinear model for sub-250 nm channel MOSFET

An empirical nonlinear model for sub-250 nm channel length MOSFET is presented which is useful for large signal RF circuit simulation. Our model is made of both analytical drain current and gate charge formulations. The drain current expression is continuous and infinitely derivable, and charge conservation is taken into account, as the capacitances derive from a single charge expression. The model's parameters are first extracted, prior the model's implementation into a circuit simulator. It is validated through dc, ac, and RF large signal measurements compared to the simulation.     

An analytical DC model for the modulation-doped field-effect transistor

A novel analytical dc model for the MODFET device is introduced. The model is based on the approximate equations obtained for the 2DEG charge density under the equilibrium and current conduction conditions. The electron charge mobility and velocity-electric field characteristics in the device channel are modeled using semi-empirical expressions in order to obtain the current-voltage drain characteristics that are related directly to the physical parameters of the device structure and its ambient temperature. The calculated current-voltage characteristics using the developed model compare well with the experimental results obtained for a low-noise microwave MODFET at different temperatures. It is believed that due to the model simplicity, it is suitable for implementation in the existing microwave CAD packages.     

A charge sheet model for MOSFETs with an abrupt retrograde channel: Part II. Charges and intrinsic capacitances

The 16 intrinsic capacitance components related to the gate, source, drain and depletion charges are examined for MOSFETs with an ideally abrupt retrograde doping profile in the channel, based on the analytical solutions for the drain current and body charge in the preceding paper. Though lengthy and complex in their final mathematical expressions, analytical solutions for the capacitances can be obtained. The validity of the analytical solutions is confirmed by comparing the modeling results with simulation data obtained using numerical calculations. The inclusion of an intrinsic surface layer in the channel merely causes a simple voltage shift for the capacitances that are not associated with the depletion charge or body bias, similarly to the variation of the drain current shown in the preceding paper. For the capacitances that are related to the depletion charge or body bias, there is not only a parallel voltage shift with an amount commensurate to the shift in drain current as well as in the other capacitances, but also a decrease in their values. This decrease depends on the thickness of the intrinsic surface layer and it amounts to 25% for a surface layer of 30 nm thickness.     

Incomplete charge transfer in IGFET bucket-brigade shift registers

The time evolution of the charge transfer during one half-cycle of operation of an IGFET bucket-brigade dynamic shift register is calculated analytically for a smooth but otherwise arbitrary voltage driving function. Wentzel-Kramers-Brillouin-Jeffreys (WKBJ) solutions to the charge transfer equation are matched to Airy-function solutions in the current cutoff region to determine the charge transferred as a function of initial charge. This directly gives several contributions to the incomplete transfer parameter α, the rate of change of the charge left behind on transfer with the initial charge. Although the increment of charge not completely transferred is less than 1 percent of the charge comprising the signal, the calculation is done so that no subtraction of nearly equal large numbers is necessary. We do not evaluate the actual loss of charge due to leakage, traps, recombination, etc. It is found that the finite dynamic drain conductance of an IGFET makes a major contribution to the parameter α, and that under many experimental conditions it will limit shift-register performance. It is also found that all contributions to α depend on the clock-voltage wave-form. Comparison is made with the results of preliminary experiments, and good qualitative and reasonable quantitative agreement is obtained.