Three-step heuristic algorithm for optimal PLA column folding

A three-step heuristic algorithm for PLA column folding is presented, which is significantly faster than the earlier works and provides nearly optimal results. The three steps are: (i) min-cut partition of vertices in the column intersection graph; (ii) determination of product order using Fiduccia's min-net cut algorithm; and (iii) head-tail pairing for deciding column folding pairs     

Maximizing pin alignment in semi-custom chip circuit layout

We consider the problem of logically permuting pins of a semi-custom chip circuit layout in order to maximize the number of connections that can be realized in the polysilicon layer. As the problem is NP-hard, we present an infinite hierarchy of heuristics, including an algorithm which produces an optimal solution. The heuristics can be tuned to yield approximate solutions of varying degree, as well as an optimal solution. The tradeoff lies in the length of runtime. We have implemented the procedures and demonstrate their behavior with one real and various randomly generated examples.     

FPGA引脚分配方案的分析与改进

本文研究了二分图算法和蚁群算法,在FPGA引脚分配上的应用,这两种算法各有优缺点。本文在这两种算法的基础上提出了一种混合算法,用于提高FPGA引脚分配的效率。经过验证得知,混合算法能有效提高FPGA引脚的实际分配效率。     

全光网中基于跳数的波长分配算法

在有波长连续性限制的情况下,减少波长预留冲突需要在波长预留时尽量使用不同的波长,这使全网的空闲波长数减少,容易导致大跳数光路的连接请求失败。解决波长预留冲突问题的大多数算法都把解决问题的目标设为降低网络阻塞率,无法兼顾网络中大跳数光路的情况。本文提出了用于全光网中基于跳数的波长分配算法,该算法通过建立跳数与波长之间的相互对应关系,对未来可能发生预留冲突的光路及其要预留的波长进行预测,根据预测尽量使用相同波长,增加全网的空闲波长数。在解决波长预留冲突问题的同时,实现支持大跳数光路连接请求的目标。     

An adaptive link assignment algorithm for dynamically changingtopologies

An adaptive link assignment algorithm for the distributed optimization of dynamically changing network topologies is presented. The algorithm is responsible for determining the network connectivity by controlling the selection of links to be established and disconnected. This algorithm is designed to recover from predictable link outages as well as massive unpredictable failures. To minimize computational time complexity as well as to improve transient response. Some known graph-theoretic algorithms are utilized     

一种新型基于子图的波长转换器配置算法

文章在已有的"子图+ADD(代数决策图)"波长转换器配置算法的基础上,将节点在路由上的平均中心距离作为权值对节点进行排序,提出了用优先配置中心节点的启发式思想对该算法进行优化,得到了新的算法,即"子图+CNF(中心节点优先分配)"算法。对本算法进行计算机仿真,结果显示新算法在保证结果准确的同时,有效降低了运算的时间复杂度。     

一种网络备用资源的集中规划算法

满足多级生存性要求的网络带宽资源规划问题是一个存在多个非线性不等式约束的整数规划问题,本文提出了一种考虑移动工作通道对胆识物资源规划算法,并采用拉格朗日松驰法和次梯度法求解该规划问题。     

TBF分配算法优化

EDGE业务的快速发展,导致2G网络综合利用率高位运行。通过对现网数据的分析,发现可以通过提高PDCH复用度以大幅节省载频资源。针对因大量低速率业务占用引起的PDCH信道承载速率低的问题,提出了一种新的TBF资源分配方法。通过此方法的应用,可缓解低速率业务带来的网络压力,提升PDCH承载速率,提高网络承载效率。     

A four-processor building block for SIMD processor arrays

A four-processor chip, for use in processor arrays for image computations, is described. The large degree of data parallelism available in image computations allows dense array implementations where all processors operate under the control of a single instruction stream. An instruction decoder shared by the four processors on the chip minimizes the pin count allocated for global control of the processors. The chip incorporates an interface to an external SRAM (static RAM) for memory expansion without glue chips. The full-custom 2-μm CMOS chip contains 56669 transistors and runs instructions at 10 MHz. Five hundred and twelve 16-b processors and 4 Mbyte of distributed external memory fit on two industry standard cards to yield 5-billion instructions per second peak throughout. As image I/O can overlap perfectly with pixel computation, an array containing 128 of these chips can provide more than 600 16-b operations per pixel on 512×512 images at 30 Hz     

Low power building block for artificial neural networks

The authors propose and analyse a low-power CMOS building block for artificial neural networks (ANNs) that can function either as a synapse or a neuron. The design is based on the current-mode approach and uses the square-law characteristics of a MOS transistor working in saturation. The new building block uses I-V converters, a current-mirror and a ±1 V power supply to achieve superior performance. Modularity, ease of interconnectivity, expandability and reconfigurability are the advantages of this building block     

单位增益段

如前所述,利用单位增益段这一概念来设计电缆电视系统。 考虑图2.59所示电缆电视系统的一条干线。注意,全部放大器具有同一输入电平和同一输出电平,因为电缆段的损耗相同。这产生具有单位增益的电缆放大器段,它是干线的构成单元。以前的例子只说明CATV的干线系统。干线电缆是把信     

A two-dimensional placement algorithm for the layout of electronic circuits

A method is developed for the optimal placement of components or subsystems to specific locations on the backboard. The objective is to minimize the number of etches passing through unit space on the board (interconnection density) and the number of holes. This avoids the congested area on the board, makes a proper distribution of wiring and reduces the stray capacitances. X-Y coordinate wiring has been used.     

OVSF码分配算法研究

提出1种优先选择极左碎片的信道化码分配算法,该算法用很简单的方式降低了码阻塞率。将新算法与已有的极左法和权重法进行比较,理论分析和计算机仿真表明,极左碎片法具有与极左法相近的简单性,在码阻塞率和公平性方面几乎与权重法一样好,是简单、高效和公平的综合性能最好的算法。该算法可应用于以OVSF码作为信道化码的各种DS-CDMA系统。     

WDM-PON的动态波长分配算法

介绍了基于动态波长分配的WDM-PON的运行原理,结合已有算法的优缺点,提出了一种新的区分业务等级的动态带宽分配算法.新算法对不同的业务区分等级,并把波长资源优先分配给高优先级,在保证服务质量的下提高了上行带宽的利用率.     

解决频率指配问题的蚁群算法

将蚁群算法和经典的四级预测模型结合使用,解决了大规模电台数目电子信息系统的频率指配问题.此类问题的数学模型与传统问题不同.提出针对该问题的算法性能评估准则,并研究了各参数对算法性能的影响.依据对研究结果的分析,提出优化参数的设定准则.     

基于动态最大传输窗口的带宽分配算法研究

数据业务和话音业务是未来网络中两个重要业务.作为下一代宽带接入的有效解决方案,以太网无源光网络(EPON)为用户提供了业务接口.对EPON中的上行带宽分配算法进行了分析研究,并提出一种基于动态最大传输窗口 DMTW 的 EPON 上行带宽分配算法.在本算法中根据业务和用户的优先级动态调整最大的传输窗口,合理分配上行带宽的资源,提高信道利用率和QoS,降低了传输时延.最后通过软件进行仿真,验证了算法的有效性.     

Adaptive Chase algorithm for block turbo codes

A new adaptive implementation of the Chase algorithm for binary block codes is proposed. Compared to the two efficiently used algorithms for iterative decoding, the standard Chase and Kaneko algorithms, the proposed algorithm can give the same performance with significant complexity reduction.     

Signal through-the-silicon via planning and pin assignment for thermal and wire length optimization in 3D ICs

Signal through-the-silicon via (STS-via) planning plays an important role in multi-layer nets which need vertical interconnection between different device layers. Moreover, STS-via can also dissipate heat, which is a much more serious problem in 3D ICs than in 2D ICs. Since the through-the-silicon via is large and can only be inserted into whitespace of the device layer, planning STS-via for thermal optimization may affect the interconnection wire length. Therefore, in order to make STS-via planning more flexible, we integrated STS-via with pin assignment. In this paper, we use min-cost maximum flow algorithm for STS-via planning and pin assignment simultaneously. Experimental results show that our approach can reduce both temperature and wire length effectively with short runtime.     

Adaptive block matching algorithm for video compression

A simple adaptive block matching algorithm for video coding is presented. In the proposed algorithm, a matching criterion called bit-plane matching is proposed to sort out a number of blocks with unlikely directive information to the test block from the search window. An adaptive searching method is developed to further improve the computational effectiveness of the system. In this searching method the search origin, search range and pixel subsampling ratio can be adjusted according to the motion content of the block. Simulation results show that the proposed algorithm achieves MSE performance to the full-search and about 92-95% savings in computation     

协同项目多目标任务分配优化算法

在协同项目中，伙伴企业间的任务分配问题直接影响到项目的整体获益。针对这一问题，以费用最小和承担企业数最少为目标，并充分考虑了任务之间的紧密关联关系，提出了一个有效的任务分配启发式算法，并进行了实例验证，给出了对算法的评价。