Measurement of V/SUB CE(sat)/ of RF power transistors and of waveform details near V/SUB CE(sat)/

Accurate measurement of V/SUB CE(sat)/ in RF operation and of the waveform details near V/SUB CE(sat)/ requires that the oscilloscope vertical deflection sensitivity be high enough so that the waveform peak value would drive the amplifier far off-scale. With many oscilloscopes, the deflection amplifier does not recover fast enough for the resulting on-screen display to be undistorted. The wideband waveform clipper described allows accurate measurement of V/SUB CE(sat)/ and the waveform details near V/SUB CE(saT)/ without overloading the oscilloscope vertical deflection amplifier.     

Stable extraction of linearity (V/sub IP3/) for nanoscale RF CMOS devices

We have proposed an improved and stable algorithm for linearity (V/sub IP3/) extraction by setting an optimized measurement node interval. This algorithm, considering the accuracy of measurement appliances, provides less noisy V/sub IP3/ without loss of details. Adopting it, V/sub IP3/ can be derived satisfying 1% error criterion. Accurate V/sub IP3/ extraction can be a strong help in CMOS performance analysis for the RF applications. Measurements were carried out on a nMOSFET.     

Impacts of gate electrode materials on threshold voltage (V/sub th/) instability in nMOS HfO/sub 2/ gate stacks under DC and AC stressing

Ultrathin nMOSFET hafnium oxide (HfO/sub 2/) gate stacks with TiN metal gate and poly-Si gate electrodes are compared to study the impact of the gate electrode on long term threshold instability reliability for both dc and ac stress conditions. The poly-Si/high-/spl kappa/ interface exhibits more traps due to interfacial reaction than the TiN/high-/spl kappa/ interface, resulting in significantly worse dc V/sub th/ instability. However, the V/sub th/ instability difference between these two stacks decreases and eventually diminishes as ac stress frequency increases, which suggests the top interface plays a minor role in charge trapping at high operating frequency. In addition, ac stress induced interface states (Nit) can be effectively recovered, resulting in negligible G/sub m/ degradation.     

Structural advantage for the EOT scaling and improved electron channel mobility by incorporating dysprosium oxide (Dy/sub 2/O/sub 3/) into HfO/sub 2/ n-MOSFETs

A structural approach of fabricating laminated Dy/sub 2/O/sub 3/-incorporated HfO/sub 2/ multimetal oxide dielectric has been developed for high-performance CMOS applications. Top Dy/sub 2/O/sub 3/ laminated HfO/sub 2/ bilayer structure shows the thinnest equivalent oxide thickness (EOT) with a reduced leakage current compared to HfO/sub 2/. This structure shows a great advantage for the EOT scaling CMOS technology. Excellent electrical performances of the Dy/sub 2/O/sub 3//HfO/sub 2/ multimetal stack oxide n-MOSFET such as lower V/sub T/, higher drive current, and an improved channel electron mobility are reported. Dy/sub 2/O/sub 3//HfO/sub 2/ sample also shows a better immunity for V/sub t/ instability and less severe charge trapping characteristics. Two different rationed Dy/sub 2/O/sub 3//HfO/sub 2/ and HfO/sub 2/ n-MOSFET were measured by charge-pumping technique to obtain the interface state density (D/sub it/), which indicates a reasonable and similar interface quality. Electron channel mobility is analyzed by decomposing into three regimes according to the effective field. Reduced phonon scattering is found to be the plausible mechanism for higher channel mobility.     

Threshold voltage (V/sub th/) instability in HfO/sub 2/ high-/spl kappa/ gate stacks with TiN metal gate: comparison between NH/sub 3/ and O/sub 3/ interface treatments

The impacts of O/sub 3/ or NH/sub 3/ interface treatments on the long-term V/sub th/ instability in nMOSFET HfO/sub 2/ high-/spl kappa/ gate stacks with TiN metal gate electrodes are compared. The NH/sub 3/ interface treatment is found to be beneficial to suppress the V/sub th/ shift compared to the O/sub 3/-treated samples. This is explained by an enhanced valence band electrons injection in O/sub 3/-treated samples and is experimentally confirmed through a carrier separation measurement. The dynamic stress measurement also indicates that trapped charges are more easily detrapped in NH/sub 3/-treated samples than O/sub 3/-treated samples, improving significantly the V/sub th/ stability.     

High gain-bandwidth differential distributed InP D-HBT driver amplifiers with large (11.3 V/sub pp/) output swing at 40 Gb/s

High-performance and compact 40-Gb/s driver amplifiers were realized in 1.2-/spl mu/m emitter double-heterojunction InGaAs-InP HBT (D-HBT) technology with a maximum cut-off frequency (f/sub T/) of 150 GHz and a maximum oscillation frequency (f/sub max/) of 200 GHz. Two-stage differential drivers feature a lumped input and fully distributed output stage and deliver a maximum differential output swing of 11.3 V peak-to-peak (V/sub pp/) at 40 Gb/s with less then 350 fs of added rms jitter and rise and fall times of about 7 ps while consuming a total power of 3 W. When biased at a lower output swing of 6.3 V/sub pp/, excellent 40-Gb/s eyes with a 7-ps fall time, 6-ps rise time, and no observable jitter deterioration compared with the input source are obtained at a reduced power consumption of 1.7 W. On-wafer measured differential S-parameters show a differential gain of 25 dB, 50 GHz bandwidth, and input and output reflection below -20 dB from 2 to 45 GHz. The amplifiers' small die size (1.0/spl times/1.7 mm), relatively low power consumption, large output swing, and ability to have dc coupled inputs and outputs enable compact 40-Gb/s optical transmitters with good eye opening for both conventional transmission formats such as nonreturn-to-zero and return-to-zero and alternative formats such as duobinary and differential phase shift keying.     

Super gain beamformer (N/sup 3/) for source power and bearing estimation

An improved super gain beamformer is presented for evaluating the source powers and bearings of the received signals at a sensor array. The processor gain is not limited to conventional bounds and is able to detect extremely weak signals.     

Super gain beamformer (N/sup 2/) for source power and bearing estimation

A technique for evaluating the source powers and bearings of the received signals at a sensor array is presented. The processor gain is not limited to conventional bounds and is able to detect extremely weak signals.     

An analysis of the anomalous dip in scattering parameter S/sub 22/ of InGaP-GaAs heterojunction bipolar transistors (HBTs)

The kink phenomenon in scattering parameter S/sub 22/ of InGaP-GaAs heterojunction bipolar transistors (HBTs) was explained quantitatively for the first time. Our results show that the output impedance of InGaP-GaAs HBTs can be represented by a simple series resistance-capacitance (R-C) circuit at low frequencies and a simple parallel R-C circuit at high frequencies very accurately because of the high output resistance of HBTs. The behavior of S/sub 22/ of HBTs is in contrast with that of field effect transistors (FETs), where the smaller drain-source output resistance R/sub ds/ obscures the ambivalent characteristics.     

Design of regular (2,d/sub c/)-LDPC codes over GF(q) using their binary images

In this paper, a method to design regular (2, d_c)- LDPC codes over GF(q) with both good waterfall and error floor properties is presented, based on the algebraic properties of their binary image. First, the algebraic properties of rows of the parity check matrix H associated with a code are characterized and optimized to improve the waterfall. Then the algebraic properties of cycles and stopping sets associated with the underlying Tanner graph are studied and linked to the global binary minimum distance of the code. Finally, simulations are presented to illustrate the excellent performance of the designed codes.     

Analytical investigation of dead space effect under near-breakdown conditions in GaInP/GaAs composite double heterojunction bipolar transistors

The dead space effect under near-breakdown conditions in GaInP/GaAs composite collector double heterojunction bipolar transistor (DHBT) is investigated analytically. Using the dead space corrected model, the breakdown voltage is found to decrease with GaAs spacer thickness as reported from experiments. The common-mode emitter IV characteristics for the DHBT are simulated until the onset of multiplication with good agreement with reported experimental results [IEEE Elec. Dev. Lett. 15 (1994) 10]. A proposed optimised structure is simulated with comparably good turn-on I–V characteristics and improved breakdown performance.     

Characterization and reliability of dual high-k gate dielectric stack (poly-Si-HfO/sub 2/-SiO/sub 2/) prepared by in situ RTCVD process for system-on-chip applications

We investigate for the first time the possibility of integrating chemical vapor deposition (CVD) HfO/sub 2/ into the multiple gate dielectric system-on-a-chip (SoC) process in the range of 6-7 nm, which supports higher voltage (2.5-5 V operation/tolerance). Results show that CVD HfO/sub 2/-SiO/sub 2/ stacked gate dielectric (EOT =6.2 nm) exhibits lower leakage current than that of SiO/sub 2/ (EOT =5.7 nm) by a factor of /spl sim/10/sup 2/, with comparable interface quality (D/sub it//spl sim/1/spl times/10/sup 10/ cm/sup -2/eV/sup -1/). The presence of negative fixed charge is observed in the HfO/sub 2/-SiO/sub 2/ gate stack. In addition, the addition of HfO/sub 2/ on SiO/sub 2/ does not alter the dominant conduction mechanism of Fowler-Nordheim tunneling in the HfO/sub 2/-SiO/sub 2/ gate stack. Furthermore, the HfO/sub 2/-SiO/sub 2/ gate stack shows longer time to breakdown T/sub BD/ than SiO/sub 2/ under constant voltage stress. These results suggest that it may be feasible to use such a gate stack for higher voltage operation in SoC, provided other key requirements such as V/sub t/ stability (charge trapping under stress) can be met and the negative fixed charge eliminated.     

Double heterojunction AlxGa1-xAs/GaAs bipolar transistors (DHBJT's) by MBE with a current gain of 1650

Double heterojunction AlGaAs/GaAs bipolar junction transistors (DHBJT's) grown by molecular beam epitaxy (MBE) were fabricated and tested. Devices with 0.2-µm and 0.1-µm base thicknesses exhibited common emitter current gains of up to 325 and 1650, respectively, in a wide range of collector currents. To obtain such high current gains, growth conditions had to be optimized and controlled. These high current gains, compared with the previous best value of 120 obtained in a MBE-grown transistor, make the HBJT's very promising for low-power high-speed logic application.     

(In,Ga)As/InP n-p-n heterojunction bipolar transistors grown by liquid phase epitaxy with high DC current gain

Experimental results on heterojunction bipolar transistors made in liquid phase epitaxial (In,Ga)As and InP layers on InP substrates are described. The (In,Ga)As base layer was doped with manganese during growth and contacts were made to it by beryllium ion implantation. The maximum measured dc current gain β of these devices was in excess of 500. These devices also demonstrate for the first time in an InP-based system, the inverted emitter-down heterojunction transistor structure with a base contact, which yields a minimized collector-base junction area and should significantly improve high-frequency performance.     

Triple implant (In,Ga)As/InP n-p-n heterojunction bipolar transistors for integrated circuit applications

For the first time (In,Ga)As/InP n-p-n heterojunction bipolar transistors (HJBT's) applicable to integrated circuits have been fabricated by triple ion implantation. The base has been formed by beryllium ion implantation and the collector by silicon ion implantation. The implants were made into an LPE-grown n-n (In,Ga)As/InP heterostructure on an n+-InP substrate. This inverted mode emitter-down heterojunction transistor structure demonstrates to a maximum current gain of 7 with no hysteresis in the characteristics. The ideality factors of the IBversus VBE, and ICversus VBEcharacterisitics with VCB= 0, are 1.25 and 1.08, respectively, indicating that the defect level in the herterojunction is low and that minority-carrier injection and diffusion is the dominant current flow mechanism.     

GaInP/GaAs collector-up tunneling-collector heterojunction bipolar transistors (C-up TC-HBTs): optimization of fabrication process and epitaxial layer structure for high-efficiency high-power amplifiers

This paper describes a novel heterojunction bipolar transistor (HBT) structure, the collector-up tunneling-collector HBT (C-up TC-HBT), that minimizes the offset voltage V/sub CE,sat/ and the knee voltage V/sub k/. In this device, a thin GaInP layer is used as a tunnel barrier at the base-collector (BC) junction to suppress hole injection into the collector, which results in small V/sub CE,sat/. Collector-up configuration is used because of the observed asymmetry of the band discontinuity between GaInP and GaAs depending on growth direction. To minimize V/sub k/, we optimized the epitaxial layer structure as well as the conditions of ion implantation into the extrinsic emitter and post-implantation annealing. The best results were obtained when a 5-nm-thick 5/spl times/10/sup 17/-cm/sup -3/-doped GaInP tunnel barrier with a 20-nm-thick undoped GaAs spacer was used at the BC junction, and when 2/spl times/10/sup 12/-cm/sup -2/ 50-keV B implantation was employed followed by 10-min annealing at 390/spl deg/C. Fabricated 40/spl times/40-/spl mu/m/sup 2/ C-up TC-HBTs showed almost zero V/sub CE,sat/ (<10 mV) and a very small V/sub k/ of 0.29 V at a collector current density of 4 kA/cm/sub 2/, which are much lower than those of a typical GaInP/GaAs HBT. The results indicate that the C-up TC-HBT's are attractive candidates for high-efficiency high power amplifiers.