Turnover phenomenon in N ν N Si devices and second breakdown in transistors

Turnover phenomenon in N νl N Si devices was studied in relation to second breakdown in NP ν N Si transistors. The devices were fabricated by a usual diffusion method using P2O5powder as diffusant source. Four groups of the devices, each having a diameter of 1.0 mm, a thickness of 0.25 mm, a resistivity in ν layer ranging from 3 to 210 ohm-cm, and a surface concentration in N layer of 2 × 10²⁰cm^-3, were tested under two kinds of applied voltage. The applied voltage was a half-cycle voltage from ac source and single-pulse voltage with a rising and flat part. The field strength in ν layer was below 3 × 10³v/cm. The voltage vs. current characteristics and the transient figures of voltage and current were observed on a memoriscope, and the temperature of the device was determined using temperature sensitive paints. The current increases linearly with the increasing voltage at the onset of the V-I curve, and saturates with further increases in voltage. Turnover occurs after the large departure from ohmic behavior in V-I characteristics. At the turnover, the temperature of the device was estimated to be near intrinsic; 160°C for the device with ∼ 210 ohm-cm, 330°C for ∼ 3 ohm-cm. The discussions on turnover characteristics are made in terms of the decrease in carrier mobility, the increase in carrier concentration in ν layer, and the current constriction in the device.     

Some new aspects of thermal instability of the current distribution in power transistors

An important characteristic of second breakdown in p-n junctions is the current constriction to a small region. This may be caused by a thermal feedback mechanism, as discussed by Scarlett and Shockley, and by Bergmann and Gerstner. A brief review of this theory is given, illustrated by experimental results of a simple model arrangement consisting of three thermally coupled transistors. The essential parameters influencing the thermal stability of the current distribution are device geometry, power density, and temperature dependence of current. It is widely known that second breakdown occurs at high voltages at a much lower power level than at low voltages. To allow a more detailed discussion of this effect in view of thermal stability, we determined experimentally the temperature coefficient of transistor current for various Si planar transistors as a function of current, voltage, and junction temperature. The experimental procedure is described and the results are discussed. The experimental values of the temperature coefficient range from 0.08 to 0.01 1/°C. The values for high currents are much lower than predicted by the theory of Ebers and Moll. It thus can easily be understood why, in the case of high current, and low voltage, the thermal stability of the current distribution is much better than in the case of low current and high voltage.     

Laser-triggered dynamic breakdown of gases and laser-induced prebreakdown signals

Dynamic breakdown of Ne and Ar gases biased to the prebreakdown stage, with and without absorption of very short duration incident N2laser pulses, is studied. Effects of bias and incident laser intensity are seen to be complementary. Laser illumination of the interelectrode gap causes gas breakdown at the cathode to take place at a faster rate and at lower breakdown threshold bias than without the illumination. Breakdown pulse shape varies according to gas composition and bias, and is much different from simple nonbreakdown "prebreakdown" responses to the laser pulses. The prebreakdown signals are attributed to photon-enhanced ionization in the focal volume between the electrodes, while the laser-triggered breakdown pulses are attributed to photon-enhanced excitation and diffusion of such neutral atoms to the high field gradient region near the cathode, where cascade ionization collisional effects are amplified.     

雪崩光电探测器的击穿效应模型分析

基于CMOS工艺制备了空穴触发的Si基雪崩探测器(APD),基于不同工作温度下器件的击穿特性,建立空穴触发的雪崩器件的击穿效应模型。根据雪崩击穿模型和击穿电压测试结果,拟合曲线得到击穿电场与温度的关系参数(dE/dT),器件在250～320 K区间内,击穿电压与温度是正温度系数,器件发生雪崩击穿为主,dV/dT=23.3 mV/K,其值是由倍增区宽度以及载流子碰撞电离系数决定的。在50～140 K工作温度下,击穿电压是负温度系数,器件发生隧道击穿,dV/dT=-58.2 mV/K,其值主要受雪崩区电场的空间延伸和峰值电场两方面因素的影响。     

High-pressure oxidation for thin gate insulator process

High-pressure oxidation of silicon was performed at a pressure of 8.9 kg/cm²at a temperature range of 650 to 950°C. The oxidation temperature dependence of the film density, refractive index, chemical etching rate, and residual stress was measured. The film density of the oxide film was found to increase with decreasing oxidation temperature. The refractive index of the film also increased with decreasing oxidation temperature. The residual stress was found to be dependent on the oxidation temperature. The dielectric breakdown strength of the oxide film was measured by the voltage ramping method. The defect density of the oxide film calculated from the distribution of dielectric breakdown strength slightly decreased with decreasing oxidation temperature. The surface-state density of the oxide film was about 1.1 × 10¹¹cm^-2throughout the oxidation temperature range. The oxide grown on a doped polysilicon layer at a temperature of 750°C was five times as thick as the oxide simultaneously grown on the silicon substrate. The high-pressure and low-temperature oxidation was applied to the fabrication process of a device with a double polysilicon layer structure.     

Electrical characteristics of AlGaN/GaN metal-insulator semiconductor heterostructure field-effect transistors on sapphire substrates

The electrical performance of AlGaN/GaN metal-insulator semiconductor, heterostructure field-effect transistors (MISHFETs) were studied and compared to passivated and unpassivated HFETs. Record MISHFET current densities up to 1,010 mA/mm were achieved, and the devices exhibited stable operation at elevated temperatures up to 200°C. Higher maximum-drain current, breakdown voltage, and a lower gate-leakage current were obtained in the MISHFETs compared to unpassivated HFETs. The breakdown voltage of these devices exhibited a negative temperature coefficient of 0.14 VK⁻¹, suggesting that a mechanism other than impact ionization may be responsible. Different structures of MIS diodes also reveal that the high-field region at the gate edge dominates the breakdown mechanism of these devices. Gate-pulse measurements indicate the presence of current collapse in the MISHFETs, despite the expected passivation effect of the insulator. However, a striking feature observed was the mitigation of these effects upon annealing the devices at 385°C for 5 min under N₂ ambient.     

A sub-1-V, high precision, ultra low-power, process trimmable, resistorless voltage reference with low cost 90-nm standard CMOS technology

A low power voltage reference generator operating with a supply voltage ranging from 1.6 to 3.6?V has been implemented in a 90-nm standard CMOS technology. The reference is based on MOSFETs that are biased in the weak inversion region to consume nanowatts of power and uses no resistors. The maximum supply current at 3.6?V and at 125°C is 173?nA. It provides a 771?mV voltage reference. A temperature coefficient of 7.5?ppm/°C is achieved at best and 39.5?ppm/°C on average, in a range from ?40 to 125°C, as the combined effect of a suppression of the temperature dependence of mobility and the compensation of the threshold voltage temperature variation. Several process parameters affect the performance of the proposed voltage reference circuit, so a process adjustment aimed at correcting errors in the reference voltage caused by these variations is dealt with. The total block area is 0.03?mm².     

Edge current induced failure of semiconductor PN junction during operation in the breakdown region of electrical characteristic

Typical blocking I-V characteristics are shown and analyzed for PN junctions exhibiting a breakdown region above 1000 V from commercial diodes and power MOSFETs. The leakage reverse current of PN junctions from commercial silicon devices available at this time has a flowing component at the semiconductor-passivant material interface around the junction edge.Part of the plotted experimental current-voltage characteristic fits to linear variation and deviation from this variation at higher applied voltage is attributed to non-controlled current flow in the interfacial layer, between the silicon and passivating material from the junction periphery. The thin interfacial layer including atomic layers both from the semiconductor and passivating dielectric material with fixed charges has imperfections resulted from the junction passivation process. For controlled-avalanche PN junctions no deviation from linear voltage dependence of the reverse current is possible until breakdown region practically at right knee appears. For other PN junctions deviation of the reverse current from linear variation results in a breakdown region with round knee and still with visible voltage dependence at current increase. Such soft breakdown region caused by the phenomena in the interfacial layer is exhibited at lower applied reverse voltage than the expected one for breakdown caused by charge carrier avalanche multiplication at the junction. Operation even for short in the soft breakdown region can lead to PN junction failure and for this reason, a maximum working permissible reverse voltage is specified in device data sheet with a value under the breakdown region. Junction failure consists in significantly lower reverse voltage than the initial one or even electrical short-circuit caused by a spot of material degradation in the interfacial layer from the junction periphery. Operation of the controlled-avalanche diode in the breakdown region is possible only for single pulse of short duration and at junction temperature not higher than 175 °C. Above 150-175 °C even for controlled-avalanche diodes deviation from linear variation of the reverse current has been observed and soft breakdown region can appear before the expected avalanche breakdown. Device failure after operation in the breakdown region, caused by spot of material degradation at the junction periphery has occurred in such conditions. For high voltage commercial power MOSFETs operation in the avalanche breakdown region is limited to 150 °C.     

Characteristics of Ni/SiC Schottky diodes grown by ICP-CVD

A Ni/SiC Schottky diode was fabricated with an α-SiC thin film grown by the inductively coupled plasma chemical vapor deposition, ICP-CVD method on a (1 1 1) Si wafer. The α-SiC film was grown on a carbonized Si layer that the Si surface had been chemically converted to a very thin SiC layer by the ICP-CVD method at 700 °C. To reduce defects between the Si and α-SiC, the surface of the Si wafer is slightly carbonized. The film characteristics of α-SiC were investigated by employing TEM and FT-IR. A sputtered Ni thin film was used for the anode metal. The boundary status of the Ni/SiC contact was investigated by AES as a function of annealing temperature. It is shown that the ohmic contact could be acquired below 1000 °C annealing temperature. The forward voltage drop of the Ni/α-SiC Schottky diode is 1.0 V at 100 A/cm². The breakdown voltage is 545 V which is five times larger than the ideal breakdown voltage of a silicon device. Also, the dependence of barrier height on temperature was observed.     

GaAs Schottky diodes with near-ideal characteristics

The I-V characteristics of some GaAs Schottky-barrier IMPATT diodes are found to be nearly ideal at operating temperatures (∼200°C). Fabricated on epitaxial n-type substrate with platinum contacts, the diodes use a truncated cone shape to avoid soft breakdown. The breakdown voltage and its temperature dependence are close to calculated values for one-sided abrupt junctions.     

Breakdown stability of gold, aluminum, and tungsten Schottky barriers on gallium arsenide

The stability of the breakdown voltage of Au, Al, and W Schottky barrier diodes fabricated on n-type GaAs has been evaluated. The nearly ideal breakdown voltage of Au diodes was found to degrade upon annealing, even at below 150°C. The breakdown voltage of the as-deposited Al diodes was half that of the Au diodes, and degraded upon annealing at above 450°C. Secondary ion mass spectroscopy (SIMS) measurements revealed penetration of Al into the GaAs. The breakdown voltage of W diodes increased to equal that of the Au diodes upon annealing above 400°C and remained stable at up to 550°C. No interdiffusion at the W/GaAs interface was observed.     

Electrical characteristics of large scale integration (LSI) MOSFETs at very high temperatures part I: Theory

A systematic investigation of the effects of high temperature (27° C to 300° C) on long N and P channel MOS transistors suitable for Large Scale Integration (LSI) is presented. The theory of the MOSFET is used to study the temperature behavior of the device's electrical parameters. The main temperature dependent parameters are the threshold voltage, the channel mobility, and the junction leakage currents. Zero-Temperature-Coefficient (ZTC) gate bias voltages are predicted, in the nonsaturation (linear) region, and in the saturation region of operation, for a given device. Criteria for the existence of such bias points are developed, and nonidealities of these points discussed. The large and small signal parameters of the MOSFET biased at its ZTC points are obtained. Detailed comparisons with experimental results will be reported in an accompanying paper [1].     

Temperature behavior and annealing of insulated gate transistors subjected to localized lifetime control by proton implantation

Localized lifetime control by proton implantation can result in a considerable improvement in the trade-off between device turn-off time and forward voltage when compared with the unlocalized method of electron irradiation. After a proton dose of 3 × 10¹¹cm⁻² at 3.1 MeV implanted here into insulated gate transistors, turn-off time is reduced by more than an order of magnitude compared to unimplanted devices. When the implanted devices are operated as high voltage switches at a current of 152 A cm⁻² and at a forward blocking voltage of 400 V, the following increases are observed by increasing device operating temperatures from 20 to 150°C, (a) forward voltage: 2.5 V to 2.7 V; (b) turn-off time: 0.78 μs to 1.23 μs; (c) leakage current: 20 nA to 1 mA. The physical mechanisms responsible for the qualitative temperature dependences are identified: MOS channel resistance for forward voltage, carrier capture cross-section for turn-off time, and generation and diffusion components of leakage current. Since no catastrophic or unrecoverable behavior is observed, normal device operation within the tested temperature range is possible. Isothermal annealing curves of turn-off time measured after annealing, and corresponding to a few hours annealing time, reveal that a constant turn-off time is reached after about an hour. The constant value increases with temperature, but is still below the unimplanted value after 4 h at 525°C. The turn-off time was verified to be constant even after 24 h of annealing at 200°C. Lifetime control by proton implantation seems to be more thermally stable than that caused by electon irradiation.     

Detailed performance characteristics of hybrid InP-InGaAsP APD's

Detailed performance characteristics of hybrid InP-InGaAsP APD's having negligible dark current (ID< 6 nA at M = 30) are reported. The excess noise factor F is found to be given by F/M ≈ const ≈ 0.42 ± 0.10 for gains in the range 5 ≤ M ≤ 35. The breakdown voltage increases with temperature according to ΔV_{BD}/V_{BD}/ΔT = 1.0 × 10^-3/°C. The dark current near breakdown doubles every 15°C. Sub-nanosecond rise times are observed, however, fall times are extended to ∼3 nsec by a diffusion tail that will be difficult to completely eliminate.     

Reanalyzing the basic bandgap reference voltage circuit considering thermal dependence of bandgap energy

The basic bandgap reference voltage generator, BGR, is thoroughly analyzed and relations are reconstructed considering dependency of bandgap energy, E_g, to absolute temperature. The previous works all consider E_g as a constant, independent of temperature variations. However, E_g varies around 25 meV when the temperature is increased from 2 to 92 °C. In this paper the dependence of E_g to absolute temperature, based on HSPICE mosfet models in HSPICE MOSFET Models Manual (Version X-2005.09, 2005), is approximated by a third-order polynomial using Lagrangian interpolating method within the temperature range of 2–92 °C. Accurate analysis on the simplified polynomial reveals that the TC of V_BE must be corrected to ?1.72 mV/°K at 27 °C which has been formerly reported about ?1.5 mV/°K in Razavi (Design of analog CMOS integrated circuits, 2001) and Colombo et al. (Impact of noise on trim circuits for bandgap voltage references, 2007), ?2 mV/°K in Gray et al. (Analysis and design of analog integrated circuits, 2001), Leung and Mok (A sub-1-V 15-ppm/°C CMOS bandgap voltage reference without requiring low threshold voltage device, 2002), Banba et al. (A CMOS bandgap reference circuit with sub-1-V operation, 1999), and ?2.2 mV/°K in Jones and Martin (Analog integrated circuit design, 1997), Tham and Nagaraj (A low supply voltage high PSRR voltage reference in CMOS process, 1995). Another important conclusion is that the typical weighting coefficient of TC+ and TC? terms is modified to about 19.84 at 27 °C temperature from otherwise 16.76, when E_g is considered constant, and also 17.2, in widely read literatures, (Razavi in Design of analog CMOS integrated circuits, 2001). Neglecting the temperature dependence of E_g might introduce a relative error of about 20.5 % in TC of V_BE. Also, resistance and transistor size ratios, which denote the weighting coefficient of TC+ term, might be encountered to utmost 20.3 % error when the temperature dependence of E_g is ignored.     

Analysis of dielectric breakdown in CoFeB/MgO/CoFeB magnetic tunnel junction

The time-dependent dielectric breakdown has been investigated in a series of nominally identical Co–Fe–B/MgO/Co–Fe–B junctions by voltage ramp experiments. The results divulge that the breakdown voltage strongly depends on the polarity of the applied voltage, junction area, ramp speed and the annealing temperature. Magnetic tunnel junctions (MTJs) with positive bias on the top electrode show higher breakdown voltage than MTJs with negative bias. We found that there is a significant decrease in the breakdown voltage when the annealing temperature is increased above 350 °C. The experimental data can be described by different specific forms of breakdown probability functions which lead to different extrapolation of life time of junctions.     

New electronic effects in double injection diodes with one deep level

Double injection diodes made of high resistivity semiconductors compensated with deep levels show a negative differential resistance region in the stationary I - V characteristic. At lower temperatures the injection level of free carriers can be altered within the prebreakdown region without changing the space charge situation. Therefore is valid for several orders of magnitude of the current. Furthermore, the switching of the diode from the “off state” (prebreakdown region) to the “on-state” (high injection or semiconductor regime) can be delayed by applying a corresponding voltage V >V_BD, the breakdown voltage. An exponential dependence of the delay time t_D on the applied voltage is found. The lower limit of t_D is determined by the free carrier lifetime, an upper limit does practically not exist if the temperature is low enough.     

A New SOI LDMOSFET Structure with a Trench in the Drift Region for a PDP Scan Driver IC

To improve the characteristics of breakdown voltage and specific on‐resistance, we propose a new structure for a LDMOSFET for a PDP scan driver IC based on silicon‐on‐insulator with a trench under the gate in the drift region. The trench reduces the electric field at the silicon surface under the gate edge in the drift region when the concentration of the drift region is high, and thereby increases the breakdown voltage and reduces the specific on‐resistance. The breakdown voltage and the specific on‐resistance of the fabricated device is 352 V and 18.8 m·cm² with a threshold voltage of 1.0 V. The breakdown voltage of the device in the on‐state is over 200 V and the saturation current at V_gs=5 V and V_ds=20 V is 16 mA with a gate width of 150 µm.     

Characteristics of enhancement/depletion (E/D) gate MOSFET fabricated using ion implantation

The E/D gate MOSFET, which has an enhancement and depletion mode region under the same gate, is fabricated by using ion implantation as a tool for shifting threshold voltage. Threshold voltage, transconductance and drain breakdown voltage are studied as functions of implantation dose up to 12 × 10¹² cm^?2.It is found that, at an appropriate dose, the transconductance of this device is determined solely by the channel length of the enhancement mode region, and is larger than that of a short channel MOSFET with a standard structure but with the same drain breakdown voltage. Moreover, the dependence of threshold voltage on substrate bias measured in this device is found less sensitive to the transconductance than that in the standard short channel MOSFET.     

The maximum dielectric strength of thin silicon oxide films

Thin film silicon oxide capacitors with nonshorting breakdowns were investigated. Breakdowns appear in three forms: single hole, self-propagating, and maximum voltage breakdowns. Single hole and self-propagating breakdowns occur at flaws, and self-propagating breakdowns develop only when the resistor to the source is relatively small, less than 10 kΩ in these experiments. After flaws are burned out by single hole breakdowns, with larger source resistors the maximum voltage breakdown can be observed, destroying the whole capacitor simultaneously. Plotting current against voltage, the current increase is quasi-exponential, but prior to maximum voltage breakdown, the current continues to increase while the voltage decreases slightly below a maximum value Vm. Assuming thermal instability as the cause for this change in the I-V relationship, we have derived an expression for the maximum voltage Vm. Calculated results for fields up to 9.5 MV/cm were found to agree well with measurements for temperatures from -145°C to 65°C and for thicknesses from 3000 Å to 50 000 Å. Fmdecreases with increasing temperature and thickness of insulation, and is higher for silicon dioxide than for silicon monoxide films. Maximum voltage breakdown occurs when the quasi-exponential increase of leakage current with field produces thermal instability over the whole capacitor area. The maximum dielectric strength is characteristic of the whole capacitor and is determined by its electrical and thermal conductance.