基于金硅原电池保护电容加速度计的制作

提出并实现了一种利用SoI结合金硅原电池保护和反熔丝制作电容式加速度计的新工艺方法。该工艺用SoI顶层硅制作梁和上电极,用衬底制作质量块。采用DRIE从正面刻蚀形成释放孔,TMAH腐蚀实现质量块的释放,在TMAH腐蚀过程中利用金硅原电池保护实现梁和表面极板的保护。在TMAH腐蚀完成前,反镕丝保持断开状态,腐蚀完成后,击穿反镕丝形成导通状态。通过测量金和硅的极化曲线得到60℃25%TMAH中实现原电池保护的金硅面积比不小于5∶1。成功制作成电容式加速度计结构,释放前后梁宽度均在9.4～10μm范围内,表明原电池保护有效。击穿后反熔丝并联导通电阻为5～25 kΩ之间。     

纳米梁的金硅原电池腐蚀和无损释放技术研究

采用金电极的硅纳米梁在通过HF湿法腐蚀SiO2牺牲层释放结构的时候会发生硅纳米梁被腐蚀现象,消除此效应对于纳米尺度梁制造非常重要:通过电化学工作站测量不同条件下金/硅在HF中的极化曲线和腐蚀电流,从定性和定量研究此腐蚀的原理和影响因素:金硅在HF中形成的原电池效应是此腐蚀的主要原因;改变金硅面积比和改变HF构成可以减缓...     

基于BOE硅腐蚀现象的硅纳米线制作

介绍一种硅纳米线制作方法.在SOI顶层硅上制作硅纳米梁,通过离子注入形成pnp结构,利用新发现的没有特殊光照时BOE溶液腐蚀pn结n型区域现象,结合BOE溶液氧化硅腐蚀,实现硅纳米线制作.制作完全采用传统MEMS工艺,具有工艺简单,成本低,可控,可靠性好,可批量制作等优点.利用该方法制作出了厚50 nm,宽100 nm的单晶硅纳米线,制作的纳米线可用于一维纳米结构电学性能研究、谐振器研究等.     

用于器件级真空封装的MEMS加速度传感器的设计与制作

设计了一种可用于器件级真空封装的三明治电容式MEMS加速度传感器.该传感器被设计为四层硅结构,其中上下两层为固定电极,中间两层为硅-硅直接键合的双面梁-质量块结构的可动电极.利用自停止腐蚀工艺在中间质量块键合层上腐蚀出2个深入腔内的V型抽气槽,使得MEMS器件在后续的封装中能够实现内部真空.为防止V型抽气槽在划片中被水或硅渣堵塞,采用双面划片工艺.划片后,器件的总尺寸为6.8mm ×5.6mm ×1.72 mm,其中,敏感质量块尺寸为3.2mm×3.2mm ×0.86mm,检测电容间隙2.1 μm.对器件级真空封装后的MEMS加速度传感器进行了初步测试,结果表明:制作的传感器的谐振频率为861 Hz,品质因数Q为76,灵敏度为1.53 V/gn,C-V特性正常,氦气细漏＜1×10-9 atm-cm3/s,粗漏无气泡.     

一种圆片级硅三层键合的三明治加速度传感器

提出了一种利用体微机械加工技术制作的硅三层键合电容式加速度传感器.采用硅各向异性腐蚀和深反应离子刻蚀技术实现中间梁一质量块结构的制作,通过玻璃软化键合方法完成上、下电极的键合.在完成整体结构圆片级真空封装的同时通过引线腔结构方便地实现了中间电极的引线.传感器芯片大小为6.8 mm×5.6 mm×l.26 ITUTI,其中敏感质量块尺寸为3.2 mm×3.2 mm×0.42 mm.对封装的传感器性能进行了初步测试,结果表明制作的传感器灵敏度约4.15 pF/g,品质因子为56,谐振频率为774 Hz.     

几种基于MEMS的纳米梁制作方法研究

特征尺度在纳米量级的梁结构是多种纳机电器件的基本结构.提出了几种基于MEMS技术的纳米梁制作方法,通过利用MEMS技术中材料与工艺的特性实现单晶硅纳米梁的制作.在普通(111)硅片上,利用各向异性湿法腐蚀对(111)面腐蚀速率极低的特性,通过干法与湿法腐蚀相结合制成厚度在100 nm以下的纳米梁.该方法不使用SOI硅片,有效控制了成本.在(100)SOI硅片上,通过氧化减薄的方法得到厚度在100 nm以下的多种纳米梁,由于热氧化的精度高,一致性好,该方法重复性与一致性均较好.在(110)SOI硅片上,利用硅的各向异性腐蚀特性以及(110)硅片的晶向特点,制作宽度在100 nm以下的纳米梁,梁的两个侧面是(111)面.     

EPW腐蚀液中制作近似圆形硅膜研究

研究了《100》单晶硅在EPW腐蚀液中制作近似圆形硅膜,在EPW腐蚀液中因《100》单晶硅腐蚀速率各向异性,在圆形掩膜下很难实现圆形单晶硅膜.基于EPW腐蚀液中《100》单晶硅存在严重凸角削角,采用带锯齿(9个、20个、36个)结构的齿轮掩膜图形腐蚀制作近似圆形硅膜,通过采用SEM观察,随腐蚀时间增加,圆形掩膜EPW腐蚀后硅膜为近似方形,而带有36个锯齿结构的齿轮掩膜腐蚀后硅膜近似圆形.结果表明,利用掩膜锯齿结构在EPW腐蚀液中存在凸角削角现象,能够实现近似圆形硅膜的制作.     

用<111>硅的自停止腐蚀方法制作硅膜

利用各向异性腐蚀和键合工艺,提出了一种新的自停止腐蚀方法,该方法可以得到大于1μm厚的均匀硅膜,可用于微传感器研制。     

微米尺度温差测试结构的研究

微米尺度热学性能测试需要在微米尺度内产生稳定的温度场并准确测量温差,对此设计并制作了一种微米尺度温差测试结构。当在测试结构的加热电极施加0.1,0.2,0.3,0.4,0.5V的电压时,测得实验室制作的硅纳米线两端温差分别为7,23,47,78,109 K,与ANSYS仿真结果大致吻合;此外,利用该测试结构测得硅纳米线塞贝克系数为4.24×10-4V/K,与文献中硅材料一致。测试结果表明:该结构能够提供稳定的温度场并精确测量温差,满足微米尺度温差测试的基本要求。     

基于硅塑性变形的蛇形梁垂直梳齿驱动器

设计了基于硅塑性变形的垂直梳齿驱动器,中央可动微镜由四组蛇形曲折梁支撑。驱动器的制作采用硅—硅键合技术,首先利用DRIE干法刻蚀技术释放可动梳齿与固定梳齿,然后通过各向异性湿法腐蚀制作的施压凸台实现可动梳齿和固定梳齿的精确自对准,最后利用硅塑性变形使可动梳齿和固定梳齿在垂直方向上产生位错,成功制作出在Z方向依靠位错梳齿实现垂直驱动的蛇形梁静电梳齿驱动器。     

PN结自致停精密腐蚀的研究

本文系统地研究了p-n结自致停精密腐蚀时的J-V特性，腐蚀自致停时电流变化的性状和实现这种精密腐蚀的关键工艺，同时也探讨了这种自致停腐蚀样品表面粗糙度、腐蚀速率与工艺参数及其他条件的关系，目的在使其能成为一种实用化的技术。p-n结自致停腐蚀克服了p^ 自致停腐蚀的缺点，且又保持了硅各向异性腐蚀的特性。     

A two-step electrochemical etch-stop to produce freestanding bulk-micromachined structures

The paper introduces a processing scheme to produce freestanding micromechanical beams by bulk micromachining silicon substrates in aqueous KOH. The release of the structures is done by wet-chemical etching exclusively. Standard MOS process steps are used to generate two adjacent etch-stop regions of different depths. During the anisotropic etching of the substrate in a protective chuck, membranes of two different thicknesses are formed by the electrochemical etch-stop mechanism. A short time-controlled etch of these regions in KOH releases the final beam by removing the thinner membrane areas around it. A layer of thermal oxide with low stress supported by a thin film of copolymer will keep the etchant away from the frontside of the wafer. It can be removed easily by BHF subsequent to micromachining. Resonance measurements with a laser vibrometer were used to determine the mechanical behaviour of the created structures under varying gas pressure.     

石英湿法腐蚀及侧壁晶棱修平工艺研究

以石英陀螺的微结构为研究对象,对石英的湿法腐蚀规律进行研究.选用500 μn厚Z切向石英片,蒸镀10 nm厚Cr膜和200 nm厚金膜作为掩模层,选用40%氢氟酸和40%氟化铵的1:1混合溶液作为腐蚀液.通过在不同温度下的腐蚀试验,表明腐蚀速率随温度增加而增大,温度过低腐蚀过慢影响腐蚀效率,温度过高使石英侧壁表面粗糙度增加.经过试验摸索,在70℃下腐蚀,可获得表面质量较好的石英微结构.石英在湿法腐蚀中结构侧壁会产生两级晶棱,根据侧壁主要晶面的腐蚀速率,计算出修平侧壁两级晶棱所需时间分别为8h和27h,经过试验验证,在预计时间内,石英侧壁晶棱基本修平.     

Defect-free wet etching through pyrex glass using Cr/Au mask

This paper reports the highest etch depth of annealed Pyrex glass achieved by wet etching in highly concentrated HF solution, using a low stress chromium–gold with assistance of photoresist as masking layer. The strategies to achieve that are: increasing the etch rate of glass and simultaneously increasing the resistance of Cr/Au mask in the etchant. By annealing the Pyrex glass and using a highly concentrated HF acid, a high etch rate can be obtained. Furthermore, a method to achieve a good resistance of the Cr/Au masking layer in the etching solution is to control the residual stress and to increase the thickness of Au deposition up to 1 μm. In addition, the presence of a hard baked photoresist can improve the etching performance. As a result, a 500-μm thick Pyrex glass wafer was etched through.     

Defect-free wet etching through pyrex glass using Cr/Au mask

This paper reports the highest etch depth of annealed Pyrex glass achieved by wet etching in highly concentrated HF solution, using a low stress chromium–gold with assistance of photoresist as masking layer. The strategies to achieve that are: increasing the etch rate of glass and simultaneously increasing the resistance of Cr/Au mask in the etchant. By annealing the Pyrex glass and using a highly concentrated HF acid, a high etch rate can be obtained. Furthermore, a method to achieve a good resistance of the Cr/Au masking layer in the etching solution is to control the residual stress and to increase the thickness of Au deposition up to 1 μm. In addition, the presence of a hard baked photoresist can improve the etching performance. As a result, a 500-μm thick Pyrex glass wafer was etched through.

     

Pyrex 7740玻璃深刻蚀掩模研究

玻璃湿法深刻蚀掩模常采用低压化学气相沉积(LPCVD)多晶硅、Cr/Au金属层+光刻胶等,但往往会在玻璃中引入应力,影响后期应用(如阳极键合),而且Cr/Au金属层价格昂贵。为避免以上缺点,引入了SX AR—PC 5000/40保护胶+WBR2075干膜作为玻璃的刻蚀掩模,在HF︰NH4F,HF︰HCl,HF︰HCl︰NH4F刻蚀溶液中进行了大量实验。实验结果表明:SX AR—PC 5000/40抗腐蚀能力强,且成功实现了对Pyrex 7740玻璃131μm的深刻蚀。整个工艺过程与IC工艺兼容,可以进行圆片级批量加工。实验结果对圆片级封装和其他MEMS器件的制作有一定参考作用。     

Low resistive silicon substrate as an etch-stop layer for drilling thick SiO2 by spark assisted chemical engraving (SACE)

Controlling precisely the depth in glass micro-drilling by spark assisted chemical engraving (SACE) remains challenging, particularly for low depths. The possibility of using an electrically conductive material as an etch-stop layer for SACE gravity-feed drilling is investigated in this paper. Micromachining with constant DC and pulsed DC of 30–35 μm thick SiO₂ deposited on low resistive silicon substrate demonstrated the etch-stop function of the conductive silicon. Measurements of etch rates and hole profiles along with scanning electron microscope imaging revealed the mechanism underlying the etch-stop process. Low resistive silicon is demonstrated to be a good etch-stop layer for SACE gravity-feed drilling. Demonstration of machining of SiO₂ layer on silicon as a substrate and an etch-stop layer opens up new possibilities to adapt SACE for developing devices on silicon platform.     

3D chip stack technology using through-chip interconnects

The current technology in micro-and nano-electronics is insufficient to meet future demands for several applications. Most state-of-the-art solutions rely on so-called embedded technologies, which are both expensive and complex. One solution to the problem of integrating mixed technologies is the concept of 3D stacking. Our approach implements an epitaxial etch-stop layer for thickness control of the thinning process. Using this etch-stop layer, we can create a precise alignment of back-side vias to the landing pads in the first metal layer of the active CMOS, resulting in small via diameters and high connection densities between individual-layers of the 3D stack. Furthermore, we can use other materials, like GaAs (gallium arsenide), in combination with an epitaxial lift-off process. We use a copper-tin soldering process based on the solid-liquid interdiffusion (solid) process to create the electrical and mechanical connection between the single chip layers. Using this process, we created true multilayer stacks and tested them with respect to the static electrical properties of ohmic contacts and interchip vias. We directly incorporated these results in the design of test circuits that create tests for stuck-at failures of the interchip connections after stack assembly. This article presents a technology overview of how to achieve the goal in a 3D fabrication process. It also shows measurements for characterizing interconnects.