高压SOI pLDMOS总剂量辐射致BV退化研究

对高压SOI pLDMOS器件总剂量辐射效应进行了研究。分析了不同偏置条件下器件击穿电压的退化机理,并使用TCAD在不同氧化层界面引入固定陷阱电荷,仿真了电离辐射总剂量效应。结果表明,总剂量辐射在FOX和BOX引入辐射陷阱电荷Q_BOX和Q_FOX。Q_FOX增加了漏极附近横向电场,降低了埋氧层电场,使击穿位置由体内转到表面,导致击穿电压退化。Q_BOX降低了埋氧层电场,降低了埋氧层压降,导致击穿电压退化。     

电场偏置对MOS器件电离辐射效应的影响

研究了外加电场对MOS器件电离辐射效应的影响.采用10 keV X射线对MOS器件在正/反电场偏置条件下进行总剂量辐射,分析了MOS器件辐射前后阈值电压的漂移量.实验结果表明,正偏情况下MOS器件的阈值电压漂移量远大于反偏情况下MOS器件的阈值电压漂移量.基于一维连续性方程,在考虑电子-空穴对的复合/逃逸率、电子及空穴的捕获横截面与外加电场关系的基础上,模拟了辐射诱生栅氧化层内陷阱电荷与辐射总剂量之间的关系,分析了陷阱电荷对MOS器件阈值电压的影响,仿真结果与实验数据吻合良好.     

γ射线辐照对130 nm部分耗尽SOI MOS器件栅氧经时击穿可靠性的影响

研究了射线辐照对130 nm部分耗尽（Partially Depleted,PD）绝缘体上硅（Silicon on Insulator,SOI）工艺MOS器件栅氧经时击穿（Time-Dependent Dielectric Breakdown,TDDB）寿命的影响。通过测试和对比辐照前后NMOS和PMOS器件的转移特性曲线、阈值电压、关态泄漏电流以及TDDB时间等电参数,分析了射线辐照对PD-SOI MOS器件TDDB可靠性的影响。结果表明:由于射线辐照在栅极氧化层中产生了带正电的氧化物陷阱电荷,影响了器件内部势垒的分布,降低了电子跃迁的势垒高度,导致了电子遂穿的正反馈作用增强,从而缩短了器件栅氧化层经时击穿时间,最终造成器件栅极氧化层的可靠性下降。     

深亚微米体硅器件电离辐射及退火与温度的相关性研究

对经过Co60不同剂量剂量率辐照的体硅MOS器件(NMOSFET与PMOSFET)分别进行了室温和高温下的退火实验,并对退火结果进行分析,讨论了退火温度对MOS器件阈值电压及辐射感生的氧化层陷阱电荷与界面态电荷产生的影响.     

不同偏置下全耗尽SOI NMOSFET总剂量抗辐射的研究

研究了不同偏置条件下,全耗尽SOI NMOSFET的总剂量抗辐射特性,主要讨论不同偏置条件对器件中陷获电荷的产生和分布,以及由此对器件性能产生的影响.通过器件模拟发现,在辐射过程中器件的偏置条件不同,造成器件的有源区和埋氧层中电场的分布有着很大的差异.而俘获电荷的产生与电场又有着紧密的联系,所以造成了俘获电荷的分布和密度有很大的不同,从而对器件的影响也不同.模拟结果表明,在三种不同的偏置条件下,OFF态(关态)时背沟道附近陷获电荷密度最高,以常数电流法估算出的阈值电压负漂移最大,同时引起了最大的本底静态漏电流.     

不同偏置下全耗尽SOI NMOSFET总剂量抗辐射的研究

研究了不同偏置条件下,全耗尽SOI NMOSFET的总剂量抗辐射特性,主要讨论不同偏置条件对器件中陷获电荷的产生和分布,以及由此对器件性能产生的影响.通过器件模拟发现,在辐射过程中器件的偏置条件不同,造成器件的有源区和埋氧层中电场的分布有着很大的差异.而俘获电荷的产生与电场又有着紧密的联系,所以造成了俘获电荷的分布和密度有很大的不同,从而对器件的影响也不同.模拟结果表明,在三种不同的偏置条件下,OFF态（关态）时背沟道附近陷获电荷密度最高,以常数电流法估算出的阈值电压负漂移最大,同时引起了最大的本底静态漏电流.     

漏雪崩应力热载流子注入引起的MOSFET退变特性研究

本对亚微米ＭＯＳＦＥＴ在漏雪崩恒流应力（ＤＡＳ）条件下热载流子注入引起的退变现象做了实验研究，实验结果表明：在一般的恒流应力条件下，栅氧化层中由空穴注入形成的空穴陷阱电荷对器件特起主要影响作用，恒流应力过程中，任何附加的电子注入都可使器件退变特性发生明显变化。实验结果还证实，漏雪崩应力期间形成的空穴陷阱电荷可明显降低器件栅氧化层的介质击穿特性。     

先进工艺对MOS器件总剂量辐射效应的影响

器件栅氧厚度的减小、场氧工艺的改变以及衬底材料的不同等都将导致MOS器件的总剂量辐射效应发生改变.亚阈斜率、阈值电压漂移、衬底技术和场氧抗辐射能力已经成为器件按比例缩小给器件带来冲击的最主要的四个方面.综述了上述条件、高k介质/硅系统以及选择SOI材料作为衬底材料对MOS器件总剂量辐射效应的影响.     

总剂量辐照对65 nm NMOSFET热载流子敏感参数的影响

为了研究总剂量辐射对纳米MOS晶体管热载流子效应的影响,对65 nm 体硅工艺的NMOS器件进行了总剂量辐射和热载流子试验,对比了辐射前后不同宽长比器件的跨导、栅极泄漏电流、线性饱和电流等电参数。结果表明,MOS器件的沟道宽度越窄,热载流子效应受辐射的影响越显著,总剂量辐射后热载流子效应对器件的损伤增强。分析认为,辐射在STI中引入的陷阱电荷是导致以上现象的主要原因。该研究结果为辐射环境下器件的可靠性评估提供了依据。     

总剂量加固对SOINMOS器件抗辐射特性的影响

采用埋层改性工艺对部分耗尽SOI NMOS器件进行总剂量加固,通过测试器件在辐射前后的电学性能研究加固对SOI NMOS器件抗辐射特性的影响。加固在埋氧层中引入电子陷阱,辐射前在正负背栅压扫描时,电子陷阱可以释放和俘获电子,导致背栅阈值电压产生漂移,漂移大小与引入电子陷阱的量有关。通过加固可以有效提高器件的抗总剂量辐射特性,电子陷阱的量对器件的抗辐射性能具有显著影响。     

非平面三栅场效应晶体管总剂量辐射研究

This paper investigates the total ionizing dose response of different non-planar triple-gate transistor structures with different fin widths. By exposing the pseudo-MOS transistor to different amounts of radiation, different interface trap densities and trapped-oxide charges can be obtained. Using these parameters together with Altal 3D simulation software, the total dose radiation response of various non-planar triple-gate devices can be simulated. The behaviors of three kinds of non-planar devices are compared.     

A new structure and its analytical breakdown model of high voltage SOI device with Step Unmovable Surface Charges of buried oxide layer

A new SOI （Silicon On Insulator） high voltage device with Step Unmovable Surface Charges （SUSC） of buried oxide layer and its analytical breakdown model are proposed in the paper. The unmovable charges are implemented into the upper surface of buried oxide layer to increase the vertical electric field and uniform the lateral one. The 2-D Poisson＇s equation is solved to demonstrate the modulation effect of the immobile interface charges and analyze the electric field and breakdown voltage with the various geometric parameters and step numbers. A new RESURF （REduce SURface Field） condition of the SOl device considering the interface charges and buried oxide is derived to maximize breakdown voltage. The analytical results are in good agreement with the numerical analysis obtained by the 2-D semiconductor devices simulator MEDICI. As a result, an 1200V breakdown voltage is firstly obtained in 3pro-thick top Si layer, 2pro-thick buried oxide layer and 70pro-length drift region using a linear doping profile of unmovable buried oxide charges.     

具有补偿埋层的槽型埋氧层SOI高压器件新结构

A new silicon-on-insulator(SOI) high-voltage MOSFET structure with a compensation layer on the trenched buried oxide layer(CL T-LDMOS) is proposed.The high density inverse interface charges at the top surface of the buried oxide layer(BOX) enhance the electric field in the BOX and a uniform surface electric field profile is obtained,which results in the enhancement of the breakdown voltage(BV).The compensation layer can provide additional P-type charges,and the optimal drift region concentration is increased in order to satisfy the reduced surface electric field(RESURF) condition.The numerical simulation results indicate that the vertical electric field in the BOX increases to 6 MV/cm and the B V of the proposed device increases by 300%in comparison to a conventional SOI LDMOS,while maintaining low on-resistance.     

一种抗总剂量辐照的新型PD SOI器件

提出了一种具有叠层埋氧层的新栅型绝缘体上硅(SOI)器件.针对SOI器件的抗总电离剂量(TID)加固方案,对绝缘埋氧层(BOX)采用了叠层埋氧方案,对浅沟槽隔离(STI)层采用了特殊S栅方案.利用Sentaurus TCAD软件,采用Insulator Fixed Charge模型设置固定电荷密度,基于0.18 μm ...     

A novel complementary N+-charge island SOI high voltage device

A new complementary interface charge island structure of SOI high voltage device (CNI SOI) and its model are presented. CNI SOI is characterized by equidistant high concentration n+-regions on the top and bottom interfaces of dielectric buried layers. When a high voltage is applied to the device, complementary hole and electron islands are formed on the two n+-regions on the top and bottom interfaces. The introduced interface charges effectively increase the electric field of the dielectric buried layer (E1) and reduce the electric field of the silicon layer (Es), which result in a high breakdown voltage (BV). The influence of structure parameters and its physical mechanism on breakdown voltage are investigated for CNI SOI. EI = 731 V/μm and BV = 750 V are obtained by 2D simulation on a l-μm-thick dielectric layer and 5-μm-thick top silicon layer. Moreover, enhanced field E1 and reduced field Es by the accumulated interface charges reach 641.3 V/μm and 23.73 V/μm, respectively.     

薄硅层阶梯埋氧PSOI高压器件新结构

基于介质电场增强ENDIF理论,提出了一种薄硅层阶梯埋氧型部分SOI(SBPSOI)高压器件结构。埋氧层阶梯处所引入的电荷不仅增强了埋层介质电场,而且对有源层中的电场进行调制,使电场优化分布,两者均提高器件的击穿电压。详细分析器件耐压与相关结构参数的关系,在埋氧层为2μm,耐压层为0.5μm时,其埋氧层电场提高到常规结构的1.5倍,击穿电压提高53.5%。同时,由于源极下硅窗口缓解SOI器件自热效应,使得在栅电压15V,漏电压30V时器件表面最高温度较常规SOI降低了34.76K。     

New High-Voltage ( $>$ 1200 V) MOSFET With the Charge Trenches on Partial SOI

A novel silicon-on-insulator (SOI) high-voltage MOSFET structure and its breakdown mechanism are presented in this paper. The structure is characterized by oxide trenches on the top interface of the buried oxide layer on partial SOI (TPSOI). Inversion charges located in the trenches enhance the electric field of the buried layer in the high-voltage blocking state, and a silicon window makes the depletion region spread into the substrate. Both of them modulate the electric field in the drift region; therefore, the breakdown voltage (BV) for a TPSOI LDMOS is greatly enhanced. Moreover, the Si window alleviates the self-heating effect. The influences of the structure parameters on device characteristics are analyzed for the proposed device structure. The TPSOI LDMOS with BV > 1200 V and the buried-layer electric field of E_I > 700 V/ mum is obtained by the simulation on a 2-mum-thick SOI layer over 2-mum-thick buried oxide layer, and its maximal temperature reduces by 19 and 8.7 K in comparison with the conventional SOI and partial SOI devices.     

Field Enhancement for Dielectric Layer of High-Voltage Devices on Silicon on Insulator

Based on the continuity theorem of electric displacement including interface charges, the enhanced dielectric layer field (ENDIF) for silicon-on-insulator (SOI) high-voltage devices is proposed. The following three approaches for enhancing the dielectric layer electric field E_I to increase the vertical breakdown voltage of a device V_B,V are presented: 1) using a thin silicon layer with a high critical electric field E_S,C ; 2) introducing a low-permittivity dielectric buried layer; and 3) implementing interface charges between the silicon and the dielectric layer. Considering the threshold energy of silicon epsiv_T, the formula of E_S,C on silicon layer thickness t_S is first obtained, which increases sharply with a decrease of t_S, and reaches up to 141 V/mum at t_S = 0.1 mum. Expressions for E_I and VByV are given, which agree well with simulative and experimental results. Based on the ENDIF, the new device structures are given, and an E_I value of 300 V/mum has been experimentally obtained for double-sided trench SOI. Moreover, several conventional SOI devices are explained well by ENDIF.     

Theoretical and experimental analysis of leakage current in InGaAsPBH lasers with p-n-p-n current blocking layers

The dependence of the leakage current in 1.3-μm InGaAsP buried heterostructure (BH) lasers with p-n-p-n current blocking layers on well number, mesa width, and carrier density has been analyzed using a two-dimensional device simulator and compared with the electroluminescence (EL) emitted from InP layers. The analysis of the minority carrier flow reveals that the electron current flowing through the p-n-p-n current blocking layers is the dominant component of the leakage current. The measured EL intensity has two peaks at both sides of the n-blocking layer apart from the active layer. The EL intensity decreases with increasing well number and carrier density of the p-blocking layer, and increases with increasing mesa width. These results are consistent with the simulations     

Negative bias illumination stress instability in amorphous InGaZnO thin film transistors with ITO local conducting buried layer

The investigations on the device instabilities of amorphous InGaZnO thin film transistors (a-IGZO TFTs) with ITO local conducting buried layer (LCBL) under the source/drain region and in the middle of the active channel region have been performed under negative bias and illumination stress. From the increased drain current of a-IGZO with ITO LCBL, one can control the drive current by modulating the length of ITO LCBL without changing the ratio of channel width and length. The reason for the less degradation of a-IGZO TFTs with LCBL under negative bias stress than that of device without LCBL was explained by the fact that ITO LCBL could act to reduce the effective energy barrier and act as a hole damping layer. However, the device degradation of a-IGZO with ITO LCBL under negative bias and illumination stress was more significant than that of one without LCBL due to the electron hole pair generation in ITO layer under illumination.