Test Generation for Mixed-Signal Devices Using Signal Flow Graphs

We describe a new reverse simulation approach to analog and mixed-signal circuit test generation that parallels digital test generation. We invert the analog circuit signal flow graph, reverse simulate it with good and bad machine outputs, and obtain test waveforms and component tolerances, given circuit output tolerances specified by the functional test needs of the designer. The inverted graph allows backtracing to justify analog outputs with analog input sinusoids. Mixed-signal circuits can be tested using this approach, and we present test generation results for two mixed-signal circuits and four analog circuits, one being a multiple-input, multiple-output circuit. This analog backtrace method can generate tests for second-order analog circuits and certain non-linear circuits. These cannot be handled by existing methods, which lack a fault model and a backtrace method. Our proposed method also defines the necessary tolerances on circuit structural components, in order to keep the output circuit signal within the envelope specified by the designer. This avoids the problem of overspecifying analog circuit component tolerances, and reduces cost. We prove that our parametric fault tests also detect all catastrophic faults. Unlike prior methods, ours is a structural, rather than functional, analog test generation method.     

Integrated Design and Test of Mixed-Signal Circuits

In this paper, the integration of design and test flows for mixed-signal circuits is discussed. The aim is to decrease test generation and debugging costs and time-to-market for the analogue blocks in mixed-signal circuits. A tool developed in order to automate the data sharing between design and test environments is described and the functionality of this tool is explained. The generation of a test plan consists of the selection of the separate test functions and addition of commands for control signal generation and tester routing. The usage of design data for each of these functions is explained and the tool is evaluated in the design and testing of a mixed-signal demonstrator circuit. Results from this experience are discussed.     

An embedded 1149.4 extension to support mixed-signal debugging

Debugging electronic circuits is traditionally done with bench equipment directly connected to the circuit under debug. In the digital domain, the difficulties associated with the direct physical access to circuit nodes led to the inclusion of resources providing support to that activity, first at the printed circuit level, and then at the integrated circuit level. The experience acquired with those solutions led to the emergence of dedicated infrastructures for debugging cores at the system-on-chip level. However, all these developments had a small impact in the analog and mixed-signal domain, where debugging still depends, to a large extent, on direct physical access to circuit nodes. As a consequence, when analog and mixed-signal circuits are integrated as cores inside a system-on-chip, the difficulties associated with debugging increase, which cause the time-to-market and the prototype verification costs to also increase.The present work considers the IEEE1149.4 infrastructure as a means to support the debugging of mixed-signal circuits, namely to access the circuit nodes and also an embedded debug mechanism named mixed-signal condition detector, necessary for watch-/breakpoints and real-time analysis operations. One of the main advantages associated with the proposed solution is the seamless migration to the system-on-chip level, as the access is done through electronic means, thus easing debugging operations at different hierarchical levels.     

混合信号集成电路边界扫描测试技术的实现

IEEE1149.4为混合信号的测试提供了一项标准,同时也提供了一种重要的可测试性设计（DFT）技术,该技术不仅可以测试芯片或PCB之间的管脚连接是否存在故障,还可以测试芯片的逻辑功能。本文以IEEE1149.4标准为基础,结合混合信号边界扫描测试系统进行了测试验证,完成对混合信号电路的参数测试。     

Efficient methods for modelling substrate coupling in mixed-signalintegrated circuits

A key problem in the design of large mixed-signal circuits is the noise caused by the coupling of digital signals into the substrate. This paper describes methods that allow circuit designers to model efficiently such substrate noise in large mixed-signal SPICE designs. In the light of these techniques a new methodology is presented for efficiently modelling the substrate noise caused by current injection and its coupling to analogue signals; this is then extended to provide a real-time modelling capability. The practicality and the numerical efficiency of the methods are demonstrated on several prototype example circuits     

Hierarchical statistical analysis of complex analog and mixed-signal systems

With increasing process parameter variations in nanometre regime, circuits and systems encounter significant performance variations and therefore statistical analysis has become increasingly important. For complex analog and mixed-signal circuits and systems, efficient yet accurate statistical analysis has been a challenge mainly due to significant simulation and modelling time. In the past years, there have been various approaches proposed for statistical analysis of analog and mixed-signal circuits. A recent work is reported to address statistical analysis for continuous-time Delta-Sigma modulators. In this article, we generalise that method and present a hierarchical method for efficient statistical analysis of complex analog and mixed-signal circuits while maintaining reasonable accuracy. At circuit level, we use the response surface modelling method to extract quadratic models of circuit-level performance parameters in terms of process parameters. Then at system level, we use behavioural models and apply the Monte-Carlo method for statistical evaluation of system performance parameters. We illustrate and validate the method on a continuous-time Delta–Sigma modulator and an analog filter.     

Challenges in analog and mixed-signal fault models

The design and testing of mixed-signal integrated circuits have enjoyed a renaissance in recent years. As is customary with past developments, however, design outpaces testing, and the drive to integrate analog and digital circuits on the same chip exacerbates the test problems. This article reviews the recent results in analog fault modeling-a critical area of mixed-signal testing-and describes the coming challenges for both industrial and university researchers     

A hierarchical analog test bus framework for testing mixed-signal integrated circuits and printed circuit boards

Progress in analog circuit testing has been hindered by the lack of structured design-for-testability methodologies. With the increasing complexity of analog/mixed-signal circuits, test program development time is now a major obstacle in achieving shorttime-to-market, while production testing cost is a prominent factor in total production cost. TheAnalog Autonomous Test is a structured design-for-testability scheme for analog circuits. Originally developed for testing analog circuits at chip level, AAT extends naturally to cover testing of mixedsignal integrated circuits mounted on printed circuit boards. With the addition of an analog test bus to PCBs, testability for analog components (bothcore circuits andglue circuits) can be improved, in a manner similar to that achieved for digital boards by the IEEE 1149.1 boundary scan scheme. Details on the implementation of thisAnalog Autonomous Test Bus, both at chip level and board level, are presented here. Its limitations and potential applications are also discussed.     

通信电路LSI／VLSI发展的新领域

本文介绍了通信技术和通信电路的发展情况,论述了通信技术和通信电路与通信LSI/VLSI发展的密切关系以及通信电路技术的特点;并通过实例说明通信LSI/VLSI中典型的电路和技术。     

Computer-aided design considerations for mixed-signal coupling inRF integrated circuits

This paper reviews computer-aided design techniques to address mixed-signal coupling in integrated circuits, particularly wireless RF circuits. Mixed-signal coupling through the chip interconnects, substrate, and package is detrimental to wireless circuit performance as it can swamp out the small received signal prior to amplification or during the mixing process. Specialized simulation techniques for the analysis of periodic circuits in conjunction with semi-analytical methods for chip substrate modeling help analyze the impart of mixed-signal coupling mechanisms on such integrated circuits. Application of these computer-aided design techniques to real-life problems is illustrated with the help of a design example. Design techniques to mitigate mixed-signal coupling can be determined with the help of these modeling and analysis methods     

A hierarchical analog test bus framework for testing mixed-signal integrated circuits and printed circuit boards

Progress in analog circuit testing has been hindered by the lack of structured design-for-testability methodologies. With the increasing complexity of analog/mixed-signal circuits, test program development time is now a major obstacle in achieving shorttime-to-market, while production testing cost is a prominent factor in total production cost. TheAnalog Autonomous Test is a structured design-for-testability scheme for analog circuits. Originally developed for testing analog circuits at chip level, AAT extends naturally to cover testing of mixedsignal integrated circuits mounted on printed circuit boards. With the addition of an analog test bus to PCBs, testability for analog components (bothcore circuits andglue circuits) can be improved, in a manner similar to that achieved for digital boards by the IEEE 1149.1 boundary scan scheme. Details on the implementation of thisAnalog Autonomous Test Bus, both at chip level and board level, are presented here. Its limitations and potential applications are also discussed.     

伪随机测试生成在混合电路参数测试中的应用

混合信号电路在通信、多媒体等领域获得越来越广泛的应用。然而,测试也变得更复杂。传统上对模拟电路的测试采用的是直接功能测试,即直接测量电路的性能参数Z。采用该测试方法,其缺点是测试时间长、测试设备昂贵、且精度差。本文针对这一问题进行研究,详细讨论了利用伪随机技术进行混合信号电路测试的方法。     

Fault detection in analog and mixed-signal circuits by using Hilbert–Huang transform and coherence analysis

Using Hilbert–Huang transform (HHT) and coherence analysis, a signature extraction method for testing analog and mixed-signal circuits is proposed in this paper. The instantaneous time–frequency signatures extracted with HHT technique from the measured signal of circuits under test (CUT) are used for faults detection that is implemented through comparing the signatures of faulty circuits with that of the fault-free circuit. The coherence functions of the instantaneous time–frequency signatures and its integral help to test faults in the faulty dictionary according to the minimum distance criterion. The superior capability of HHT-based technique, compared to traditional linear techniques such as the wavelet transform and the fast Fourier transform, is to obtain the subtle time-varying signatures, i.e., the instantaneous time–frequency signatures, and is demonstrated by applying to Leapfrog filter, a benchmark circuit for analog and mixed-signal testing, with 100% of F.D.R (fault detection rate) in the best cases and with the least 24.2% of F.L.R. (fault localization rate) with one signature.     

一种混合信号边界扫描测试系统的设计

IEEE 1149.4的推出为混合信号测试提供了一个标准,推动了混合信号边界扫描测试技术的研究。简要介绍了IEEE 1149.4标准及混合信号测试方法,并根据标准定义的测试结构设计出一种混合信号边界扫描测试系统。经过测试验证,该系统能够对混合信号电路进行互连测试和参数测试,可实现准确的故障诊断,具有一定的实用价值。     

Substrate coupling in digital circuits in mixed-signal smart-power systems

This paper describes theoretical and experimental data characterizing the sensitivity of nMOS and CMOS digital circuits to substrate coupling in mixed-signal, smart-power systems. The work presented here focuses on the noise effects created by high-power analog circuits and affecting sensitive digital circuits on the same integrated circuit. The sources and mechanism of the noise behavior of such digital circuits are identified and analyzed. The results are obtained primarily from a set of dedicated test circuits specifically designed, fabricated, and evaluated for this work. The conclusions drawn from the theoretical and experimental analyses are used to develop physical and circuit design techniques to mitigate the substrate noise problems. These results provide insight into the noise immunity of digital circuits with respect to substrate coupling.     

Behavioral Fault Modeling and Simulation Using VHDL-AMS to Speed-Up Analog Fault Simulation

One of the main requirements for generating test patterns for analog and mixed-signal circuits is fast fault simulation. Analog fault simulation is much slower than the digital equivalent. This is due to the fact that digital circuit simulators use less complex algorithms compared with transistor-level simulators. Two of the techniques to speed up analog fault simulation are: fault dropping/collapsing, in which faults that have similar circuit responses compared with the fault-free circuit response and/or with another faulty circuit response are considered equivalent; and behavioral/macro modeling, whereby parts of the circuit are modeled at a more abstract level, therefore reducing the complexity and the simulation time. This paper discusses behavioral fault modeling to speed-up fault simulation for analog circuits.     

Mixed-Signal Circuit Classification in a Pseudo-Random Testing Scheme

Pseudo-random testing techniques for mixed-signal circuits offer several advantages compared to explicit time-domain and frequency-domain test methods, especially in a BIST structure. To fully exploit these advantages a suitable choice of the pseudo-random input parameters should be done and an investigation on the accuracy of the circuit response samples needed to reduce the risk of misclassification should be carried out. Here these issues have been addressed for a testing scheme based on the estimation of the impulse response of the device under test (DUT) by means of input-output cross-correlation. Moreover, new acceptance criteria for the DUT are suggested which solve some ambiguity problems arising if the classification of the DUT as good or bad is based on a few samples of the cross-correlation function. Examples of application of the proposed techniques to real cases are also shown in order to assess the impact of the measurement system inaccuracies on the reliability of the test.     

Analytical and experimental verification of substrate noise spectrum for mixed-signal ICs

In this paper, the most relevant characteristics of the substrate noise spectrum for mixed-signal integrated circuits (ICs) are derived using a simple analytical model. These characteristics are related to parameters of the digital circuit, the package + printed circuit board parasitics, and other elements of the mixed-signal IC. The model used to derive the substrate noise spectral characteristics includes the statistical properties of the digital switching current waveform and the coupling transfer function between the digital power supply nodes and the substrate node of the victim circuitry. The results of the work are validated experimentally on a mixed-signal prototype.