收视价值的迷失 高端人群在远离卫视 2008目睹中国电视之怪现状

近两个月来,本刊网站的论坛里又不太安静。有个叫"高清迷"的香港网友遭到了广东一些网友的质疑。彼此论战的焦点大部分在说香港电视好看或不好看。"高清迷"网友说大陆电视越来越好,水平已经超过香港的电视节目。广东网友们则是缅怀香港电视的辉煌历史。这原本是简单的我说你好你说我好,互相捧场的事情,但是网络的奇妙性在于事情并没有朝积极的方向发展,其结果是吵架不可避免的发生了。外来的和尚是不是会念经,我们先不去管他。重要的是我们要弄清楚自己是怎么回事。本文,是专业电视人对我国各省卫视台做的调查评估。让我们了解一下我国的电视台的现状吧。     

上海慕尼黑电子展暨同期展会见闻

2007年3月21日～23日的上海新国际博览中心是格外的热闹,超过2万名来自电子行业的专业观众汇聚与此.吸引他们来到这里的原因就是慕尼黑上海电子展,慕尼黑上海激光、光电展(LASER. World of Photonics China)、中国国际半导体设备、材料、生产和服务展览暨研讨会(SEMICON China),以及中国国际电子电路展览会(CPCA Show)四大电子业权威品牌展联合在此举行.     

ADSL服务

现在使用ADSL上宽带网的用户是越来越多了,对ADSL设备的维护也成了一个不容忽视的问题.只有维护保养好它,不但让你的"宽带之旅"省心又省力,还能延长其寿命.ADSL的维护可分为软件和硬件两个方面来分析,软件主要是PPPOE协议的问题,和计算机本身的气操作系统,和网卡方面的事情.硬件主要是局端的节点设备,和用户端猫的问题.还有通信的线路等一些因素.     

命题逻辑中代数学的影子

命题逻辑是一个以命题为基本研究对象的数学化的逻辑系统,命题逻辑是数理逻辑的基础,也是计算机科学与技术的理论基础.为了深入理解命题逻辑,将命题逻辑与一般的代数学进行比较,从6个方面简要总结和论述命题逻辑中代数学的一些思想和方法,使得读者能从中体会到代数学的一些思想和方法在命题逻辑中的应用.     

从跨国公司CEO扎堆访华说起

11月1日,似乎是个好日子!来自英特尔、EMC、思科的3位跨国公司CEO均选在这一天访华,并宣布其在中国市场大手笔的战略投入. 11月2日,来自全球最大显卡芯片厂商NVIDIA公司的联合创始人、总裁兼CEO黄仁勋借访华之际,在清华大学美术学院报告厅进行了"GPU--还原一个真世界"的演讲.     

不一样的热插拔(hot swap)控制器

引言 热插拔(hot swapping)的定义是从一块正在通电运作中的背板(backplane)上插入或移除电路板.这项技术被广泛应用在电信服务器(telecom servers)、USB界面、火线(firewire)界面和 CompactPCI应用等[参考1].这种技术可在维持系统背板的电压下,更换发生故障的电路板,而同时系统中其它正常的电路板仍可保持运作.     

FEW-NNN: A Fuzzy Entropy Weighted Natural Nearest Neighbor Method for Flow-Based Network Traffic Attack Detection

Attacks such as APT usually hide communication data in massive legitimate network traffic, and mining structurally complex and latent relationships among flow-based network traffic to detect attacks has become the focus of many initiatives. Effectively analyzing massive network security data with high dimensions for suspicious flow diagnosis is a huge challenge. In addition, the uneven distribution of network traffic does not fully reflect the differences of class sample features, resulting in the low accuracy of attack detection. To solve these problems, a novel approach called the fuzzy entropy weighted natural nearest neighbor(FEW-NNN) method is proposed to enhance the accuracy and efficiency of flowbased network traffic attack detection. First, the FEW-NNN method uses the Fisher score and deep graph feature learning algorithm to remove unimportant features and reduce the data dimension. Then, according to the proposed natural nearest neighbor searching algorithm(NNN_Searching), the density of data points, each class center and the smallest enclosing sphere radius are determined correspondingly. Finally, a fuzzy entropy weighted KNN classification method based on affinity is proposed, which mainly includes the following three steps: 1、 the feature weights of samples are calculated based on fuzzy entropy values, 2、 the fuzzy memberships of samples are determined based on affinity among samples, and 3、 K-neighbors are selected according to the class-conditional weighted Euclidean distance, the fuzzy membership value of the testing sample is calculated based on the membership of k-neighbors, and then all testing samples are classified according to the fuzzy membership value of the samples belonging to each class;that is, the attack type is determined. The method has been applied to the problem of attack detection and validated based on the famous KDD99 and CICIDS-2017 datasets. From the experimental results shown in this paper, it is observed that the FEW-NNN method improves the accuracy and efficiency of flow-based network traffic attack detection.     

追日

去年10月一个温暖的早晨,在澳大利亚内陆深处,14名麻省理工学院的学生和校友上午6点就爬出了他们的睡袋,准备车队,进行又一天的艰苦驾驶,在护卫队的护送下,他们驶过一段平坦、笔直、炎热、灰尘弥漫的道路.领头的车辆迎着其他车流,形成了一个缓冲带,一辆货车断后以监测整个队伍的进程.     

Design of Diode Type Un-Cooled Infrared Focal Plane Array Readout Circuit

The diode infrared focal plane array uses the silicon diodes as a sensitive device for infrared signal measurement. By the infrared radiation, the infrared focal plane can produces small voltage signals. For the traditional readout circuit structures are designed to process current signals, they cannot be applied to it. In this paper,a new readout circuit for the diode un-cooled infrared focal plane array is developed. The principle of detector array signal readout and small signal amplification is given in detail. The readout circuit is designed and simulated by using the Central Semiconductor Manufacturing Corporation (CSMC) 0.5 μm complementary metal-oxide-semiconductor transistor (CMOS) technology library. Cadence Spectre simulation results show that the scheme can be applied to the CMOS readout integrated circuit (ROIC) with a larger array, such as 320×240 size array.     

产业化新年迈出第一步龙芯3000万欲卖5年产销权

2007年的元旦前,业界对商品化"中国芯"的最后一丝担忧得到了舒缓. 12月27日,神州龙芯集成电路设计有限公司对外公布,中科院计算所已选择与欧洲最大的半导体公司意法半导体,将就龙芯2E的生产和销售展开合作.双方合作细节至今未见披露,但知情人士向透露,双方已经达成初步意向,即意法半导体将出资3000万元购买龙芯2E处理器5年产销权,在此期间,这家法国公司每销售一枚处理器将向北京神州龙芯公司提交2美元的专利许可费.中科院计算所所长李国杰向证实,正式确认合作的时刻将等到今年3月,届时双方将齐聚人民大会堂公布合作详情.     

Design of testable reversible latches by using a novel efficient implementation of Fredkin gate

ABSTRACT

Energy dissipation caused by information loss in irreversible computations will be an important limitation for the development of nano-scale circuits in the near future. Reductions in energy dissipation comprise one of the important goals of nanotechnology-based methods, including Quantum dot Cellular Automata (QCA), and so it is desirable to consider reversibility in the design of QCA circuits. In this research, a novel reversible Fredkin gate based on QCA is proposed, which is more efficient and less complex than the conventional Fredkin gate. Conservative reversible logic is parity preserving; hence, any permanent or transient fault can be caused a mismatch between the inputs and the outputs and can be concurrently detected if a reversible circuit is implemented with the conservative Fredkin gate. A single missing/additional cell defect is investigated in the proposed Fredkin gate and fault patterns are presented. To demonstrate the efficiency of the proposed design, some testable reversible sequential elements, such as D-latch, JK-latch, T-latch and SR-latch, are designed by using it. Our proposed concurrent testable designs greatly reduce the occupied area and maximise the circuit density in comparison with previously reported designs. The proposed designs are simulated and verified using QCA Designer ver.2.0.3 and HDLQ.     

基于QCA的五输入Majority门设计及应用

Majority门作为多数逻辑电路的基本逻辑单元,其性能直接影响整体电路的质量.使用量子元胞自动机（QCA）设计Majority门具有结构简单的优点.本文提出了一种三层电路实现五输入Majority门的设计,并以此设计了全加器,进一步应用于多位加法器和乘法器中,与已发表的电路设计比较表明,其版图使用面积和元胞数有明显的减少,加法器元胞数和面积改进最高可达43%和87.2%,乘法器元胞数和面积改进最高可达48.2%和100%.     

基于量子元胞自动机的奇偶校验系统分块设计

量子元胞自动机(QCA)是一种纳米范围内不含晶体管的计算范例。基于QCA提出了QCA奇偶校验系统电路的分块设计方法。首先设计了异或门、奇偶判断单元,再运用分块设计思想构建了奇数产生电路和奇偶校验电路的结构,所设计的电路拥有尺寸极小和功耗极低等优点,QCADesigner软件仿真结果验证了设计的有效性。     

Mixed logic style adder circuit designed and fabricated using SOI substrate for irradiation-hardened experiment

This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit’s delay, power and power–delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.     

On the design robustness of threshold logic gates using multi-inputfloating gate MOS transistors

In this paper, the design robustness of logic circuits implemented as threshold logic gates with multi-input floating gate transistors is analyzed. The parameter variations of the basic components, namely the coupling capacitances of the floating gate MOSFETs and the sensing circuits for obtaining full logic levels, are investigated separately using appropriate array test structures. It is found that the dominant mismatch originates from the input offset voltage variations of the sensing circuits. Methods are presented for estimating the yield of a given logic circuit from the measured parameter distributions. The estimations are verified with measured data of a multiplier cell and of the encoding logic in a parallel fingerprint sensor architecture. Considerations are given for robust design of circuits based on threshold logic gates that use floating gate transistors     

基于忆阻器的乘法器电路设计

忆阻器作为一种非易失性的新型电路元件,在数字逻辑电路中具有良好的应用前景。目前,基于忆阻器的逻辑电路主要涉及全加器、乘法器以及异或(XOR)和同或(XNOR)门等研究,其中对于忆阻乘法器的研究仍比较少。该文采用两种不同方式来设计基于忆阻器的2位二进制乘法器电路。一种是利用改进的“异或”及“与”多功能逻辑模块,设计了一个2位二进制乘法器电路,另一种是结合新型的比例逻辑,即由一个忆阻器和一个NMOS管构成的单元门电路设计了一个2位二进制乘法器。对于所设计的两种乘法器进行了比较,并通过LTSPICS仿真进行验证。该文所设计的乘法器仅使用了2个N型金属-氧化物-半导体(NMOS)以及18个忆阻器(另一种为6个NMOS和28个忆阻器),相比于过去的忆阻乘法器,减少了大量晶体管的使用。     

Design of high speed and low power 4-bit comparator using FGMOS

This paper presents a novel low power and high speed 4-bit comparator extendable to 64-bits using floating-gate MOSFET (FGMOS). Here, we have exploited the unique feature of FGMOS wherein the effective voltage at its floating-gate is the weighted sum of many input voltages which are capacitively coupled to the floating-gate. The performance of proposed 4-bit comparator circuit has been compared with other comparator circuits designed using CMOS, transmission gate (TG), pass transistor logic (PTL) and gate diffusion input (GDI) technique. The proposed FGMOS based 4-bit comparator have shown remarkable performance in terms of transistor count, speed, power dissipation and power delay product besides full swing at the output in comparison to the existing comparator designs available in literature. Thus the proposed circuit can be viable option for high speed and low power applications. The performance of the proposed FGMOS based 4-bit comparator has been verified through OrCAD PSpice simulations through circuit file/schematics using level 7 parameters obtained from TSMC in 0.13 μm technology with the supply voltage of 1 V.     

Design of sequential circuits by quantum-dot cellular automata

This paper proposes a detailed design analysis of sequential circuits for quantum-dot cellular automata (QCA). This analysis encompasses flip-flop (FF) devices as well as circuits. Initially, a novel RS-type FF amenable to a QCA implementation is proposed. This FF extends a previous threshold-based configuration to QCA by taking into account the timing issues associated with the adiabatic switching of this technology. The characterization of a D-type FF as a device consisting of an embedded wire is also presented. Unique timing constraints in QCA sequential logic design are identified and investigated. An algorithm for assigning appropriate clocking zones to a QCA sequential circuit is proposed. A technique referred to as stretching is used in the algorithm to ensure timing and delay matching. This algorithm relies on a topological sorting and enumeration step to consistently traversing only once the edges of the graph representation of the QCA sequential circuit. Examples of QCA sequential circuits are provided.     

Efficient design of parity preserving logic in quantum-dot cellular automata targeting enhanced scalability in testing

Design of parity preserving logic based on emerging nanotechnology is very limited due to present technological limitation in tackling its high error rate. In this work, Quantum-dot cellular automata (QCA), a potential alternative to CMOS, is investigated for designing easily testable logic circuit. A novel self-testable logic structure referred to as the testable-QCA (t-QCA), using parity preserving logic, is proposed. Design flexibility of t-QCA then evaluated through synthesis of standard functions. The programmability feature of t-QCA is utilized to implement an ALU, realizing six important functions. Although the parity preservation property of t-QCA enables concurrent detection of permanent as well as the transient faults, an augmented test logic circuit (TC) using QCA primitives has been introduced to cover the cell defects in nanotechnology. Experimental results establish the efficiency of the proposed design that outperforms the existing technologies in terms of design cost and test overhead. The achievement of 100% stuck-at fault coverage and the 100% fault coverage for single missing/additional cell defects in QCA layout of the t-QCA gate, address the reliability issues of QCA nano-circuit design.     

Design and comparison of new fault-tolerant majority gate based on quantum-dot cellular automata

Quantum-dot cellular automata (QCA) is increasingly valued by researchers because of its nanoscale size and very low power consumption.However,in the manufacture of nanoscale devices prone to various forms of defects,which will affect the subsequent circuits design.Therefore,fault-tolerant QCA architectures have become a new research direction.The purpose of this paper is to build a novel fault-tolerant three-input majority gate based on normal cells.Compared with the previous structures,the majority gate shows high fault tolerance under single-cell and double-cell omission defects.In order to examine the functionality of the proposed structure,some physical proofs under single cell missing defects are provided.Besides,two new fault-tolerant decoders are constructed based on the proposed majority gate.In order to fully demonstrate the performance of the proposed decoder,the previous decoders were thoroughly compared in terms of fault tolerance,area and delay.The result shows that the proposed design has a good fault tolerance characteristic,while the performance in other aspects is also quite good.