A high-speed 128-kb MRAM core for future universal memory applications

A 128-kb magnetic random access memory (MRAM) test chip has been fabricated utilizing, for the first time, a 0.18-/spl mu/m V/sub DD/=1.8 V logic process technology with Cu metallization. The presented design uses a 1.4-/spl mu/m/sup 2/ one-transistor/one-magnetic tunnel junction (1T1MTJ) cell and features a symmetrical high-speed sensing architecture using complementary reference cells and configurable load devices. Extrapolations from test chip measurements and circuit assessments predict a 5-ns random array read access time and random write operations with <5-ns write pulse width.     

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes

An 87.7 mm² 1.6 GB/s 128 Mb chain FeRAM with 130 nm 4-metal CMOS process is demonstrated. In addition to small bitline capacitance inherent to chain FeRAM architecture, three new FeRAM scaling techniques - octal bitline architecture, small parasitic capacitance sensing scheme, and dual metal plateline scheme - reduce bitline capacitance from 100 fF to 60 fF. As a result, a cell signal of ±220 mV is achieved even with the small cell size of 0.252 ?m². An 800 Mb/s/pin read/write bandwidth at 400 MHz clock is realized by installing SDRAM compatible DDR2 interface, and performance is verified by simulation. The internal power-line bounce noise due to 400 MHz clock operation is suppressed to less than 50 mV by an event-driven current driver, which supplies several hundreds of mA of current within 2 ns response. The precise timing and voltage controls are achieved by using the data stored in a compact FeRAM-fuse, which consists of extra FeRAM memory cells placed in edge of normal array instead of conventional laser fuse links. This configuration minimizes area penalty to 0.2% without cell signal degradation.     

A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM

An ultrahigh-speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65-ns address-access time, 0.80-ns write-pulse width, and 30.24-μm ² memory cells has been developed using 0.3-μm BiCMOS technology. Two key techniques for achieving ultrahigh speed are an ECL decoder/driver circuit with a BiCMOS inverter and a write-pulse generator with a replica memory cell. These circuit techniques can reduce access time and write-pulse width of the 72-kb RAM macro to 71% and 58% of those of RAM macros with conventional circuits. In order to reduce crosstalk noise for CMOS memory-cell arrays driven at extremely high speeds, a twisted bit-line structure with a normally on MOS equalizer is proposed. These techniques are especially useful for realizing ultrahigh-speed, high-density SRAM's, which have been used as cache and control storages in mainframe computers     

A low power wireless node for contact and contactless heart monitoring

Ubiquitous vital signs sensing and processing are promising alternatives to conventional clinical and ambulatory healthcare. Novel sensors, low power solutions for processing and wireless connectivity are creating new opportunities for wearable devices which allow continuous and long term monitoring, while maintaining freedom of movement for the users. This paper presents a low-power embedded platform with novel high sensitivity electric potential dry surface sensors that can be used in either contact or non-contact mode to measure biomedical signals. The proposed low power system is optimized to compute the heart rate and respiratory rate close to the sensors. This approach reduces the amount of data that needs to be transmitted to a host device. It allows also the platform to be autonomous and wearable or even be used in cars for applications such as driver drowsiness detection. Experimental measurements show the acquisition and the processing of data from sensors and the low power consumption achieved with the node in different modes of operation.     

A/D转换器和微控制器--走向集成

应用情况决定了是否应将A/D转换器集成进控制器     

A 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) scheme

This paper reports a 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using a novel two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) and sense wordline/bitline (SWL/SBL) tag-sense amplifiers with an eight-transistor (8-T) tag cell in Level 2 (L2) and a 10-T shrunk logic swing (SLS) memory cell. with the ground/floating (G/F) data sense amplifier in Level 1 (L1) for high-speed operation for low-voltage low-power VLSI system applications. Owing to the reduced loading at the SWL in the new 11-T tag cell using the WLOTC scheme, the 10-T SLS memory cell with G/F sense amplifier in L1, and the split comparison of the index signal in the 8-T tag cells with SWL/SBL tag sense amplifiers in L2, this 0.8-V cache memory implemented in a 1.8-V 0.18-/spl mu/m CMOS technology has a measured L1/L2 hit time of 11.6/20.5 ns at the average dissipation of 0.77 mW at 50 MHz.     

A 32-Mb chain FeRAM with segment/stitch array architecture

This paper demonstrates the 32-Mb chain ferroelectric RAM (chain FeRAM) with 0.2-/spl mu/m three-metal CMOS technology. A small die size of 96 mm/sup 2/ and a high cell/chip area efficiency of 65.6% are realized not only by the small cell size using capacitor-on-plug technology but also by two key techniques that utilize the three-metal process: 1) a compact memory cell block structure that eliminates plateline area and reduces block selector area and 2) the segment/stitch array architecture which reduces the area of row decoders and plate drivers. As a result, the average cell size shrinks to 1.875 /spl mu/m/sup 2/, which is smaller than a 0.13-/spl mu/m SRAM cell, and the chip size is reduced to 70% of the chain FeRAM of conventional configuration with two-metal process. Moreover, a power-on/off sequence suitable to the chain FeRAM is introduced to protect the memory cell data from the startup noise. Compatibility with low-power SRAM is a key issue for mobile applications. The low-standby-current bias generator is introduced and the standby current of the chip is suppressed to 3 /spl mu/A. The modified address access mode is also adopted to eliminate the need of intentional address transition after the startup of the chip. The chip enable access time was 50 ns and cycle time was 75 ns at 3.0-V V/sub dd/.     

A 1000 FPS at 128/spl times/128 vision processor with 8-bit digitized I/O

This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of processing elements, arranged to operate in accordance with the principles of single instruction multiple data (SIMD) computing architectures. This chip, implemented in a 0.35-/spl mu/m fully digital CMOS technology, contains /spl sim/ 3.75 M transistors and exhibits peak performance figures of 330 GOPS (8-bit equivalent giga-operations per second), 3.6 GOPS/mm/sup 2/ and 82.5 GOPS/W. It includes structures for image acquisition and for image processing, meaning that it does not require a separate imager for operation. At the sensory side, integration and log-compression sensing circuits are embedded, thus allowing the chip to handle a large variety of illumination conditions. At the processing plane, analog and digital circuits are employed whose parameters can be programmed and their architecture reconfigured for the realization of software-coded processing algorithms. The chip provides, and accepts, 8-bit digitized data through a 32-bit bidirectional data bus which operates at 120 MB/s. Experimental results show that frame rates of 1000 frames per second (FPS) can be achieved under room illumination conditions; applications using exposures of about 50 /spl mu/s have been recently reached by using special illumination setups. The chip can capture an image, run approximately 150 two-dimensional linear convolutions, and download the result in 8-bit digital format, in less than 1 ms. This feature, together with the possibility of executing sequences of user-definable instructions (stored on a full-custom 32-kb on-chip memory), and storing intermediate results (up to 8 grayscale images) makes the chip a true general-purpose sensory/processing device.     

一种新的铁电电容模型及其在1T/1C FeRAM中的应用

随着集成铁电工艺的迅速发展和铁电电容的广泛应用 ,铁电电容模型的缺乏已成为制约基于铁电电容电路设计和优化的瓶颈。文中提出的非线性双电容铁电电容模型是线性双电容铁电电容模型的改进 ,它不仅与线性双电容模型一样易于用宏模型实现 ,而且比后者具有更高的精度和更简单的控制方式。以 1 T/1 C单元作为基于铁电电容电路设计优化的实例 ,定性分析了位线寄生电容对读出窗口的影响 ,并在 HSPICE中用非线性双电容模型进行了仿真 ,得到位线寄生电容与 1 T/1 C单元铁电电容比例 (CBL/CF E)对读出窗口的最优值 :CBL/CF E=2 .4     

A 270-kb/s 35-mW modulator IC for GSM cellular radio hand-heldterminals

The modulator IC is a mixed analog/digital transceiver component in a chip set that is designed for the hand-held terminals of the pan-European 900-MHz Groupe Special Mobile (GSM) digital cellular radio network. The concept of the radio-frequency environment in which the circuit is used is explained, focusing on the differences in existing systems. The architecture and different functions of the modulator circuit and details of the digital and analog processing in the transmission mode are discussed. The receiving mode, which is mostly based on analog processing, is highlighted. The device generates Gaussian minimum-shift-keying (GMSK) modulation and converts the received signal to 8-b words after filtering. The modulator IC uses digital waveform generation and a quadrature signal representation. This device is implemented in a 1.5-μm CMOS technology. The power consumption is less than 35 mW from a 5-V supply     

用于非破坏性读出铁电存储器的MFIS结构的机理研究

分析了 MFIS FET的工作机理以及影响 MFIS电容的存储窗口特性的因素 ,提出用存储窗口与铁电薄膜正、负矫顽电压的差值来评价存储窗口特性 ,制备了 Au/Cr/PZT/Zr O2 /Si的 MFIS结构并研究了其存储窗口特性 ,存储窗口随 Zr O2 的厚度变化呈现一个极大值 ,甚至会出现 C-V曲线方向的变化 ,而 PZT薄膜的厚度增大会导致窗口增大 ,这是由于界面效应以及在铁电层和介质阻挡层上电压分配关系的不同而造成的 ,这一结果与前面的分析很好地吻合。当 Zr O2 和 PZT的厚度分别为 3 0 nm和 2 5 0 nm、扫描电压从 -5 V到 +5 V变化时 ,存储窗口大小为 2 .5 V,与相应的铁电薄膜的正、负矫顽电压的差值的比为 0 .8。     

以MCS-51单片机为核心研制的四脚步行机器人分布式控制系统

本文描述一个四脚步行机器人的微处理器分布式实时控制系统,介绍系统的主从分布式松耦合结构.该系统采用了2只8088CPU,一只8087协处理器和14只8031单片机.文中设计了一个系统管理员来负责整个系统的时序控制,用C写的系统管理程序具有移植性好和执行速度快的特点.而松耦合的任务处理器则根据系统管理员的指令来执行特定的算法.本文将首先介绍把整个系统控制分解为一组单独执行的任务(即电机伺服)的方法,然后重点讨论基于8031单片机的全数字式直流伺服系统的设计以及步行机的实时控制等问题.模块化设计、并行处理、数字化和分布控制技术使得整个控制系统的性能和可靠性均得到了提高.     

A contactless electrical energy transmission system for portable-telephone battery chargers

A high-performance contactless electrical energy transmission (CEET) technique which employs the inductive energy transmission principle is described. The proposed technique enables the implementation of high-efficiency high-power-density fully regulated CEET systems suitable for applications with a wide input and load range. A high efficiency of the system is achieved by recovering the energy stored in the leakage inductances of the transformer by incorporating them in the operation of the circuit, and by employing high-frequency-inverter and controlled-rectifier topologies that allow a controlled bidirectional power flow through the transformer. In addition, a feedforward variable-switching-frequency control of the inverter is used to maintain approximately constant power transfer through the transformer with the input voltage changes, whereas the output-side rectifier employs a local pulsewidth-modulation control to achieve a tight regulation of the output in the presence of load variations. Specifically, the described CEET system is suitable for use in universal-input battery chargers.     

A 128K word/spl times/8 bit dynamic RAM

A 1-Mb DRAM with 128K/spl times/8 bit organization is described. In designing the circuit, half V/SUB cc/ bit line precharge with dummy reverse circuits was adopted for noise reduction. The noise is estimated using a three-dimensional capacitance calculation. In realizing the chip, a 1-/spl mu/m NMOS process with double-level aluminum wiring was used.     

A 35-ns 128K/spl times/8 CMOS SRAM

A 128 K/spl times/8-b CMOS SRAM with TTL input/output levels and a typical address access time of 35 ns is described. A novel data transfer circuit with dual threshold level is utilized to obtain improved noise immunity. A divided-word-line architecture and an automatic power reduction function are utilized to achieve a low operational power of 10 mW at 1 MHz, and 100 mW at 10 MHz. A novel fabrication technology, including improved LOCOS and highly stable polysilicon loads, was introduced to achieve a compact memory cell which measures 6.4/spl times/11.5 /spl mu/m/SUP 2/. Typical standby current is 2 /spl mu/A. The RAM was fabricated with 1.0-/spl mu/m design rules, double-level polysilicon, and double-level aluminum CMOS technology. The chip size of the RAM is 8/spl times/13.65 mm/SUP 2/.     

A comprehensive delay macro modeling for submicrometer CMOS logics

The increasing need for high-performance, cost-effective, application-specific integrated circuits, associated to the reduction of design cycle time, compels designers to manage and optimize the circuit speed performance at each step of the design flow. Circuits are usually designed at gate level; the gate selection or sizing and their placement are driven by estimated delay, hence the need for accurate estimations at the logical level. In the submicrometer range, the gap between gate-level logical estimations and transistor-level electrical simulations dramatically increases. We propose here a comprehensive analytical modeling of the speed performance of CMOS gates with an accuracy comparable to electrical simulators. A design-oriented expression of delay is first developed for CMOS inverters, considering input slope, input-to-output capacitance coupling, and short-circuit current effects. The extension to more complex gates is proposed using a serial array reduction technique taking account of the gate input dependency and the input-slope-induced nonlinearity. Validations are obtained over a large range of design, load, and input slope conditions by comparison with SPICE simulations (level 6 with 0.65-μm foundry specified card model) used as a reference     

A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation

Low-voltage operation for memories is attractive because of lower leakage power and active energy, but the challenges of SRAM design tend to increase at lower voltage. This paper explores the limits of low-voltage operation for traditional six-transistor (6T) SRAM and proposes an alternative bitcell that functions too much lower voltages. Measurements confirm that a 256-kb 65-nm SRAM test chip using the proposed bitcell operates into sub-threshold to below 400 mV. At this low voltage, the memory offers substantial power and energy savings at the cost of speed, making it well-suited to energy-constrained applications. The paper provides measured data and analysis on the limiting effects for voltage scaling for the test chip     

A 1-V 128-kb four-way set-associative CMOS cache memory usingwordline-oriented tag-compare (WLOTC) structure with thecontent-addressable-memory (CAM) 10-transistor tag cell

This paper reports a 1-V 128-kb four-way set-associative CMOS cache memory implemented by a 0.18-μm CMOS technology using wordline-oriented tag-compare (WLOTC) structure with the 10-transistor tag cell usually for content-addressable memory (CAM) for low-voltage low-power VLSI system application. Owing to the WLOTC structure with the CAM 10-transistor tag cell for accommodating the one-step hit/miss generation and the dynamic pulse generators for realizing read-enable signals, a small hit access time (3.5 ns), low power consumption (4.1 mW at 50 MHz), and good expansion capability without sacrificing speed have been obtained     

A 160-kb/s digital subscriber loop transceiver with memory compensation echo canceller

A full-duplex transceiver chip incorporating an adaptive echo canceling modem and a 2.048-Mb/s serial interface is described. The device provides a full-duplex communication link at 160 or 80 kb/s on up to 4 or 5 km, respectively, of 0.5-mm twisted-pair cable. Full integration is achieved through the use of RAM-based sign-algorithm echo-cancellation, biphase line code, a fixed switched-capacitor equalizer, and a digital phase locked loop. The authors emphasize system design considerations and a chip architecture minimizing power dissipation, silicon area, and off-chip components. A double poly 3-/spl mu/m CMOS technology is used to implement the 5-V 22-pin device which dissipates less than 50 mW and occupies 27.7 mm/SUP 2/.     

Control scheme for micro/macro/megacell-overlaying cellular systemincluding an LEO satellite system

A flexible radio resource management technique is proposed for multilayered cellular systems that consist of megacells using LEO satellites, and macrocell and microcell overlaid terrestrial cellular systems. In the proposed system, the radio spectra for microcell and macrocell terrestrial systems are adaptively and autonomously shared according to the traffic conditions of each microcell. Moreover, the radio resource for a satellite system is also dynamically shared by a temporarily unused satellite band. Computer simulation confirms that the proposed system can achieve high system capacity by reusing the radio resource allocated for the satellite band