A 2-μm BiCMOS process utilizing selective epitaxy

A 2-μm BiCMOS process designed for 10-V analog/digital applications is described. This process utilizes selective epitaxial growth to integrate a vertical n-p-n bipolar structure with an estimated cutoff frequency of 5 GHz and nonoptimized vertical p-n-p structure into a 2-μm CMOS process with a poly-to-n⁺ capacitors. The insertion of the bipolar structures is accomplished with only two added masking steps and with no change to the critical process parameters which determine the performance of the MOS transistors     

A BiCMOS technology with 660-MHz vertical p-n-p transistor foranalog/digital ASICs

A fully complementary BiCMOS technology based on a 2-μm process designed for 12-V analog/digital applications is described. In this technology, a triple diffused vertical p-n-p transistor and n-p-n bipolar and CMOS devices are integrated in a single chip. A transition frequency of 660 MHz and a collector-to-emitter breakdown voltage of over 15 V have been obtained for the collector-isolated p-n-p transistor by adding only one extra mask to a conventional 2-μm BiCMOS process. The total number of masks is 20 with double-layer metallization. A unity gain frequency of 52 MHz and a DC gain of 85 dB have been obtained for a single-supply operational amplifier with a vertical p-n-p first stage. The propagation delay time for a CMOS two-NAND gate was 1.27 ns driving three loads and 3 mm of metal     

A 150-V multiple up-drain VDMOS, CMOS, and bipolar process in`direct-bonded' silicon on insulator on silicon

Silicon on insulator on silicon (SOIS) has been produced with silicon direct bonding (SDB). Within a silicon film of 15-μm thickness, islands with ubiquitous oxide isolation have been formed for the simultaneous integration of 150-V power VDMOS transistors, CMOS circuits in a channelless sea-of-gates array with 2-μm gates, and bipolar transistors. The up-drain VDMOS transistors with 2-Ω-mm ² specific on-resistance allow multiple isolated outputs, so high-voltage push-pull drivers can be fabricated in a single chip. The bipolar transistors are comparable to those of a 60-V standard process with vertical n-p-n and lateral p-n-p current gains of 80     

Self-aligned complementary bipolar transistors fabricated with a selective-oxidation mask

This paper deals with a self-aligned complementary transistor (vertical n-p-n and vertical p-n-p) structure that is ideal for high-speed and high-accuracy analog bipolar LSI circuits. The device structure consists of a 2-µm epitaxial layer, a non-LOCOS trench isolation buried with polysilicon, and complementary transistors, which are characterized by self-aligned active base and emitter. The key feature lies in the fabrication process, which forms an active base and emitter by ion implantations through a silicon nitride film by the use of an oxidation film that covers an extrinsic base as a mask [1]. The leakage current at the emitter-base junction can be minimized, because the ion-implantation-induced residual defects are confined in the emitter and the extrinsic base regions. The current gains of both transistors (n-p-n and p-n-p) remain constant down to a collector current of Ic= 10^-9A. The typical distribution of the base-emitter offsets (ΔVBE) of transistor pairs was 0.2 mV as expressed in the standard deviation = 3σ. The maximum values of fTfor n-p-n and p-n-p transistors are 6 and 1.5 GHz, respectively.     

High-performance, graded-base AlGaAs/InGaAs collector-upheterojunction bipolar transistors using a novel selective area regrowthprocess

Graded-base AlGaAs/InGaAs collector-up heterojunction bipolar transistors (C-up HBTs) were successfully fabricated using a novel selective area regrowth process to reduce the base resistance and their dc and microwave performances were evaluated. The base is compositionally graded to provide a quasi-built-in field which decreases the base transit time for high-frequency response and increases the base transport factor at low-temperature operation. A unity-gain cutoff frequency f_T=55 GHz and a maximum frequency of oscillation f _MAX=74 GHz for the C-up n-p-n HBT, and an f_T=48 GHz and an f_MAX= 39 GHz for the C-up p-n-p HBT were obtained for devices with a 5-μm×10-μm collector area. The nonself-aligned C-up HBT's reported here show great promise for future high-speed C-up complementary bipolar IC's     

High-gain lateral bipolar action in a MOSFET structure

A hybrid-mode device based on a standard submicrometer CMOS technology is presented. The device is essentially a MOSFET in which the gate and the well are internally connected to form the base of a lateral bipolar junction transistor (BJT). At low collector current levels, lateral bipolar action with a current gain higher than 1000 is achieved. No additional processing steps are needed to obtain the BJT when the MOSFET is properly designed. n-p-n BJTs with a 0.25-μm base width have been successfully fabricated in a p-well 0.25-μm bulk n-MOSFET process. The electrical characteristics of the n-MOSFET and the lateral n-p-n BJT at room and liquid nitrogen temperatures are reported     

A high-speed complementary silicon bipolar technology with 12-fJpower-delay product

A complementary silicon bipolar technology offering a substantial improvement in power-delay performance over conventional n-p-n-only bipolar technology is demonstrated. High-speed n-p-n and p-n-p double-polysilicon, self-aligned transistors were fabricated in a 20-mask-count integrated process using an experimental test site designed specifically for complementary bipolar applications. N-p-n and p-n-p transistors with 0.50-μm emitter widths have cutoff frequencies of 50 GHz and 13 GHz, respectively. Two novel complementary bipolar circuits-AC-coupled complementary push-pull ECL, and NTL with complementary emitter-follower-display a significant advantage in power dissipation as well as gate delay when compared to conventional n-p-n-only ECL circuits. Record power-delay products of 34 fJ (23.2 ps at 1.48 mW) and 12 fJ (19.0 ps at 0.65 mW) were achieved for these unloaded complementary circuits, respectively. These results demonstrate the feasibility and resultant performance leverage of high-speed complementary bipolar technologies     

An investigation of low-frequency noise in complementary SiGe HBTs

We present a comprehensive investigation of low-frequency noise behavior in complementary (n-p-n + p-n-p) SiGe heterojunction bipolar transistors (HBTs). The low-frequency noise of p-n-p devices is higher than that of n-p-n devices. Noise data from different geometry devices show that n-p-n transistors have an increased size dependence when compared with p-n-p transistors. The 1/f noise of p-n-p SiGe HBTs was found to have an exponential dependence on the (intentionally introduced) interfacial oxide (IFO) thickness at the polysilicon-to-monosilicon interface. Temperature measurements as well as ionizing radiation were used to probe the physics of 1/f noise in n-p-n and p-n-p SiGe HBTs. A weak temperature dependence (nearly a 1/T dependence) of 1/f noise is found in both n-p-n and p-n-p devices with cooling. In most cases, the magnitude of 1/f noise is proportional to I/sub B//sup 2/. The only exception in our study is for noise in the post-radiation n-p-n transistor biased at a low base current, which exhibits a near-linear dependence on I/sub B/. In addition, in proton radiation experiments, the 1/f noise of p-n-p devices was found to have higher radiation tolerance than that of n-p-n devices. A two-step tunneling model and a carrier random-walk model are both used to explain the observed behavior. The first model suggests that 1/f noise may be caused by a trapping-detrapping process occurring at traps located inside IFO, while the second one indicates that noise may be originating from the emitting-recapturing process occurring in states located at the monosilicon-IFO interface.     

A delay model and optimization method of a low-power BiCMOS logiccircuit

A new delay model and optimization method is proposed for a low-power BiCMOS driver. A transient overdrive, base directly-tied complementary BiCMOS logic circuit operates faster than conventional BiCMOS and CMOS circuits for supply voltage down to 1.5 V by using a speed-power-area optimization approach. An analytical delay expression is derived for the first time for a full-swing BiCMOS circuit with short-channel effects. The circuit is simulated with a HSPICE model using 0.8-μm BiCMOS technology with a 6-GHz n-p-n and a 1-GHz p-n-p transistor. The simulation results have verified the analytical results and demonstrated that the circuit can work up to 200 MHz operating frequency for a load capacitance of 1 pF at 1.5 V of supply voltage     

New Curvature-Compensation Technique for CMOS Bandgap Reference With Sub-1-V Operation

A new sub-1-V curvature-compensated CMOS bandgap reference, which utilizes the temperature-dependent currents generated from the parasitic n-p-n and p-n-p bipolar junction transistor devices in the CMOS process, is presented. The new proposed sub-1-V curvature-compensated CMOS bandgap reference has been successfully verified in a standard 0.25-$muhboxm$CMOS process. The experimental results have confirmed that, with the minimum supply voltage of 0.9 V, the output reference voltage at 536 mV has a temperature coefficient of 19.5$hboxppm/^circhboxC$from 0$^circhboxC$to 100$~^circhboxC$. With a 0.9-V supply voltage, the measured power noise rejection ratio is$-hbox25.5~hboxdB$at 10 kHz.     

A dielectrically isolated complementary bipolar technique for analog/Digital compatible LSI's

A dielectrically isolated complementary bipolar technique has been developed for use in analog LSI's or analog/digital compatible LSI's. This process makes it possible to form vertical double-diffused transistors in complementary islands and to obtain a high breakdown voltage of more than 350 V in spite of using shallow junctions with a depth of less than 2 µm. The gain bandwidth product fTis 450 and 200 MHz for n-p-n and p-n-p transitors, respectively. With this process, a subscriber line interface LSI that includes three functions (battery feed, supervision, and hybrid) has been successfully achieved within a 12.6 mm²die area.     

A compact low noise operational amplifier for a 1.2 μm digitalCMOS technology

A compact low noise operational amplifier using lateral p-n-p bipolar transistors in the input stage has been fabricated in a standard 1.2 μm digital n-well CMOS process. Like their n-p-n counterparts in p-well processes, these lateral p-n-p transistors exhibit low 1/f noise and good lateral β. The fabricated op amp has an area of only 0.211 mm² with E_n=3.2 nV/√(Hz), I_n=0.73 pA/√(Hz), E_n and I_n 1/f noise corner frequencies less than 100 Hz, a -3 dB bandwidth greater than 10 MHz with a closed loop gain of 20.8 dB, a minimum PSRR (DC) of 68 dB, a CMRR (DC) of 100 dB, a minimum output slew rate of 39 V/μs, and a quiescent current of 2.1 mA at supply voltages of ±2.5 V. The operational amplifier drives a 1 kΩ resistive load to 1 V peak-to-peak at 10 MHz and has been used as a versatile building block for mixed-signal IC designs     

CMOS-Compatible bipolar and I2L technology using three-level epitaxial layers for analog/Digital VLSI's

A high-performance bipolar/I²L/CMOS on-chip technology has been developed. To combine all devices, three-level epitaxial layers Were used. Both n-p-n and lateral p-n-p bipolar transistors, and p-channel MOSFET's were fabricated on the top level epitaxial layer. I²L and n-channel MOSFET's were fabricated on the middle and bottom levels, respectively. Using a thin epitaxial layer and simultaneously reducing the level of regions for n-channel MOSFET's and bi-polar isolation grooves, the process sequence was designed to be as simple as possible. Bipolar n-p-n transistors with a maximum cutoff frequency of 5 GHz, I²L circuits having 40-MHz maximum toggle frequency, and CMOS devices operating at a minimum propagation delay time of 300 ps/gate were developed compatibly. This technology has feasibility for application to multifunctional analog/digital VLSI's.     

1.0-µm n-well CMOS/bipolar technology

High-performance 1.0-µm n-well CMOS/bipolar on-chip technology was developed. For process simplicity, an n-well and a collector of bipolar transistors were formed simultaneously, and base and NMOS channel regions were also made simultaneously resulting in collector-isolated vertical n-p-n bipolar transistor fabrication without any additional process step to CMOS process. On the other hand, 1.0-µm CMOS with a new "hot carrier resistant" self-defined polysilicon sidewall spacer (SEPOS) LDD NMOS was developed. It can operate safely under supply voltage over 5 V without performance degradation of CMOS circuits. By evaluating ring oscillators and differential amplifiers constructed by both CMOS and bipolar transistors, it can be concluded that in a digital and in an analog combined system, CMOS has sufficiently high-speed performance for digital parts, while bipolar is superior for analog parts. In addition, bipolar transistors with an n⁺-buried layer were also fabricated to reduce collector resistance. Concerning the bipolar input/output buffers, the patterned n⁺-buried layer improves the drivability and high-frequency response. As a result, the applications of n-well CMOS/bipolar technology become clear. This technology was successfully applied to a high-speed 64-kbit CMOS static RAM, and improvement in access time was observed.     

Vertical p-n-p for Complementary Bipolar Technology

A process to fabricate high-performance vertical p-n-p devices has been developed. The use of a high-dose bolon-implanted poly-Si layer to form the emitter is essential to obtain shallow emitters with high emitter gradient. The devices exhibit very high current gain (>200) and a calculated cutoff frequency of 3.6 GHz. The process as developed is compatible with the n-p-n process and, thus, suitable for fabrication of complementary bipolar devices.     

Measurement of collector and emitter resistances in bipolartransistors

New DC methods to measure the collector resistance R_C and emitter resistance R_E are presented. These methods are based on monitoring the substrate current of the parasitic vertical p-n-p transistor linked with the n-p-n intrinsic transistor. The p-n-p transistor is operated with either the bottom substrate-collector or the top base-collector p-n junction forward-biased. This allows for a separation of the various components of R_C. R_E is obtained from the measured lateral portion of R_C and the collector-emitter saturation voltage. Examples of measurements on advanced self-aligned transistors with polysilicon contacts are shown. The results show a very strong dependence of R_C on the base-emitter and base-collector voltages of the n-p-n transistor. The bias dependence of R_C is due to the conductivity modulation of the epitaxial collector. From the measured emitter resistance R_E a value for the specific contact resistance for the polysilicon emitter contact of ρ_c≅50 Ω-μm² is obtained     

Vertical p-n-p for complementary bipolar technology

A process to fabricate high-performance vertical p-n-p devices has been developed. The use of a high-dose boron-implanted poly-Si layer to form the emitter is essential to obtain shallow emitters with high emitter gradient. The devices exhibit very high current gain (>200) and a calculated cutoff frequency of 3.6 GHz. The process as developed is compatible with the n-p-n process and, thus, suitable for fabrication of complementary bipolar devices.     

An Advanced Bipolar-MOS-I/sub 2/L Technology with a Thin Epitaxial Layer for Analog-Digital VLSI

A novel Bi-MOS technology, Advanced Bipolar CMOS (ABC), is proposed. Bipolar transistors (n-p-n, p-n-p, I/sup 2/L)and MOS transistors (both n- and p-channel) have been successfully fabricated on the same chip with no decrease in performance by using a 3-/spl mu/m design rule. Thin epitaxial layer (<= 2 /spl mu/m) is used in order to obtain small-size high-performance (3-GHz) bipolar devices. Device size is reduced by using a shallow junction and self-aligning technique. n-channel MOS transistors are formed in p-well regions designed to reach p-type substrate, and p-channel MOS transistors are formed in epitaxial layer with an n/sup +/ buried layer. This technology has the potential for monolithic multifunctional analog-digital VLSI.     

1.0-/spl mu/m n-Well CMOS/Bipolar Technology

High-performance 1.0-/spl mu/m n-well CMOS/bipolar on-chip technology was developed. For process simplicity, an n-well and a collector of bipolar transistors were formed simultaneously, and base and NMOS channel regions were also made simultaneously resulting in collector-isolated vertical n-p-n bipolar transistor fabrication without any additional process step to CMOS process. On the other hand, 1.0-/spl mu/m CMOS with a new "hot carrier resistant" seIf-defined Polysilicon sidewall spacer (SEPOS) LDD NMOS was developed. It can operate safely under supply voltage over 5 V without performance degradation of CMOS circuits. By evaluating ring oscillators and differential amplifiers constructed by both CMOS and bipolar transistors. it can be concluded that in a digital and in an analog combined system, CMOS has sufficiently high-speed performance for digital parts, while bipolar is superior for analog parts. In addition, bipolar transistors with an n/sup +/-buried layer were also fabricated to reduce collector resistance. Concerning the bipolar input/output buffers, the patterned n/sup +/-buried layer improves the drivability and high-frequency response. As a result, the applications of n-well CMOS/bipolar technology become clear. This technology was successfully applied to a high-speed 64-kbit CMOS static RAM, and improvement in access time was observed.     

High-gain lateral p-n-p bipolar action in a p-MOSFET structure

Lateral p-n-p bipolar junction transistors (BJTs) fabricated using a bulk 0.25 μm CMOS technology are presented. The devices are structurally the same as p-MOSFETs in which the gate and the n-well are internally connected to form the base. The p-n-p BJT has an adjustable current gain which can be higher than 1000 and its peak cutoff frequency is 3.7 GHz. Since the lateral p-n-p BJT is fully process compatible with submicrometer CMOS and/or BiCMOS technologies, extension to a BiCMOS and/or complementary BiCMOS process is readily achieved