光通信系统的定时抖动

本文主要研究高速数字光通信系统中的定时抖动的问题。由时变谱法概念,给出了在任意的提取方式(BPF或PLL等)及非线性电路(NLC)条件下,诸抖动功率谱的一般表达式。并在简单定时提取电路(STC)的具体情况下与其它推导方式的结论进行了分析比较。为分析比较各个抖动源在具体电路中的影响,合理使用具体的NLC形式提供了方便。     

数字光纤中继系统的抖动积累特性

本文探讨数字光纤中继系统中的抖动积累问题,具体分析谐振槽路(RC)作定时提取时的抖动积累特性,并给出适于工程估算抖动积累特性的简化公式。     

基于FPGA的数字复接系统的设计与实现

本文提出了基于FPGA技术实现数字复接系统的设计方案,并介绍了基群与二次群之间的复接与分接的系统总体设计。硬件电路调试证明,该方案是行之有效的。     

分频提取的定时抖动

本文提出了一种适合于140Mb/s数字复接设备中定时抖动分析的方法——分频提取抖动分析法。此方法较为全面地考虑了影响抖动的各种因素,在较为一般的情况下,推导出了抖动传递函数和抖动功率谱密度的表达式。     

基于CPLD的数字语音通信中复分接的设计

介绍了在数字语音通信中,利用在系统可编程技术和复杂可编程逻辑器件CPLD,实现数字语音的复接和分接;对干其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。     

全数字化PDH复接系统的设计

为了便于ＰＤＨ复接系统的集成和设备的小型化，以及改善系统的性能，本文介绍了复接系统的几个主要部分（定时提取，码速调整，收端支路时钟恢复等）的数字化实现方法，还介绍了采用这些数字化方法的多功能复接专用集成电路－ＭＸＺＷ６８２３１。     

用声表面波滤波器实现高速光纤传输系统的定时恢复

在高速光纤数字传输系统中,尤其在长中继链路系统中,定时恢复的质量直接影响到传输系统的性能。本文分析了100Mbit/s以上光纤数字传输系统用声表面波滤波器(SAW—F)定时提取电路。首先给出SAW—F的基本原理;然后讨论了SAW—F定时提取实现方案并分析了其抖动积累特性,得出SAW—F定时提取电路的设计依据;最后,根据理论分析的结果,我们设计了一个可用于155.520Mbit/s光纤数字传输系统的SAW—F定时提取电路。分析和实验表明,SAW-F适合用作100Mbit/s以上数字传输系统的定时提取。     

一种定时脉冲低抖动传输方案设计

针对时统系统中脉冲传输问题,提出了一种定时脉冲低抖动传输方案。介绍了定时脉冲低抖动传输系统的方案设计,对数字内插、锁相环、调制解调方案和相位模糊检测等关键技术进行了阐述,最后给出了定时脉冲低抖动传输系统设计实现方案及性能测试结果分析,利用示波器观察时统系统中脉冲传输抖动控制在4 ns以内,通过实际工程证明了其有效性。     

基于FPGA的多路数字信号复接系统设计与实现

数字复分接技术是数字通信网中的一项重要技术,能将若干路低速信号合并为一路高速信号,以提高带宽利用率和数据传输效率。文中在介绍数字复接系统的基础上,采用VHDL对数字复分接系统进行建模设计和实现。并利用乒乓操作和先进先出存储器(FIFO)对复接器进行设计,利用帧同步器对数据进行分接。以QuartusII8.0为仿真软件,对设计进行仿真验证,仿真结果表明,设计实现了复接系统,便于修改电路结构,增强了设计的灵活性,且节约了系统资源。     

复分接中数字化定时处理的参数化验证法

在复分接系统中，如同步数字系列，定时处理占有重要地位。数字化定时处理技术应用于ＡＳＩＣ设计时，传统方法需要的仿真代价太大。作者 定时验证的特殊性，提出了定时处理电路验证的概念。同时利用参数化方法对定时处理进行验证，大大缩短了仿真时间。     

Coding, decoding, and recovery of clock synchronization in digital multiplexing system

High-speed broadband digital communication networks rely on digital multiplexing technology where clock synchronization, including processing, transmission, and recovery of the clock, is the critical technique. This paper interprets the process of clock synchronization in multiplexing systems as quantizing and coding the information of clock synchronization, interprets clock justification as timing sigma-delta modulation (T/spl Delta/-/spl Sigma/M), and interprets the jitter of justification as quantization error. As a result, decreasing the quantization error is equivalent to decreasing the jitter of justification. Using this theory, the paper studies the existing jitter-reducing techniques in transmitters and receivers, presents some techniques that can decrease the quantization error (justification jitter) in digital multiplexing systems, and presents a new method of clock recovery.     

Sampling Jitter Effect on a Reconfigurable Digital IF Transceiver to WiMAX and HSDPA

This paper outlines the time jitter effect of a sampling clock on a software‐defined radio technology‐based digital intermediate frequency (IF) transceiver for a mobile communication base station. The implemented digital IF transceiver is reconfigurable to high‐speed data packet access (HSDPA) and three bandwidth profiles: 1.75 MHz, 3.5 MHz, and 7 MHz, each incorporating the IEEE 802.16d worldwide interoperability for microwave access (WiMAX) standard. This paper examines the relationship between the signal‐to‐noise ratio (SNR) characteristics of a digital IF transceiver with an under‐sampling scheme and the sampling jitter effect on a multichannel orthogonal frequency‐division multiplexing (OFDM) signal. The simulation and experimental results show that the SNR of the OFDM system with narrower band profiles is more susceptible to sampling clock jitter than systems with relatively wider band profiles. Further, for systems with a comparable bandwidth, HSDPA outperforms WiMAX, for example, a 5 dB error vector magnitude improvement at 15 picoseconds time jitter for a bandwidth of WiMAX 3.5 MHz profile.     

带通采样时钟沿抖动对解调性能的影响分析

在中频直接采样系统中,采样时钟的抖动问题是带通采样的一个关键问题。研究了带通采样时钟抖动对系统的影响,介绍了带通采样时钟沿抖动的产生极其直观影响,分析带通采样时钟沿抖动对解调性能的影响,并仿真验证了理论分析的正确性。结合典型的调制编码方式对带通采样时钟沿抖动范围提出了要求,为带通采样的设计及实现提供了依据。     

数字电视中的编解码同步分析

研究了数字电视传输系统中的编解码同步机制,分析了节目参考时钟PCR在系统同步中的重要作用及产生PCR抖动的原因,探讨了几种适用于不同场合的PCR抖动校正方法.     

Short-term frequency stability of clock generators for multigigahertz rapid-single-flux quantum digital circuits

Superconducting digital systems based on Josephson junctions have generally used a synchronous timing strategy. A master clock signal is used to delimit a data window during which the system changes state and data is transferred from one block to the next. The temporal stability of the clock signal has a profound effect on the performance of rapid single flux quantum (RSFQ) digital systems. In particular, short-term clock fluctuations, or clock jitter, can degrade system performance due to the hazard of timing constraint violations. The successful development of large-scale RSFQ digital systems will require highly stable multigigahertz on-chip clock sources. To meet this need, methods for characterizing and measuring the short-term stability of such sources are required. We identify the relevant figure of merit to characterize and compare various clocks: the cycle-to-cycle standard deviation of the clock periods. We present experimental techniques for the measurement of this figure of merit and apply them to the measurement of jitter in a clock generator used often in RSFQ systems, the ring oscillator. High-frequency phase noise measurements found the jitter of a 9.6-GHz clock to be in the range from 0.6% to 0.36% of the clock period. The measured values of clock jitter fell within the 95% confidence interval of our stochastic circuit simulations. This was sufficient evidence to conclude that thermal noise from the resistors in the circuit may be the dominant source of jitter in the ring oscillator.     

孔径抖动对中频采样系统信噪比影响的研究

孔径抖动对中频(或射频)带通采样系统信噪比的影响非常严重.理论上,尽管相同带宽的中频信号和基带信号可以用相同的频率进行采样,但中频采样受孔径抖动等因素的影响更大,其采样技术要求也更高.如果在中频采样系统中解决不好孔径抖动问题,很可能根本采集不到正确的信号.本文通过分析孔径抖动产生的原因,孔径抖动与ADC (模数转换器)的信噪比以及与被采样信号上限频率之间的关系,找出了由孔径抖动决定的被采样信号的上限频率与ADC模拟带宽之间存在差距的原因,并发现了过采样率与处理增益及孔径抖动之间的关系.最后,介绍了几项减小孔径抖动的具体措施.     

Clock jitter generator with picoseconds resolution

The clock is one of the most critical signals in any synchronous system. As CMOS technology has scaled, supply voltages have dropped chip power consumption has increased and the effects of jitter due to clock frequency increase have become critical and jitter budget has become tighter. This article describes design and development of low-cost mixed-signal programmable jitter generator with high resolution. The digital technique is used for coarse-grain and an analogue technique for fine-grain clock phase shifting. Its structure allows injection of various random and deterministic jitter components in a controllable and programmable fashion. Each jitter component can be switched on or off. The jitter generator can be used in jitter tolerance test and jitter transfer function measurement of high-speed synchronous digital circuits. At operating system clock frequency of 220?MHz, a jitter with 4?ps resolution can be injected.     

低抖动时钟产生电路设计

相位噪声和抖动是考量周期信号性能最常用的2个指标。介绍了相位噪声和抖动的概念,详细分析了两者之间的联系,设计了一个低抖动的标频时钟模块,测试结果表明均方根（RMS）周期抖动≤250 fs。     

FPGA在直接数字波形合成宽带信号源中的应用

介绍了现场可编程门阵列（FPGA）作为控制核心在直接数字波形合成宽带信号源中的应用,分析了FPGA在时钟管理、数据传输及电平转换等方面的功能。该方法具有高速、高集成度和可编程性,简化了系统结构,提高了系统性能。     

Performance aspects of reference clock distribution for evolvingdigital networks

Recent reference clock distribution technologies are reviewed. Performance concepts and specification methodologies for synchronization system designs are then summarized. The focus is on the common master-slave synchronization designs, generally consisting of three subsystems: the primary clock supply, the slave clock supply, and the clock distribution system overlaid on the digital network. Network synchronization performance is specified with relative clock frequency stability and accuracy of the corresponding reference clock. An overview is also given of clock and jitter and wander specification methodologies discussed in CCITT