Analysis, Design, and $X$-Band Implementation of a Self-Biased Active Feedback $G_{m}$ -Boosted Common-Gate CMOS LNA

This paper explores the use of active feedback to boost the transconductance of a common-gate (CG) low-noise amplifier and achieve simultaneous low noise and input power match. Unlike transformer coupled topologies, the CG input stage is dc-coupled to a self-biased common-source feedback amplifier (for $g_{m}$ boosting), thus eliminating the need of external bias circuitry. Noise and intermodulation analysis with and without $g_{m}$ boosting are extensively studied yielding closed-form expressions of the noise figure (NF) and third-order input-referred intercept point (IIP3) that are useful for circuit design and optimization. A 9.6-GHz differential prototype implemented in a 0.18-$mu$ m technology using only NMOS transistors, achieves a minimum NF of 4 dB, an IIP3 of ${-}$ 11.3 dBm, a return loss of ${-}$ 17 dB, and a transducer gain of 18 dB while dissipating 10 m (excluding buffer circuit) from a 1.8-V supply voltage. The active chip area is 0.11 $mu$m $^{2}$.      

$L$ -Band Polarization-Independent Reflective SOA for WDM-PON Applications

An $L$-band polarization-independent reflective semiconductor optical amplifier (RSOA) is demonstrated for the first time. Optical gain of greater than 21 dB and gain flatness better than 4 dB is achieved over the $L$-band. The polarization-dependent gain estimated using a polarization resolved spectrum is less than 1 dB over the $L$-band. The measured output saturation power is $-$1.0 dBm and the noise figure (NF) is 10 dB for the packaged device. The 3-dB frequency bandwidth for the device is 1.3 GHz making it suitable for 1.25-Gb/s modulated wavelength-division-multiplexed passive optical network networks. Further, the saturation power and the NF of the RSOA were compared with an SOA of identical length.      

$C$ -Band Optical 90$^{circ}$ -Hybrids Based on Silicon-on-Insulator 4 $times$ 4 Waveguide Couplers

We demonstrate 4times4 multimode interference couplers in a silicon-on-insulator rib waveguide technology that enable compact integrated fully passive optical 90deg-hybrid devices with operation across the C-band.     

22.7-dB Gain $-$19.7-dBm $ICP_{1{rm dB}}$ UWB CMOS LNA

A fully differential CMOS ultrawideband low-noise amplifier (LNA) is presented. The LNA has been realized in a standard 90-nm CMOS technology and consists of a common-gate stage and two subsequent common-source stages. The common-gate input stage realizes a wideband input impedance matching to the source impedance of the receiver (i.e., the antenna), whereas the two subsequent common-source stages provide a wideband gain by exploiting RLC tanks. The measurements have exhibited a transducer gain of 22.7 dB at 5.2 GHz, a 4.9-GHz-wide B _3dB, an input reflection coefficient lower than -10.5 dB, and an input-referred 1-dB compression point of -19.7 dBm, which are in excellent agreement with the postlayout simulation results, confirming the approach validity and the design robustness.     

A $Q$ -Band Four-Element Phased-Array Front-End Receiver With Integrated Wilkinson Power Combiners in 0.18-$mu{{hbox{m}}}$ SiGe BiCMOS Technology

A four-element phased-array front-end receiver based on 4-bit RF phase shifters is demonstrated in a standard 0.18- $mu{{hbox{m}}}$ SiGe BiCMOS technology for $Q$-band (30–50 GHz) satellite communications and radar applications. The phased-array receiver uses a corporate-feed approach with on-chip Wilkinson power combiners, and shows a power gain of 10.4 dB with an ${rm IIP}_{3}$ of $-$13.8 dBm per element at 38.5 GHz and a 3-dB gain bandwidth of 32.8–44 GHz. The rms gain and phase errors are $leq$1.2 dB and $leq {hbox{8.7}}^{circ}$ for all 4-bit phase states at 30–50 GHz. The beamformer also results in $leq$ 0.4 dB of rms gain mismatch and $leq {hbox{2}}^{circ}$ of rms phase mismatch between the four channels. The channel-to-channel isolation is better than $-$35 dB at 30–50 GHz. The chip consumes 118 mA from a 5-V supply voltage and overall chip size is ${hbox{1.4}}times {hbox{1.7}} {{hbox{mm}}}^{2}$ including all pads and CMOS control electronics.      

Design of $X$ -Band RF CMOS Transceiver for FMCW Monopulse Radar

In this paper, an X-band CMOS single chip integrating 16 building blocks is developed for frequency modulation continuous wave radar application. The quadrature and monopulse transceiver consists of a voltage-controlled oscillator, amplifiers, Wilkinson power dividers, 90deg hybrid low-noise amplifiers, rat-race hybrid, a single-pole double-throw switch, an active bandpass filter (BPF), and mixers. The transceiver is fabricated in a standard mixed-signal/RF bulk 0.18-mum CMOS technology with a chip area of 2.6 mm 3.3 mm, including contact pads. The transceiver is implemented by meandered complementary-conducting-strip transmission lines demonstrating their capability of miniaturizing circuits such as 90deg hybrid and rat-race hybrid with 95% and 98% size reduction compared to the prototype designs, respectively. The active BPF consumes 4.5 mW achieving 0-dB insertion loss at the passband. The total power consumption of the transceiver is 0.35 W. Output power of the transmitter is 1 dBm with a 35-dB second harmonic suppression. Moreover, the on-chip isolations between T/R in this compacted transceiver are more than 60 dB. The measured receiver gain and NF are -4.5 and 11.5 dB, respectively. Finally, the obtained in-phase and quadrature signals demonstrate 0.6-dB amplitude and 7deg phase imbalance.     

A 1.2 V 114 mW Dual-Band Direct-Conversion DVB-H Tuner in 0.13 $mu$ m CMOS

A fully integrated direct-conversion tuner is implemented in 0.13 $muhbox{m}$ CMOS technology. A broadband noise-canceling balun LNA with the proposed dual cross-coupling technique helps achieve an overall receiver noise figure from 3.7 to 4.3 dB while consuming only 3.6 mW. The proposed current-mode switching scheme improves the achievable SNIR with a gain step of 15 dB, providing IIP3 improvement of 18 dB and NF degradation of only 6 dB. Moreover, design trade-offs are carefully considered in designing the baseband circuit, which provides wide gain tuning and bandwidth accuracy with a DC offset residual less than 6 mV. The measured maximum SNR values are better than 30 dB over wide input power levels, ensuring robust reception in a mobile environment. All circuit blocks are operated at 1.2 V. As a result, the tuner consumes power as low as 114 mW in the continuous mode. This compact tuner supports both UHF and L- bands, and occupies only 7.2 $ {hbox{mm}}^{2}$ die area.      

A 2.4-GHz Resistive Feedback LNA in 0.13-$mu$m CMOS

A $g_{m}$-boosted resistive feedback low-noise amplifier (LNA) using a series inductor matching network and its application to a 2.4 GHz LNA is presented. While keeping the advantage of easy and reliable input matching of a resistive feedback topology, it takes an extra advantage of $g_{m}$ -boosting as in inductively degenerated topology. The gain of the LNA increases by the $Q$ -factor of the series RLC input network, and its noise figure (NF) is reduced by a similar factor. By exploiting the $g_{m}$-boosting property, the proposed fully integrated LNA achieves a noise figure of 2.0 dB, S21 of 24 dB, and IIP3 of ${- 11}~ hbox{dBm}$ while consuming 2.6 mW from a 1.2 V supply, and occupies 0.6 ${hbox {mm}}^{2}$ in 0.13-$mu{hbox {m}}$ CMOS, which provides the best figure of merit. This paper also includes an LNA of the same topology with an external input matching network which has an NF of 1.2 dB.      

A K-Band High-Gain Down-Conversion Mixer in 0.18 $mu$m CMOS Technology

A high gain CMOS down conversion mixer with a gain enhancement technique is presented. This technique includes negative resistance generation, parasitic capacitance cancellation and current-injection. These are implemented with an additional circuitry. This mixer has a conversion gain of 9.12 dB, input 1 dB compression point of -11 dBm at 24 GHz, while consuming 16.2 mW from 1.8 V supply. Between 22 and 26 GHz, the LO-to-RF and RF-to-LO isolations are better than 35 dB and 26 dB, respectively.     

A 66 $mu$ W 86 ppm$/^{circ}$ C Fully-Integrated 6 MHz Wienbridge Oscillator With a 172 dB Phase Noise FOM

This paper presents the design of a new Wienbridge topology. Its phase noise performance, low temperature dependency and low power consumption make it suitable for use in wireless sensor nodes and time-based sensor readout circuitry. The noise as well as temperature behavior of the oscillator is explained using extensive calculations. Measurements on 7 samples of the same batch show a temperature stability of 86 $hbox{ppm}/^{circ}hbox{C}$ and a measured spread of 0.9% at an oscillation frequency of 6 MHz. The circuit consumes 66 $muhbox{W}$ and is realized in a 65 nm technology measuring 150 $muhbox{m}$ by 200 $muhbox{m}$. The measured phase noise figure of merit is 172 dB at a frequency offset of 100 kHz.      

A 3.1 GHz–8.0 GHz Single-Chip Transceiver for MB-OFDM UWB in 0.18-$mu$ m CMOS Process

This paper presents the design and integration of a fully-integrated dual-conversion zero-IF2 CMOS transceiver for 9-band MB-OFDM UWB systems from 3.1 GHz to 8.0 GHz. The transceiver integrates all building blocks including a variable-gain wideband LNA, a single combined mixer for both RF down-conversion in RX and up-conversion in TX, a fast-settling frequency synthesizer, and IQ ADCs and DACs. Fabricated in a standard 0.18- mum CMOS process, the receiver measures maximum S11 of - 13 dB, maximum NF of 8.25 dB, in-band IIP3 of better than -13.7 dBm, and variable gain from 25.3 to 84.0 dB. IQ path gain and phase mismatches of the receiver chain are measured to be 0.8 dB and 4 ^deg, respectively. The transmitter achieves a minimum output P-1 dB of -8.2 dBm, sideband rejection of better than -42.2 dBc, and LO leakage of smaller than - 46.5 dBc.     

AlGaN/GaN HEMT High Power Densities on $hbox{SiC/} hbox{SiO}_{2}$/poly-SiC Substrates

In this letter, successful operation at 10 GHz of T-gate HEMTs on epitaxial structures grown by metal–organic chemical vapor deposition (MOCVD) or MBE on composite substrates is demonstrated. The used device fabrication process is very similar to the process used on monocrystalline SiC substrate. High power density was measured on both epimaterials at 10 GHz. The best value is an output power density of 5.06 W/mm associated to a power-added efficiency (PAE) of 34.7% and a linear gain of 11.8 dB at $V_{rm DS} = hbox{30} hbox{V}$ for the components based on MOCVD-grown material. The output power density is 3.58 W/mm with a maximum PAE of 25% and a linear gain around 15 dB at $V_{rm DS} = hbox{40} hbox{V}$ for the MBE-grown material.      

A Millimeter-Wave (40–45 GHz) 16-Element Phased-Array Transmitter in 0.18-$mu$ m SiGe BiCMOS Technology

This paper demonstrates a 16-element phased-array transmitter in a standard 0.18-mum SiGe BiCMOS technology for Q-band satellite applications. The transmitter array is based on the all-RF architecture with 4-bit RF phase shifters and a corporate-feed network. A 1:2 active divider and two 1:8 passive tee-junction dividers constitute the corporate-feed network, and three-dimensional shielded transmission-lines are used for the passive divider to minimize area. All signals are processed differentially inside the chip except for the input and output interfaces. The phased-array transmitter results in a 12.5 dB of average power gain per channel at 42.5 GHz with a 3-dB gain bandwidth of 39.9-45.6 GHz. The RMS gain variation is < 1.3 dB and the RMS phase variation is < for all 4-bit phase states at 35-50 GHz. The measured input and output return losses are < -10 dB at 36.6-50 GHz, and <-10 dB at 37.6-50 GHz, respectively. The measured peak-to-peak group delay variation is plusmn 20 ps at 40-45 GHz. The output P_-1dB is -5plusmn1.5 dBm and the maximum saturated output power is - 2.5plusmn1.5 dBm per channel at 42.5 GHz. The transmitter shows <1.8 dB of RMS gain mismatch and < 7deg of RMS phase mismatch between the 16 different channels over all phase states. A - 30 dB worst-case port-to-port coupling is measured between adjacent channels at 30-50 GHz, and the measured RMS gain and phase disturbances due to the inter-channel coupling are < 0.15 dB and < 1deg, respectively, at 35-50 GHz. All measurements are obtained without any on-chip calibration. The chip consumes 720 mA from a 5 V supply voltage and the chip size is 2.6times3.2 mm².     

Leakage Minimization of SRAM Cells in a Dual-$V_t$ and Dual-$T_{rm ox}$ Technology

Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicrometer regime. As a result, reducing the subthreshold and tunneling gate leakage currents has become one of the most important criteria in the design of VLSI circuits. This paper presents a method based on dual- V t and dual- T _ox assignment to reduce the total leakage power dissipation of static random access memories (SRAMs) while maintaining their performance. The proposed method is based on the observation that read and write delays of a memory cell in an SRAM block depend on the physical distance of the cell from the sense amplifier and the decoder. Thus, the idea is to deploy different configurations of six-transistor SRAM cells corresponding to different threshold voltage and oxide thickness assignments for the transistors. Unlike other techniques for low-leakage SRAM design, the proposed technique incurs neither area nor delay overhead. In addition, it results in a minor change in the SRAM design flow. The leakage saving achieved by using this technique is a function of the values of the high threshold voltage and the oxide thickness, as well as the number of rows and columns in the cell array. Simulation results with a 65-nm process demonstrate that this technique can reduce the total leakage power dissipation of a 64 times 512 SRAM array by 33% and that of a 32 times 512 SRAM array by 40%.     

A 60-GHz Phased Array Receiver Front-End in 0.13-$mu {hbox{m}}$ CMOS Technology

This paper presents a fully integrated dual-antenna phased-array RF front-end receiver architecture for 60-GHz broadband wireless applications. It contains two differential receiver chains, each receiver path consists of an on-chip balun, ag_m-boosted current-reuse low-noise amplifier (LNA), a sub-harmonic dual-gate down-conversion mixer, an IF mixer, and a baseband gain stage. An active all-pass filter is employed to adjust the phase shift of each LO signal. Associated with the proposed dual conversion topology, the phase shift of the LO signal can be scaled to one-third. Differential circuitry is adopted to achieve good common-mode rejection. The g_m-boosted current-reuse differential LNA mitigates the noise, gain, robustness, stability, and integration challenges. The sub-harmonic dual-gate down-conversion mixer prevents the third harmonic issue in LO as well. Realized in a 0.13-mum 1P8M RF CMOS technology, the chip occupies an active area of 1.1 times 1.2 mm². The measured conversion gain and input P1 dB of the single receiver path are 30 dB and -27 dBm , respectively. The measured noise figure at 100 MHz baseband output is around 10 dB. The measured phased array in the receiver achieves a total gain of 34.5 dB and theoretically improves the receiver SNR by 4.5 dB. The proposed 60 GHz receiver dissipates 44 mW from a 1.2 V supply voltage. The whole two-channel receiver, including the vector modulator circuits for built-in testing, consumes 93 mW from a 1.2 V supply voltage.     

A 20 to 24 GHz $+$16.8 dBm Fully Integrated Power Amplifier Using 0.18 $mu{rm m}$ CMOS Process

A 20-24 GHz, fully integrated power amplifier (PA) with on-chip input and output matching is realized in 0.18 mum standard CMOS process. By cascading two cascode stages, the PA achieves 15 dB small signal gain, 10.7% power added efficiency, 16.8 dBm output saturation power and high power density per chip area of 0.137 W/mm², which is believed to be the highest power density to our knowledge. The whole chip area with pads is 0.35 mm², which is the smallest one compared to all reported paper.     

A $K$ -Band CMOS Distributed Doubler With Current-Reuse Technique

A $K$-band distributed frequency doubler is developed in 0.18 $mu{rm m}$ CMOS technology. This doubler combines the distributed topology for broadband characteristics and current-reuse technique to improve the conversion gain. The high-pass drain line and high-pass inter-stage matching network are used to obtain a good fundamental rejection. A measured conversion gain of better than ${- 12.3}~{rm dB}$ is obtained, and the fundamental rejection is better than 30 dB for the output frequency between 18 and 26 GHz. The dc power consumption is 10.5 mW with a chip size of 0.55$,times,$0.5 ${rm mm}^{2}$.      

Resilient Self-V$_{rm DD}$-Tuning Scheme With Speed-Margining for Low-Power SRAM

Lowering the supply voltage is an effective way to significantly reduce the power consumption of a static random access memory (SRAM). However, the minimum supply voltage (V_minf) required to support a given operating frequency in an SRAM macro is often elusive from one chip to another due to process variations. Moreover, temperature could vary when an SRAM macro is in operation, and thus exacerbating the problem since temperature variation could affect the V_minf . In this paper, we propose an on-chip self-V_DD-tuning scheme that automatically adjusts each manufactured SRAM macro to a minimal voltage near its V_minf. Our scheme can provide a user-specified speed margin (e.g., 10% of the target frequency), and thereby creating a guard band for assuring robust operations over a wide range of temperatures. Simulation results show that, with the proposed speed margining technique, a 64 Kb SRAM macro can tolerate temperature up to 125degC. Measurement results from a test chip in a 0.18-mum CMOS process also demonstrate that we can achieve 40% power savings for an 8 Kb SRAM macro operating at 150 MHz by means of this resilient self-V_DD-tuning.     

A 51 to 65 GHz Low-Power Bulk-Driven Mixer Using 0.13 $mu$m CMOS Technology

A low-voltage and low-power down-conversion bulk-driven mixer using standard 0.13 $mu$ m CMOS technology is presented in this letter. To work on a low supply voltage and low power consumption applications while maintaining reasonable performance, the bulk-driven technique is selected in this V-band mixer design. The mixer has a conversion gain of $0 pm 1.5$ dB from 51 to 65 GHz with low supply voltage of 1 V and low power consumption of 3 mW. To our knowledge, the MMIC is the highest frequency CMOS bulk-driven mixer to date with good conversion gain and low power consumption among the recently published active mixers around 60 GHz.      

2$,times,$ 2 InP Optical Switching Matrix Based on Carrier-Induced Effects for 1.55-$mu$m Applications

This letter demonstrates a 2times2 low optical crosstalk and low power consumption switching matrix device based on carrier-induced effects on an InP substrate. The matrix device comprises two digital optical switches (DOSs) with a wide multimode Y-junction associated with a sinusoidal passive integrated optical circuit with an optimized X-crossing. The passive structure was designed using a two-dimensional beam propagation method (BPM) and the entire InP-InGaAsP-InP DOS was designed using a semivectorial three-dimensional BPM. The fabricated 2times2 InP switching matrix heterostructure with lambdag=1.3 mum exhibits optical crosstalk as low as -30.5 dB for drive current of 52 mA at 1.55-mum wavelength. Maximum crosstalk change of 4 dB is measured under optical polarization variation.