Bandpass Sigma–Delta Modulator Employing SAW Resonator as Loop Filter

Continuous-time bandpass (BP) sigma-delta modulators (SigmaDeltaMs) employing surface acoustic wave (SAW) resonators as loop filters are presented. Compared with the loop filters realized with G_m-C and LC resonators, the SAW resonator has the advantage of high-Q factor, wide resonant frequency range and accurate resonant frequency without the need for automatic tuning. With the proposed anti-resonance cancellation and loop filter phase compensation techniques, a second- and a fourth-order BP SigmaDeltaMs are demonstrated in a 0.35-mum CMOS technology. Both modulators are tested with 47.3-MHz off-chip SAW resonators. The second-order modulator attains a dynamic range of 57 dB and peak signal-to-noise distortion ratio (SNDR) of 54 dB and the fourth-order one achieves a dynamic range of 69 dB and peak SNDR of 66 dB, both in a 200-kHz signal bandwidth. The fourth-order modulator is also measured in a 3.84-MHz signal bandwidth and achieves a dynamic range of 52.5 dB and peak SNDR of 50 dB, an effective 8-bit resolution     

A 20-mW 640-MHz CMOS Continuous-Time Σ∆ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB

A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is implemented in 130-nm CMOS. The circuit is targeted for applications that demand high bandwidth, high resolution, and low power, such as wireless and wireline communications, medical imaging, video, and instrumentation. The third-order continuous-time SigmaDelta modulator comprises a third-order RC operational-amplifier-based loop filter and 4-bit internal quantizer operating at 640 MHz. A 400-fs rms jitter LC PLL with 450-kHz bandwidth is integrated, generating the low-jitter clock for the jitter-sensitive continuous-time SigmaDelta ADC from a single-ended input clock between 13.5 and 40 MHz. To reduce clock jitter sensitivity, nonreturn-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the degradation of modulator stability due to excess loop delay is avoided with a new architecture. The SigmaDelta ADC achieves 76-dB SNR, -78-dB THD, and a 74-dB SNDR or 12 ENOB over a 20-MHz signal band at an OSR of 16. The power consumption of the CT SigmaDelta modulator itself is 20 mW and in total the ADC dissipates 58 mW from the 1.2-V supply     

A cascaded continuous-time /spl Sigma//spl Delta/ Modulator with 67-dB dynamic range in 10-MHz bandwidth

This paper presents the design of a 2-2 cascaded continuous-time sigma-delta modulator. The cascaded modulator comprises two stages with second-order continuous-time resonator loopfilters, 4-bit quantizers, and feedback digital-to-analog converters. The digital noise cancellation filter design is determined using continuous-time to discrete-time transformation of the sigma-delta loopfilter transfer functions. The required matching between the analog and digital filter coefficients is achieved by means of simple digital calibration of the noise cancellation filter. Measurement results of a 0.18-/spl mu/m CMOS prototype chip demonstrate 67-dB dynamic range in a 10-MHz bandwidth at 8 times oversampling for a single continuous-time cascaded modulator. Two cascaded modulators in quadrature configuration provide 20-MHz aggregate bandwidth. Measured anti-alias suppression is over 50 dB for input signals in the band from 150 to 170 MHz around the sampling frequency of 160 MHz.     

A multibit sigma-delta ADC for multimode receivers

A 2.7-V sigma-delta modulator with a 6-bit quantizer is fabricated in a 0.18-/spl mu/m CMOS process. The modulator makes use of noise-shaped dynamic element matching (DEM) and quantizer offset chopping to attain high linearity over a wide bandwidth. The DEM algorithm is implemented in such a way as to minimize additional delay within the feedback loop of the modulator, thereby enabling the use of the highest resolution quantizer yet reported in a multibit sigma-delta analog-to-digital converter of this speed. The part achieves 95-dB peak spurious-free dynamic range and 77-dB signal-to-noise ratio over a 625-kHz bandwidth, and consumes 30 mW at a sampling frequency of 23 MHz. The part achieves 70-dB signal-to-noise ratio over a 1.92-MHz bandwidth and dissipates 50 mW when clocked at 46 MHz.     

A 64-MHz clock-rate /spl Sigma//spl Delta/ ADC with 88-dB SNDR and -105-dB IM3 distortion at a 1.5-MHz signal frequency

A 64-MHz clock rate sigma-delta (/spl Sigma//spl Delta/) analog-to-digital converter (ADC) with -105-dB intermodulation distortion (IMD) at a 1.5-MHz signal frequency is reported. A linear replica bridge sampling network enables the ADC to achieve high linearity for high signal frequencies. Operating at an oversampling ratio of 29, a 2-1-1 cascade with a 2-b quantizer in the last stage reduces the quantization noise level well below that of the thermal noise. The measured signal-to-noise and distortion ratio (SNDR) in 1.1-MHz bandwidth is 88 dB, and the spurious-free-dynamic-range (SFDR) is 106 dB. The modulator and reference buffers occupy a 2.6-mm/sup 2/ die area and have been implemented with thick oxide devices, with minimum channel length of 0.35 /spl mu/m, in a dual-gate 0.18-/spl mu/m 1.8-V single-poly five-metal (SP5M) digital CMOS process. The power consumed by the ADC is 230 mW, including the decimation filters.     

A 1.44-mW, 1-MHz bandwidth continuous-time Σ∆ modulator with 10-bit ENOB in 130-nm CMOS

A low-power, low-pass continuous-time sigma-delta A/D modulator with 1-MHz bandwidth is implemented in a 130-nm CMOS process. The circuit is targeted for an IEEE 802.15.4 direct conversion receiver operating in the 2.4-GHz band. It has a third-order feedforward single-loop filter and a 1-bit quantizer to minimize power consumption. Non-return-to-zero DAC pulse shaping is used to reduce sensitivity to clock jitter. Clocked at 64 MHz, the prototype chip achieves 62-dB peak SNR, −70-dB peak THD, 63-dB dynamic range with an oversampling ratio of 32. The built-in anti-alias filter provides alias attenuation greater than 57 dB, which improves coexistence of the receiver with other devices that operate in the 2.4-GHz band. The circuit dissipates 1.44 mW from the 1.2-V supply and the active die area is 0.1 mm².     

一款使用低功耗多级运放实现的12位，20兆带宽，18毫瓦的连续时间型过采样调制器

本文在130纳米CMOS工艺下实现了一种具有20兆赫兹带宽,四阶连续时间型过采样调制器。调制器由有源积分环路滤波器、4位内部量化器和3个电流舵型反馈数模转换器构成。本文提出了一种三级运算放大器,它可以在获得高带内增益和高带宽的同时消耗较小的功耗。为了减小时钟抖动对连续时间型过采样调制器的影响,内部反馈数模转化器采用了不自归零的反馈波形。同时采用特殊的版图技术保证数模转换器的线性度,同时避免使用动态器件匹配技术引入的额外环路延时。芯片工作在1. 2 V 电源电压和480 M Hz 时钟频率, 在20 MHz 的信号带宽内, 调制器的动态范围为66 dB, 峰值SNR为64.6 dB, 功耗为18 mW。     

An agile ISM band frequency synthesizer with built-in GMSK datamodulation

In this paper, a high-resolution fractional-N RF frequency synthesizer is presented which is controlled by a fourth-order digital sigma-delta modulator. The high resolution allows the synthesizer to be digitally modulated directly at RF. A simplified digital filter which makes use of sigma-delta quantized tap coefficients is included which provides built-in GMSK pulse shaping for data transmission. Quantization of the tap coefficients to single-bit values not only simplifies the filter architecture, but the fourth-order digital sigma-delta modulator as well. The synthesizer makes extensive use of custom VLSI, with only a simple off-chip loop filter and VCO required. The synthesizer operates from a single 3-V supply, and has low power consumption. Phase noise levels are less than -90 dBc/Hz at frequency offsets within the loop bandwidth. Spurious components are less than -90 dBc/Hz over a 19.6-MHz tuning range     

A 18-mW,20-MHz bandwidth,12-bit continuous-time∑△modulator using a power-efficient multi-stage amplifier

正A fourth-order continuous-time sigma delta modulator with 20-MHz bandwidth,implemented in 130nm CMOS technology is presented.The modulator is comprised of an active-RC operational-amplifier based loop filter,a 4-bit internal quantizer and three current steering feedback DACs.A three-stage amplifier with low power is designed to satisfy the requirement of high dc gain and high gain-bandwidth product of the loop filter.Non-return-to -zero DAC pulse shaping is utilized to reduce clock jitter sensitivity.A special layout technique guarantees that the main feedback DAC reaches 12-bit match accuracy,avoiding the use of a dynamic element matching algorithm to induce excess loop delay.The experimental results demonstrate a 64.6-dB peak signal-to-noise ratio,and 66-dB dynamic range over a 20-MHz signal bandwidth when clocked at 480 MHz with 18-mW power consumption from a 1.2-V supply.     

A 16-b 160-kHz CMOS A/D converter using sigma-delta modulation

The design and measured performance of a third-order sigma-delta analog-to-digital (A/D) converter sampling at 10.24 MHz that achieves a 91-dB signal-to-noise-plus-distortion ratio (RMS/RMS) with a 160-kHz output rate are discussed. The converter consists of three cascaded first-order sigma-delta modulators and a fourth-order comb decimation filter. A special autozeroed integrator having low pole error is required to achieve the 10.24-MHz sampling rate and high S/N. The modulator is implemented with fully differential switched-capacitor circuits and is manufactured using a 1.5-μm double-metal double-poly CMOS process     

A 400-MHz, 12-bit, 18-mW, IF digitizer with mixer inside asigma-delta modulator loop

A 0.8-μ BiCMOS, 400-MHz intermediate-frequency digitizer based on embedding a down-conversion mixer inside a sigma-delta modulator together with a reconstruction filter in the feedback path has been developed. The digitizer, when subsampled with a clock of 20 MHz, achieves a measured resolution of 12 bits for a 40-kHz bandwidth and dissipates 18 mW of power. The third harmonic distortion (HD₃) is less than -90 dBc for a -4-dB input, and the third-order intermodulation product (IM₃) is less than -70 dBc for a -8-dB input, with a full-scale voltage of 0.5 V. The chip area is 1.5 mm²     

Architecture, design, and test of continuous-time tunableintermediate-frequency bandpass delta-sigma modulators

This paper examines the architecture, design, and test of continuous-time tunable intermediate-frequency (IF) fourth-order bandpass delta-sigma (BP ΔΣ) modulators. Bandpass modulators sampling at high IFs (~100 MHz) allow direct sampling of the RF signal-reducing analog hardware and make it easier to realize completely software programmable receivers. This paper presents circuit design of and test results from continuous-time fourth-order BP ΔΣ modulators fabricated in AlInAs/GaInAs heterojunction bipolar technology with a peak unity current gain cutoff frequency (f_T) of 80 GHz and a maximum frequency of oscillation (f_MAX) of about 130 GHz. Operating from ±5-V power supplies, a fabricated 180-MHz IF fourth-order ΔΣ modulator sampling at 4 GS/s demonstrates stable behavior and achieves 75.8 dB of signal-to-(noise+distortion)-ratio (SNDR) over a 1-MHz bandwidth. Narrowband performance (~1 MHz) performance of these modulators is limited by thermal/device noise while broadband performance (~60 MHz), is limited by quantization noise. The high sampling frequency (4 GS/s) in this converter is dictated by broadband (60 MHz) performance requirements     

A 2.2-mW CMOS bandpass continuous-time multibit /spl Delta/-/spl Sigma/ ADC with 68 dB of dynamic range and 1-MHz bandwidth for wireless applications

A delta-sigma (/spl Delta//spl Sigma/) analog-to-digital converter featuring 68-dB dynamic range and 64-dB signal-to-noise ratio in a 1-MHz bandwidth centered at an intermediate frequency of 2 MHz with a 48-MHz sample rate is reported. A second-order continuous-time modulator employing 4-bit quantization is used to achieve this performance with 2.2 mW of power consumption from a 1.8-V supply. The modulator including references occupies 0.36 mm/sup 2/ of die area and is implemented in a 0.18-/spl mu/m five-metal single-poly digital CMOS process.     

Design and implementation of quadrature bandpass sigma-delta modulator used in low-IF RF receiver

This paper presents the design and implementation of quadrature bandpass sigma-delta modulator.A pole movement method for transforming real sigma-delta modulator to a quadrature one is proposed by detailed study of the relationship of noise-shaping center frequency and integrator pole position in sigma-delta modulator.The proposed modulator uses sampling capacitor sharing switched capacitor integrator,and achieves a very small feedback coefficient by a series capacitor network,and those two techniques can dramatically reduce capacitor area.Quantizer output-dependent dummy capacitor load for reference voltage buffer can compensate signal-dependent noise that is caused by load variation.This paper designs a quadrature bandpass Sigma-Delta modulator for 2.4 GHz low IF receivers that achieve 69 dB SNDR at 1 MHz BW and-1 MHz IF with 48 MHz clock.The chip is fabricated with SMIC 0.18 μm CMOS technology,it achieves a total power current of 2.1 mA,and the chip area is 0.48 mm2.     

Miniature surface-acoustic-wave filters

An introduction to Surface-Acoustic-Wave (SAW) devices-their operation, advantages, and applications--is presented. The process of design and realization of high-performance SAW filters is examined from initial specifications to final device operation. Several techniques drawn from a variety of disciplines illustrate the implementation of finite impulse response SAW frequency functions. Material properties, transducer weighting, and computer-aided design are treated. An example of the design and testing of a 321-MHz 0.35-percent bandwidth, 65-dB sidelobe, 15-dB insertion loss filter is presented.     

Managing subthreshold leakage in charge-based analog circuits with low-V/sub TH/ transistors by analog T- switch (AT-switch) and super cut-off CMOS (SCCMOS)

The analog T-switch (AT-switch) scheme is introduced to suppress subthreshold-leakage problems in charge-based analog circuits such as switched capacitors and sample-and-hold circuits. A 0.5-V sigma-delta modulator is manufactured in a 0.15-/spl mu/m FD-SOI process with low V/sub TH/ of 0.1 V using the concept. The scheme is compared with another leakage-suppression scheme based on super cut-off CMOS (SCCMOS) and the conventional circuit which are also fabricated. The sigma-delta modulator based on AT-switch greatly improves 8.1-dB SNDR through reducing nonlinear leakage effects while the modulator based on SCCMOS improves the dynamic range rather than the SNDR by comparing with the conventional sigma-delta modulator.     

A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

This paper presents a quadrature bandpass /spl Sigma//spl Delta/ modulator with continuous-time architecture. Due to the continuous-time architecture and the inherent anti-aliasing filter, the proposed /spl Sigma//spl Delta/ modulator needs no additional anti-aliasing filter in front of the modulator in contrast to quadrature bandpass /spl Sigma//spl Delta/ modulators with switched-capacitor architectures. The second-order /spl Sigma//spl Delta/ modulator digitizes complex analog I/Q input signals at 1-MHz intermediate frequency and operates within a clock frequency range of 25-100 MHz. The modulator chip achieves a peak signal-to-noise-distortion ratio (SNDR) of 56.7 dB and a dynamic range of 63.8 dB within a 1-MHz signal bandwidth and at a clock frequency of 100 MHz. Furthermore, it provides an image rejection of at least 40 dB. The 0.65-/spl mu/m BiCMOS chip consumes 21.8 mW at 2.7-V supply voltage.     

A selectable-bandwidth 3.5 mW, 0.03?mm2 self-oscillating Sigma Delta modulator with 71 dB dynamic range at 5?MHz and 65 dB at 10?MHz bandwidth

In this paper we present a dual-mode third-order continuous time $\Upsigma\Updelta$ modulator that combines noise-shaping and pulse-width-modulation (PWM). In our 0.18???m CMOS prototype chip the clock frequency equals 1?GHz, but the PWM carrier is only around 125?MHz. By adjusting the loop filter, the ADC bandwidth can be set to 5 or 10?MHz. In the 5?MHz mode the peak SNDR equals 64?dB and the dynamic range 71?dB. In the 10?MHz mode the peak SNDR equals 58?dB and the DR 65?dB. This performance is achieved at an attractively low silicon area of 0.03?mm² and a power consumption of 3.5?mW.     

连续时间Sigma Delta ADC设计和非理想因素分析

文章设计了一个用于物联网模拟基带的、低压、低功耗、宽带、连续时间Sigma Delta ADC,特别是对各种非理想因素（时钟抖动,环路延时,运放有限增益和带宽,比较器offset,DAC失配等）,基于matlab和simulink等工具进行了系统级仿真并得到各种非理想因素对系统性能的影响。电路架构采用3阶3bit前馈加反馈结构,电源电压1.2V,输入信号带宽为16MHz,过采样率为16,采样频率为512MHz。测试结果显示,SNR为60dB,SNDR为59.3dB,总功耗为22mW。