一种自适应DRAM刷新控制方法和DRAM刷新控制器

为了降低现有动态随机存取存储器（DRAM）刷新控制器基于平均刷新时间（tREFI）发送刷新指令所带来的系统性能损失,本文提供了一种自适应DRAM刷新控制方法和DRAM刷新控制器。本设计先将刷新指令进行缓存,然后判断读写总线状态,若读写总线空闲,将缓存的刷新指令顺序发送DRAM;若读写总线处于工作状态,依据缓存中刷新指令的数目决定是否将缓存的刷新指令顺序发给DRAM。     

FPGA与外部存储设备的接口实现

本文介绍了现场可编程门阵列(FPGA)与外部存储设备的接口实现问题，给出了SRAM和DRAM这两种典型的存储器接口实现的设计方法，分析了在FPGA具体实现过程中的一些常见问题，并提供了设计实现时所需的时序图和原理图。本设计采用VHDL。硬件描述语言编程，可以实现：FPGA与外围设备的高速数据传输，同时还可以扩大存储容量。其中FPGA与SRAM和DRAM的接口设计基本原理对其它同类的存储器也适用。     

一种速度低于100ns的256kDRAM

动态随机存取存贮器(DRAM)不仅在密度方面一直在提高,而且在实现高速度方面也在提高。由于三层多晶硅技术和增压高电平时钟发生器电路的使用,一种管芯面积为34.1mm~2、速度低于100ns的DRAM已经获得。这种器件能够以一个CAS时钟的15ns存取时间的半节型工作,并且也能够用CAS先于RAS的时序刷新。     

基于EDA技术的高速转换控制器的设计与研究

FPGA概述 FPGA是现场可编程门阵列的简称,是一种由用户实现芯片功能的器件,用户在设计完成之后可以进行功能仿真和时序仿真,也可以现场编程进行验证,有利于提前发现问题和进一步完善设计。其特点主要有：     

低成本科学级CCD数字相机的研制

介绍了科学级CCD芯片的主要性能参数和读出驱动时序要求，设计了图像采集总体方案。利用计算机EPP方式和采用CCD读出、A／D转换及数据传输流水线方法降低成本、噪声和实现难度。用复杂可编程器件(CPLD)实现了图像采集的各个控制信号，并给出了时序仿真波形。给出了相机的主要性能指标和在X射线数字实时成像检测中的应用。     

基于乒乓操作的异步FIFO设计及VHDL实现

目前的PLD(可编程逻辑器件)例如FPGA(现场可编程门阵列)凭借其灵活、方便、资源丰富的优势在很多领域得到了广泛应用.随着其片内存储资源的增加,把FIFO(先进先出)器件集成到PLD中是一种方便地代替专用FIFO芯片的实现方法.根据异步FIFO的设计方法,引入乒乓操作的设计技巧,给出了一种用FPGA实现异步FIFO的设计方案.     

一种用于高速数据采集的SDRAM控制器

同步动态随机存储器(SDRAM)在数据存储领域得到广泛的应用。针对一项基于PCI总线的高速数据采集系统提出了一种基于FPGA的SDRAM控制器的实现方法,FPGA中采用模块化设计方法。详细介绍了SDRAM控制器的组成结构和各模块功能,重点解决了SDRAM的刷新控制和空满检测问题,并对其进行了仿真验证,给出了全页读写模式下SDRAM的仿真时序图。仿真结果表明,SDRAM控制器实现了对SDRAM的读写操作,满足器件时序要求,完成了高速数据的大容量存储。     

内存条的结构与应用研究

采用大容量的存储器扩大单片机数据空间，常用的器件有：RAM、FLASH RAM、NVRAM以及DRAM。其中，DRAM具有容量特点大、价格低的优点。介绍了内存条的刷新原理和工作时序，详细讨论了89C51单片机与内存条接口设计的方法。最后采用ispLSI1032进行了集成处理，简单可靠，可使单片机系统拥有大容量的数据存储空间。     

基于1553B总线协议的解码器设计和FPGA实现

文章通过对1553B总线协议的研究,结合现代EDA技术,介绍了一种使用现场可编程逻辑器件(FPGA)设计1553B总线协议用的manchesterⅡ型码解码器的方法.通过采用Verilog HDL硬件描述语言和原理图混合输入法,使设计简洁有效.通过QuartusII开发软件对设计进行了时序约束和分析,最后给出了时序仿真...     

基于交叉双平面技术的图像采集存储系统

设计的系统能够实现对高速、大容量图像信息的采集和存储,采用模块化的设计思想,选用现场可编程门阵列(FPGA)作为逻辑控制器件,以一片三星公司生产的容量为4 Gbyte的NAND型Flash芯片K9WBF08U1M作为存储介质.针对图像信息高速存储的要求,提出利用交叉双平面页编程技术写Flash对数据进行存储.从硬件电路及逻辑时序两个方面介绍了此图像采集存储系统,并给出了试验结果.     

Cell-plate-line/bit-line complementary sensing (CBCS) architecturefor ultra low-power DRAMs

In the realization of gigabit scale DRAMs, one of the most serious problems is how to reduce the array power consumption without degradation of the operating margin and other characteristics. This paper proposes a new array architecture called cell-plate-line/bit-line complementary sensing (CBCS) architecture which realizes drastic array power reduction for both read/write operations and refresh operations, and develops a large readout voltage difference on the bit-line and cell-plate-line. For read/write operations, the array power reduces to only 0.2%, and for refresh operations becomes 36%, This architecture requires no unique process technology and no additional chip area. Using a test device with a 64-Mb DRAM process, the basic operation has been successfully demonstrated. This new memory core design realizes a high-density DRAM suitable for the 1-Gb level and beyond with power consumption significantly reduced     

GaAs dynamic memory design

Subthreshold leakage loss is a serious problem for GaAs dynamic memory. Since the leakage current in a MESFET is several orders of magnitude higher than that in a MOSFET, it is difficult to retain the charge at dynamic nodes resulting in data storage errors, In order to solve this problem, a novel DRAM architecture is proposed. The design is based on a cell consisting of a MESFET switch and a metal-insulator-metal (MIM) planar capacitor as the storage element. The leakage current is reduced by a level-shift technique and a self-biased transistor is used to maintain the dynamic charge during the sense period. A high performance sense amplifier is used to detect small bit line voltage changes and refresh the stored data. A 1 Kb prototype, fabricated in a 1 μm nonself-aligned GaAs MESFET technology, exhibited a total read/write access time of the order of 3 ns     

Design of a 128-mb SOI DRAM using the floating body cell (FBC)

A 128-Mb SOI DRAM has been developed featuring the floating body cell (FBC). To keep the cell data state from being degraded by the word-line (WL) disturb due to the charge pumping and to reduce the refresh busy rate, a sense amplifier (S/A) is arranged for every bit-line (BL) and replenishes data "1" cells' bodies with holes which are lost by the disturb in every read and write cycle. The power is reduced by operating the S/As asymmetrically between the selected and the unselected thanks to that the number of holes to be replenished in the unselected S/As for charge pumping is two order of magnitude smaller than that required for writing the data "1". The multi-pair averaging of dummy cells generates a very accurate reference current for distinguishing the data "1" and "0" and a Monte Carlo simulation shows that it achieves a sensing scheme robust enough to realize all good parts of the DRAM with a reasonable amount of redundancy. The cell's feature of quasi-nondestructive read-out is also advantageous for making an SRAM interface of the DRAM or hiding refresh from uses without sacrificing the access time.     

一种交错并行隐式刷新增益单元eDRAM设计

设计了一种与逻辑工艺兼容的64 kb高速高密度嵌入式增益单元动态随机存储器(eDRAM)。该存储器单元通过结构和版图的优化,典型尺寸为同代SRAM的40%。高低阈值管的引入分别改善了单元的读取速度和数据保持时间。同时交错并行隐式刷新机制利用增益存储单元读、写端口独立的结构和操作特性,配以合适的时序和仲裁机制,使得在无额外通信信号和握手接口下,实现刷新与访问互不影响,数据访问率达到100%。相比其他隐式刷新技术,该技术不需要过大的外围开销即可完成访问带宽加倍。芯片用SMIC 0.13μm CMOS工艺实现,大小为1.35 mm×1.35 mm。     

A 12-ns 8-Mbyte DRAM secondary cache for a 64-bit microprocessor

This paper describes three circuit technologies that have been developed for high-speed large-bandwidth on-chip DRAM secondary caches. They include a redundancy-array advanced activation scheme, a bus-assignment-exchangeable selector scheme and an address-zero access refresh scheme. By using these circuit technologies and new small subarray structures, a row-address access time of 12 ns and a row-address cycle time of 16 ns were obtained. An experimental chip made up of an 8-Mbyte DRAM and a 64-bit microprocessor was developed using 0.25-μm merged logic and DRAM process technology     

Hidden double data transfer scheme for MDL design [merged DRAMlogic]

A high-speed DRAM data transfer scheme between DRAM and logic parts in merged DRAM logic (MDL) designs is proposed with logically divided DRAM row address mapping. The proposed scheme results in a 20% faster write access and 40% faster read access. It can be used as a general design framework to maximise DRAM access speed in various MDL designs. A test chip has been fabricated by 0.16 μm DRAM technology, and the scheme has been verified in the design of a DRAM L2 cache memory     

A new extension method of retention time for memory cell on dynamic random access memory

Demands have been placed on dynamic random access memory (DRAM) to not only increase memory capacity and data transfer speed but also to reduce operating and standby currents. When a system uses DRAM, the restricted data retention time necessitates a refresh operation because each bit of the DRAM is stored as an amount of electrical charge in a storage capacitor. Power consumption for the refresh operation increases in proportion to memory capacity. A new method is proposed to reduce the refresh power consumption dynamically, when full memory capacity is not required, by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2^N cells/bit reduces the variation of retention times among memory cells. The proposed method reduces the frequency of disturbance and power consumption by two orders of magnitude. Furthermore, the conversion itself can be realized very simply from the structure of the DRAM array circuit, while maintaining all conventional functions and operations in the full array access mode.     

Block-based multiperiod dynamic memory design for low data-retention power

Dynamic random access memorys (DRAMs) are widely used in portable applications due to their high storage density. In standby mode, the main source of DRAM power dissipation is the refresh operation that periodically restores leaking charge in each memory cell to its correct level. Conventional DRAMs use a single refresh period determined by the cell with the largest leakage. This approach is simple but dissipative, because it forces unnecessary refreshes for the majority of the cells with small leakage. In this paper, we investigate a novel scheme that relies on small refresh blocks and multiple refresh periods to reduce DRAM dissipation by decreasing the number of cells refreshed too often. In contrast to conventional row-based refresh, small refresh blocks are used to increase worst case data retention times. Long periods are used to accommodate cells with small leakage. Retention times are further extended by adding a swap cell to each refresh block. We give a novel polynomial-time algorithm for computing an optimal set of refresh periods for block-based multiperiod refresh. Specifically, given an integer K and a distribution of data-retention times, in O(KN/sup 2/) steps our algorithm computes K refresh periods that minimize DRAM dissipation, where N is the number of refresh blocks in the memory. We describe and evaluate a scalable implementation of our refresh scheme whose overhead is asymptotically linear with memory size. In simulations with a 16-Mb DRAM, block-based multiperiod refresh reduces DRAM standby dissipation by a multiplicative factor of 4 with area overhead below 6%. Moreover, our proposed scheme is robust to semiconductor process variations, with power savings degrading no more than 7% over a 20-fold increase of leaky cells.     

A ferroelectric DRAM cell for high-density NVRAMs

The operation of a ferroelectric DRAM (dynamic random access memory) cell for nonvolatile RAM (NVRAM) applications is described. Because polarization reversal only occurs during nonvolatile store/recall operations and not during read/write operations, ferroelectric fatigue is not a serious endurance problem. For a 3-V power supply, the worst-case effective silicon dioxide thickness of the unoptimized lead zirconate titanate film studied is less than 17 Å. The resistivity and endurance properties of ferroelectric films can be optimized by modifying the composition of the film. This cell can be the basis of a very-high-density NVRAM with practically no read/write cycle limit and at least 10¹⁰ nonvolatile store/recall cycles