Best ROBDD variable ordering for functions with disjunctivedecompositions

The problem of finding a variable ordering to minimise the size of a reduced ordered binary decision diagrams (ROBDD) is considered for functions possessing disjunctive decompositions. An example is presented showing that the best ordering for a function with a disjunctive decomposition cannot always be directly determined from the best orderings for the component functions     

ROBDD complexity analysis for XOR/XNOR min-terms

This paper discusses the complexity of reduced ordered binary decision diagrams (ROBDDs) for Boolean functions with XOR/XNOR min-terms. Knowing the number of variables and the number of product terms of Boolean function containing only XOR/XNOR min-terms, one can predict the number of nodes in its ROBDD representation without building the binary decision diagram (BDD). A mathematical model for this prediction has been developed. This model can be used to find the maximum number of nodes for a given number of variables. Theoretical and experimental results are reported to underline the efficiency of this approach. The experimental results show that even though the XOR/XNOR min-terms cannot be simplified using Boolean laws or any other simplification method leading to a better min-term representation, the ROBDD will perform the simplification using the ROBDD reduction rules. The required memory is analysed for different methods of representation, and this analysis showed that ROBDDs are memory efficient structures to store and represent large numbers of XOR/XNOR min-terms in Boolean functions.     

Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design

Automatic test pattern generation (ATPG) is the next step after synthesis in the process of chip manufacturing. The ATPG may not be successful in generating tests for all multiple stuck-at faults since the number of fault combinations is large. Hence a need arises for highly testable designs which have 100% fault efficiency under the multiple stuck-at fault(MSAF) model. In this paper we investigate the testability of ROBDD based 2×1 mux implemented combinational circuit design. We show that the ROBDD based 2×1 mux implemented circuit is fully testable under multiple stuck-at fault model. Principles of pseudoexhaustive testing and multiple stuck-at fault testing of two level AND-OR gates are applied to one sub-circuit(2×1 mux). We show that the composite test vector set derived for all 2×1 muxes is capable of detecting multiple stuck-at faults of the circuit as a whole. Algorithms to derive test set for multiple stuck-at faults are demonstrated. The multiple stuck-at fault test set is larger than the single stuck-at fault test set. We show that the multiple stuck-at fault test set can be derived from the Disjoint Sum of Product expression which allows test pattern generation at design time, eliminating the need of an ATPG after the synthesis stage.     

Resistance-CMOS circuits

By combining dynamic CMOS circuits with a few resistive components, very simple sequential logic circuits with static behavior are obtained (e.g., frequency dividers, flip-flops, decoders). Using silicon gate technology and reverse-biased polysilicon diodes for the resistive elements, the area is nearly half that required for corresponding standard CMOS circuits.     

Low-power interface circuits between adiabatic and standard CMOS circuits

The clocking schemes and signal waveforms of adiabatic circuits are different from those of standard CMOS circuits. This paper investigates the design approaches of low-power interface circuits in terms of energy dissipation. Several low-power interface circuits that convert signals between adiabatic logic and standard CMOS circuits are presented. All interface circuits and their layouts are implemented using TSMC 0.18 μm CMOS technology. The function verifications and energy loss tests for all interfaces are carried out using the net-list extracted from the layout. Full parasitic extraction is done. An adiabatic 8-bit carry look-ahead adder embedded in a static CMOS circuits is used to verify the proposed interfaces. The proposed interface circuits attain large energy savings over a wide range of frequencies, as compared with the previously reported circuits.     

Advances in Reversed Nested Miller Compensation

The use of two frequency compensation schemes for three-stage operational transconductance amplifiers, namely the reversed nested Miller compensation with nulling resistor (RN-MCNR) and reversed active feedback frequency compensation (RAFFC), is presented in this paper. The techniques are based on the basic RNMC and show an inherent advantage over traditional compensation strategies, especially for heavy capacitive loads. Moreover, they are implemented without entailing extra transistors, thus saving circuit complexity and power consumption. A well-defined design procedure, introducing phase margin as main design parameter, is also developed for each solution. To verify the effectiveness of the techniques, two amplifiers have been fabricated in a standard 0.5-mum CMOS process. Experimental measurements are found in good agreement with theoretical analysis and show an improvement in small-signal and large-signal amplifier performances. Finally, an analytical comparison with the nonreversed counterparts topologies, which shows the superiority of the proposed solutions, is also included.     

Transistor equivalent circuits

This paper surveys the history of the electric-circuit representation of the transistor over the past fifty years. During the first two decades after the transistor was announced in 1948, primary emphasis was on small-signal equivalent circuits, which could be used for linear-circuit analysis and design. In addition, parameters of many of these equivalent circuits for the bipolar junction transistor, which are described, were related to the physical construction of the device. Approximately two-thirds of the paper is devoted to this period, when the writer personally contributed to this effort. By the beginning of the third decade, transistor circuits had became more complex, and circuit analysis was carried out with the help of digital computers. Interest then shifted away from small-signal equivalent circuits to “models” for computer-aided circuit design (CACD). This transition, including the models used in the widely used CACD program SPICE, is described. MOS transistors are treated only briefly; by the time MOS transistors became commercially viable devices, emphasis then also had shifted to “models” for CACD. In conclusion, the writer notes that there is still hope for us aficionados of small-signal equivalent circuits; new types of transistors are still being characterized in this manner     

Multivalued dynamic circuits

A new family of multivalued logic circuits is presented. These circuits exhibit some appealing features: they are the first MV dynamic operators reported in the literature, they implement the Vranesic-Smith-Lee algebra (which is specially suited for arithmetic operations), and their performance has been found to be similar to binary counterparts by simulation.     

Taking circuits seriously

The teaching of introductory circuit theory provides a context for comparing electrical engineering (EE) education of the 1950s and the present. It is argued that the classic introductory circuits course no longer serves anyone well and that revising it requires rethinking undergraduate EE education. It is proposed that the present course be reevaluated with respect to the principal goals of explaining the interrelationships among circuit concepts and providing students with an understanding of the field as a cohesive set of basic principles from which many useful results can be deduced     

Weakly superconducting circuits

An equivalent circuit has been developed for the time-dependent dissipating state of superconductivity which accompanies quantum phase slip. This equivalent circuit is used here to analyze the superconducting thin-film ring magnetometer and to determine its operating characteristics in terms of measurable circuit parameters.     

Broadband AGC circuits

Two types of broadband AGC circuits are described, one using a PIN diode, the other using a unijunction transistor. Performance data are given for frequency response, group delay, and AM to PM conversion.     

Self-timed logic circuits

Self-timed and asynchronous design techniques are currently proposed as a vehicle for pushing digital integrated circuits to higher levels of density and performance. The arguments for and against the adoption of these techniques are presented with illustrations from practical development projects. Some of the key principles behind self-timed operation are reviewed. Design tools to enable complex practical applications to be engineered are considered. For engineers who wish to find out more a selection of key references is provided     

Skew-tolerant domino circuits

Domino circuits are widely used in high-performance CMOS microprocessors. However, textbook domino pipelines suffer significant timing overhead from clock skew, latch delay, and the inability to borrow time. To eliminate this overhead, some designers provide multiple overlapping clock phases such that domino gates are always ready for evaluation by the time critical inputs arrive and do not precharge until the next gate consumes the result. This paper describes a systematic framework, called skew-tolerant domino circuits, for understanding and analyzing domino circuits with overlapping clocks. Simulations confirm that a speedup of 25% or more can be achieved over textbook domino circuits in high-speed systems     

Switched-capacitor modulator circuits

Four switched-capacitor modulator circuits which make use of the system clock as the carrier are presented. the circuits are simple and fast: the output signals are sampled at twice the rate of the system clock. Two of the circuits are also offset-free. Experimental results are described; they demonstrate the functionality of the new schemes.<>     

Digital logic circuits

Recent progress in Josephson digital logic circuits is described. It is noted that changing the junction material from a lead alloy to niobium has dramatically improved process reliability, and that high-speed, low-power operations have been demonstrated at large-scale integrated-circuit levels. The first Josephson microprocessor, operated at 770 MHz, verified the potential of Josephson devices for future digital elements. The possibilities of the ultrafast Josephson computer, previously shelved because of a number of problems, are being actively reconsidered. The performance anticipated for Josephson digital circuits using high-temperature superconducting materials is also discussed     

MOSFET memory circuits

Metal-oxide-semiconductor first effect transistors (MOSFETs) are currently being used in a variety of memory applications. The requirements of memory usage and the characteristics of MOSFET devices and technology have led to a number of unique circuits for these applications. Organization and design considerations of memory systems using MOSFET devices are reviewed, and examples of specific circuits are presented and analyzed. These include random access cells, shift registers, read only storage, and on-chip support circuits; both complementary and noncomplementary circuits are discussed.