模拟浮栅技术获得承认

正如其名称暗示的那样,浮栅晶体管的驱动端子与该器件的其它部分彼此绝缘,即它是悬浮的,因此从输入端子到其它端子之间没有直接的内部DC路径。40多年前,当半导体公司在检查     

0.1μm SOI槽栅pMOS器件特性

制造了栅长0.1μm,栅氧厚度5.6nm,栅槽180nm的SOI槽栅pMOSFET.给出了器件的转移特性和输出特性.在Vds=-1.5V时,其饱和漏电流为380μA,关态泄漏电流为1.9nA;在Vds=-0.1V下的亚阈值斜率为115mV/dec,DIBL因子为70.7mV/V.实验结果表明,0.1μm SOI槽栅pMOSFET比同尺寸体硅槽栅pMOSFET拥有更好的电流驱动能力和亚阈值特性.     

浮栅技术及其应用

介绍了浮栅技术的基本原理及应用情况。井对2种应用了浮栅技术的典型器件-浮栅MOS晶体管和神MOS晶体管做了详细介绍，分析了他们的基本结构和工作原理，以及建立浮栅MOS晶体管的等效模型，并说明了他们的应用情况及存在的不足。     

浮栅结构SOI LDMOS 器件的模拟研究

研究了一种具有浮栅结构的SOI LDMOS(FGSOI LDMOS)器件模型,并分析了该结构的耐压机理,通过Silvaco TCAD软件对该结构进行仿真优化。通过仿真验证可知,该结构通过类场板的结终端技术可以调节器件的横向电场,从而得到比普通SOI LDMOS器件更高的耐压并且降低了器件的比导通电阻。仿真结果表明,该结构与普通SOI LDMOS器件结构在相同的尺寸条件下耐压提高了41%,比导通电阻降低了21.9%。     

一种新型全耗尽双栅MOSFET

提出一种新型全耗尽双栅MOSFET,该器件具有异质栅和LDD结构.异质栅由主栅和两个侧栅组成,分区控制器件的沟道表面势垒.通过Tsuprem-4工艺模拟和Medici器件模拟验证表明,与普通双栅全耗尽SOI相比,该器件获得了更好的开态/关态电流比和亚阈值斜率.在0.18μm工艺下,开态/关态电流比约为1010,亚阈值斜率接近60mV/dec.     

一种新型全耗尽双栅MOSFET

提出一种新型全耗尽双栅MOSFET,该器件具有异质栅和LDD结构.异质栅由主栅和两个侧栅组成,分区控制器件的沟道表面势垒.通过Tsuprem-4工艺模拟和Medici器件模拟验证表明,与普通双栅全耗尽SOI相比,该器件获得了更好的开态/关态电流比和亚阈值斜率.在0.18μm工艺下,开态/关态电流比约为1010,亚阈值斜率接近60mV/dec.     

0.18μm浮栅Flash存储器件的总剂量辐射效应试验研究

针对自主设计的4 Mbit基于0.18μm商用CMOS flash工艺的浮栅flash存储器件进行了钴-60γ射线辐射效应试验研究.该存储器为FPGA的配置存储器.通过对被测器件分组,在加电配置和未加电配置条件下分别进行了钴-60γ射线辐射效应试验.试验实时监测了被测器件的工作电流以及其配置FPGA功能随总剂量变化的特...     

对称三材料双栅应变硅MOSFET亚阈值电流与亚阈值斜率解析模型

基于泊松方程和边界条件,推导了对称三材料双栅应变硅金属氧化物半导体场效应晶体管（MOSFET：metal oxide semiconductor field effect transistor）的表面势解析解.利用扩散-漂移理论,在亚阈值区电流密度方程的基础上,提出了亚阈值电流与亚阈值斜率二维解析模型.分析了沟道长度、功函数差、弛豫SiGe层的Ge组份、栅介质层的介电常数、应变硅沟道层厚度、栅介质高k层厚度和沟道掺杂浓度等参数对亚阈值性能的影响,并对亚阈值性能改进进行了分析研究.研究结果为优化器件参数提供了有意义的指导.模型解析结果与DESSIS仿真结果吻合较好.     

浮栅隧道氧化层EEPROM中浮栅上电荷泄漏研究

本文从研究不同单元尺寸浮栅隧道氧化层EEPROM在不同状态、不同温度保存下阈值电压的变化入手,论述了浮栅隧道氧化层EEPROM中浮栅上电荷的泄漏机理,并提出了改进EEPROM保持特性的措施.     

平面分离双栅金属氧化物半导体场效应晶体管的设计与制作

提出并制作了一种全新的平面分离双栅金属氧化物半导体场效应晶体管,该器件垂直于沟道方向的电场为一非均匀场.理论计算、TCAD三维器件仿真以及实验结果均表明,通过改变该器件中任何一个栅极偏置电压,能够得到可以调节的输出特性(增益系数)及转移特性曲线,可以很方便地调节器件的阈值电压及亚阈值摆幅并具备低功耗特点.这为电路的设计及器件制作提供了更多的灵活性,既可以简化电路的设计又可以降低MOS集成电路制造工艺的复杂程度.平面分离双栅金属氧化物半导体场效应晶体管制作工艺与目前常规的CMOS工艺完全兼容.     

平面分离双栅金属氧化物半导体场效应晶体管的设计与制作

提出并制作了一种全新的平面分离双栅金属氧化物半导体场效应晶体管,该器件垂直于沟道方向的电场为一非均匀场.理论计算、TCAD三维器件仿真以及实验结果均表明,通过改变该器件中任何一个栅极偏置电压,能够得到可以调节的输出特性(增益系数)及转移特性曲线,可以很方便地调节器件的阈值电压及亚阈值摆幅并具备低功耗特点.这为电路的设计及器件制作提供了更多的灵活性,既可以简化电路的设计又可以降低MOS集成电路制造工艺的复杂程度.平面分离双栅金属氧化物半导体场效应晶体管制作工艺与目前常规的CMOS工艺完全兼容.     

Characterization of Floating Gate Defects in Analog Cells

A unified approach to tackle the characterization of the floating gate defect in analog and mixed-signal circuits is introduced. An electrical level model of the defective circuit is proposed extending previous models used effectively in the digital domain. The poly-bulk, poly-well, poly-power rail and metal-poly capacitances are significant parameters in determining the behavior of the floating gate transistor. The model is used to analyze the feasibility of testing a simple analog cell with the floating gate defects through the observation of the quiescent current consumption and the dynamic behavior.     

浮动电极对屏蔽栅沟槽型MOSFET特性的影响

提出了在屏蔽栅沟槽型MOSFET(SGT)的沟槽侧壁氧化层中形成浮动电极的结构,通过改善电场分布,优化了特征导通电阻与特征栅漏电容。在传统SGT结构的基础上,仅通过增大外延层掺杂浓度,改变浮动电极的长度和位置以及氧化层厚度,最终得到击穿电压为141.1 V、特征导通电阻为55 mΩ·mm²、特征栅漏电容为4.72 pF·mm^-2的浮动电极结构。与相同结构参数的SGT结构相比,在击穿电压不变的条件下,浮动电极结构的特征导通电阻降低了9.3%,Baliga优值提升了13%,特征栅漏电容降低了28.4%。     

Multi-Input Floating Gate Differential Amplifier and Application to Intelligent Sensors

Multi-input floating gate differential amplifier (FGDA) is proposed which can perform any convolution operation with differential structure and feedback loop. All operations are in the voltage mode. Only one terminal is required for the negative feedback which can suppress distortions due to mismatches of active elements. Possible applications include intelligent image sensor, where fully parallel DCT operation can be performed. A prototype chip is fabricated which is functional. A preliminary test result is reported.     

纳米晶浮栅存储器的模拟、制备和电学特性

介绍了在纳米晶浮栅存储器数据保持特性方面的研究工作,重点介绍了纳米晶材料的选择与制备和遂穿介质层工程。研究证明,金属纳米晶浮栅存储器比半导体纳米晶浮栅存储器具有更好的电荷保持特性。并且金属纳米晶制备方法简单,通过电子束蒸发热退火的方法就能够得到质量较好的金属纳米晶,密度约4×1011cm-2,纳米晶尺寸约6～7nm。实验证明,高介电常数隧穿介质能够明显改善浮栅存储器的电荷保持特性,所以在引入金属纳米晶和高介电常数遂穿介质之后,纳米晶浮栅存储器可能成为下一代非挥发性存储器的候选者。     

Differential Hot Electron Injection in an Adaptive Floating Gate Comparator

We introduce differential-mode hot electron injection for adapting and storing analog nonvolatile signed state variables. This approach is compatible with modern digital CMOS technologies and is readily extended to novel circuit applications. We highlight advantages of the technique by applying it to the design of an adaptive floating gate comparator (AFGC). This is the first use of this technique for adaptation in a nonlinear circuit. The AFGC computes appropriate voltages for locally adapting the input floating gate nodes to cancel offsets. The technique is amenable to both local and nonlocal adaptation which allows greater design flexibility. The AFGC has been fabricated in a commercially available 0.35 μm CMOS process. We experimentally demonstrate more than two orders of magnitude reduction in offset voltage: the mean offset is reduced by 416× relative to chips direct from the foundry and by 202× relative to UV-irradiated chips. We consider both static and dynamic adaptation and demonstrate that the the accuracy of dynamic offset cancellation is approximately two orders of magnitude better than static adaptation. In the presence of observed 8% injection mismatch, the AFGC robustly converges to within 728 μV of the desired input offset (mean offset −109 μV, standard deviation 379 μV). Adaptation occurs within milliseconds, with charge retention for more than one month, and variation of offset error with temperature of −15 μV/°C.     

Differential Hot Electron Injection in an Adaptive Floating Gate Comparator

We introduce differential-mode hot electron injection for adapting and storing analog nonvolatile signed state variables. This approach is compatible with modern digital CMOS technologies and is readily extended to novel circuit applications. We highlight advantages of the technique by applying it to the design of an adaptive floating gate comparator (AFGC). This is the first use of this technique for adaptation in a nonlinear circuit. The AFGC computes appropriate voltages for locally adapting the input floating gate nodes to cancel offsets. The technique is amenable to both local and nonlocal adaptation which allows greater design flexibility.The AFGC has been fabricated in a commercially available 0.35 μm CMOS process. We experimentally demonstrate more than two orders of magnitude reduction in offset voltage: the mean offset is reduced by 416X relative to chips direct from the foundry and by 202X relative to UV-irradiated chips. We consider both static and dynamic adaptation and demonstrate that the the accuracy of dynamic offset cancellation is approximately two orders of magnitude better than static adaptation. In the presence of observed 8% injection mismatch, the AFGC robustly converges to within 728 μV of the desired input offset (mean offset −109 μV, standard deviation 379 μV). Adaptation occurs within milliseconds, with charge retention for more than one month, and variation of offset error with temperature of −15 μV/^∘C.Yanyi Liu Wong received the B.S. and M.S. degrees in Electrical Engineering in 2001 and 2004, respectively, from the University of Maryland, College Park, where he is currently working toward the Ph.D. degree. From 2001 to 2003, he was a Teaching Assistant for microelectronics lectures and labs. Since 2003, he has been with The Johns Hopkins University Applied Physics Laboratory developing Radiation-Hardened-By-Design EEPROM subsystems for space based ASICs. At the same time, he has been working as a Research Assistant at the Integrated Biomorphic Information Systems Laboratory, UMCP, and has been actively designing low-power, mixed-signal, adaptive floating gate circuits and applications in commercially available CMOS processes.Marc H. Cohen received both B.Sc. and M.Sc. degrees in Electrical Engineering from the University of the Witwatersrand, Johannesburg, South Africa in 1978 and 1983 respectively. He received an M.S. in Biomedical Engineering and a Ph.D. in Electrical and Computer Engineering from The Johns Hopkins University, Baltimore, MD, USA in 1991 and 2001 respectively. He is currently an Assistant Research Scientist in the Institute for Systems Research, University of Maryland, College Park. His research interests lie in the areas of adaptive low power analog and mixed-signal integrated circuit design. Current application areas include ultrasonic echolocation, contact imagers for control of microfluidic devices, controllers for adaptive optics and integrated sensors for RFID.Pamela A. Abshire received the B.S. degree in physics with honor in 1992 from the California Institute of Technology. Between 1992 and 1995 she worked as a Research Engineer in the Bradycardia Research Department of Medtronic, Inc. She received her M.S. and Ph.D. degrees in Electrical and Computer Engineering from The Johns Hopkins University in 1997 and 2002, respectively. She is currently an assistant professor in the Department of Electrical and Computer Engineering and the Institute for Systems Research at the University of Maryland, College Park. Dr. Abshire’s research focuses on low power mixed signal integrated circuit design, adaptive integrated circuits, integrated circuits for biosensing, and understanding the tradeoffs between performance and energy in natural and engineered systems.     

压电元件机电耦合系数定义研究

用作转换器的压电元件的一个重要特性是衡量其能量转换效率。常用来表征这一特征的参数是机电耦合系数。对于机电耦合系数这一参数,没有一个统一的定义,对目前常用的三种定义方式进行了分析,通过一个实例 — —长条片横向长度伸缩振动模式压电振子,比较了三种定义的联系、差别以及适用范围。分析结果表明:开路-短路计算方法是一种适用范围更广的方法。