用ispPAC20和isp1032实现可编程逐次逼近式A/D转换器的研究

ispPAC20在系统可编程模拟器件集放大器、比较器、D／A转换器为一体、方便地完成放大器、有源滤波器、方波发生器等模拟电路单元的设计。还可将其与isp1032结合实现可编程的逐次逼近式A／D转换。本文给出了一个设计,它具有控制灵活,可8方便地嵌入到电子系统设计中的优点。     

Binary weighted D/A converters with mismatch-shaping

A D/A convertor suited to multibit sigma-delta modulators is described. This convertor is able to shape the spectrum of the error caused by the mismatch among its components. The hardware implementation is based on a simple, binary-weighted structure     

基于16 bit Sigma-Delta模数转换器的数字滤波器设计

介绍了基于64倍过采样sigma-delta模数转换器的多级抽取滤波器设计.通过采用低功耗的多相分解梳状滤波器结构来代替传统的CIC滤波器结构,使得梳状滤波器部分的功耗降低近5倍.通过对滤波器电路结构的优化,可节省35%的芯片面积占用量.经过仿真及FPGA验证,该滤波器的信噪比达到99 dB,可以实现16位精度模数转换器的设计要求.     

New analogue multiplier-divider circuit based on cyclic data convertors

A new method for the realisation of analogue multiplier/divider circuits is presented. The method uses a modified cyclic data convertor that operates sequentially as an A/D convertor and as a D/A multiplying convertor in such a way that it performs the analogue operation v/sub 0/=v/sub x/v/sub y//v/sub z/.<>     

双积分A/D转换器的量程自动转换

介绍了一种双积分式A/D转换器在宽范围量程测量中的自动量程转换技术.在测量仪表的输入通道中,用计数器对双积分型A/D转换器本身所固有的过量程/欠量程信号计数,计数器的输出作为量程编码去控制量程的选择,同时又是送到CPU的量程指示信号.该技术扩大了A/D转换量程,提高了精度,设计简单,工作可靠.     

一种可重构流水线ADC的设计

对多标准无线通信系统中的A／D转换器进行了研究,根据无线通信系统的特点,构建了一个新型可重构流水线A／D转换器结构,该A／D转换器的可重构功能是通过在低分辨率下关断子级流水线来实现的。转换器的系统指标为6～14b,从而可以在保证不影响ADC性能的前提下,引入新颖的可重构控制以进一步降低功耗。最后对改进的可重构流水线ADC进行了性能仿真。     

基于AD650的VFC型A/D转换器

针对实际工程的技术要求，设计了一种新型高精度模数转换电路——VFC型A／D转换器。该电路作为计算机控制系统与受控设备之间的接口电路，在计算机控制下，所有的逻辑判断和校正网络均由计算机软件实现，此转换电路不仅调试方便、简单，而且增加了系统的可靠性。实践表明，设计的VFC型A／D转换电路完全满足系统设计要求。本文详细叙述了VFC型A／D转换电路的工作原理、设计思想和实现方法。     

基于S3C2440的多道脉冲幅度分析器硬件设计

传统的以单片机为核心的多道脉冲幅度分析器集成度低、软硬件设计难度大、系统升级困难。文中介绍了一种以高性能32位嵌入式处理器S3C2440处理为核心的多道脉冲幅度分析器的硬件设计方案,电路主要包括甄别电路、峰值扩展电路、控制电路和A/D转换电路。甄别电路通过设定阈值去除低能噪声信号,峰值检测电路进行输入信号的峰位检测和峰值扩展,A/D转换电路实现输入信号的模拟-数字量的转换。控制电精确控制了整个电路的工作时序。测试表明,该系统具备良好的微分非线性和积分非线性、速度快、稳定性好、可用于实际工作。     

2/sup 1///sub 2/ step flash A/D convertor

A simple technique for obtaining an extra bit of resolution from a multistep flash A/D convertor is described. It is shown that when used with a conventional multistep convertor, this technique can give significant savings in chip area and power at the expense of a very small increase in conversion time.<>     

一种可调精度的A/D转换器设计

现代测控系统对测量信号的处理基本由数字技术完成,A/D转换器的性能对系统具有重要的影响.采用SDM(∑-⊿调制器)实现A/D转换器,省略复杂的数字抽取滤波器,由DSP和CPLD对SDM输出的高速码流处理,实现A/D转换.DSP软件编程可以控制CPLD的计数器,实现可变精度(和速度)的A/D转换.通过对SDM特性分析,得到转换方法及计算公式,最后设计电路实现要求的功能.实验实现了最高16位A/D转换,很好地证明了设计分析的结论.     

Current-mode divide-by-two circuit

A current-mode divide-by-two circuit is presented which does not rely on well matched components and a high gain opamp. The circuit can be employee as a reference-generating circuit of an algorithmic current-mode A/D convertor.<>     

基于FPGA的高分辨率D／A转换器的实现

为增强FPGA（现场可编程门阵列）对模拟信号的处理能力,扩展FPGA的应用范围,介绍了一种基于FPGA实现高分辨率D／A转换器的技术。利用FPGA内部PLL（锁相环）,提高时钟信号的计数频率,从而提高PWM（脉宽调制）信号的基波频率,通过5阶巴特沃斯低通滤波器,实现14位高分辨率D／A转换器。阐述了PWM实现D／A转换器的理论基础和实际应用注意事项,该方法已用于实际D／A转换器系统,具有精度高、误差小的优点,对于FPGA的实际应用具有一定的指导意义。     

Analogue to digital convertor architecture with a signal leveldetector

A new signal level detector for a flash-type A/D convertor is introduced. It operates like a comparator with the 1-of-n encoder of flash-type A/D convertors. Because the clock signal can be omitted in the application of the comparator, clock feedthrough noise is not a problem. A resolution of up to 8 bits in A/D conversion is feasible     

基于FFT的两种伪码快速捕获方案的研究与实现

该文提出两种基于FFT的伪码快速捕获方案,一种是基于分数倍采样率转换器的快捕方案;另一种是基于抽取器的快捕方案。两种伪码快捕电路均利用设计复用技术使硬件规模大幅减少;采用并行设计使系统的运算速度大大提高;采用块浮点算法以提高动态范围和运算精度。两种快捕电路均由一块FPGA实现。仿真和测试结果表明,基于分数倍采样率转换器的快捕电路与基于抽取器的快捕电路相比,占用的硬件资源较大,但是捕获精度更高。     

Improved digital/analogue conversion technique using currentsplitting in lateral bipolar transistors

Describes the use of multiple collector lateral bipolar transistors as precision current splitting elements suitable for use in high resolution monolithic D/A convertor design. Multiple collector structures result in better overall linearity and smaller chip area than previously suggested techniques. A six-bit convertor implemented on a linear bipolar semicustom array is used to demonstrate the advantages of this technique     

8-bit micropower algorithmic A/D convertor

A switched-capacitor algorithmic A/D convertor is described, in which the amplifier offset compensation is inherent to the circuit structure and the effect of clock-feedthrough is as low as 0.5 mV. Preliminary experimental results, obtained on circuits fabricated using a low-voltage CMOS technology, indicate 8-bit resolution for 15 kHz sampling frequency, with only 350 ?W power consumption.     

5 GHz Josephson A/D converter

A four-bit A/D convertor using Nb/AlO_x/Nb Josephson junctions was fabricated. The circuit was designed to preserve the matching of characteristic impedances at all nodes. Four-bit A/D conversion was confirmed at a low frequency. The A/D convertor correctly operated at up to 5 GHz for two-bit conversion     

Interpolative bandpass A/D conversion-experimental results

Experimental results for a second order interpolative bandpass A/D convertor are presented. The A/D convertor operating at 10 MHz sampling rate is able to process narrow-band bandpass signals centred at 2.5 MHz. The effective resolution in a 80 kHz bandwidth is between 9 and 10 bits.<>     

Multiplexed noise shaping structures for delta-sigma modulators

A new structure for realising a multiplexed noise-shaping A/D convertor is proposed. It improves the performance of first- or second-order Delta Sigma modulators by employing additional feedback paths for suppressing the quantiser error. The structure, its theoretical analysis, and simulations confirming the improved resolution are presented.<>     

Dual translinear voltage/current convertor

A new voltage/current convertor (VCCS) using a translinear loop and two current mirrors is described. This convertor has two bipolar outputs, and two different loads can be used. The properties of this convertor are presented for direct current and sinusoidal input signals.