Two silicon nitride technologies for post-SiO2 MOSFETgate dielectric

P-MOSFETs with 14 Å equivalent oxide thickness (EOT) were fabricated using both JVD Si₃N₄ and RTCVD Si₃ N₄/SiO_xN_y gate dielectric technologies. With gate length down to 80 nm, the two technologies produced very similar device performances, such as drive current and gate tunneling current. The low gate leakage current, good device characteristics and compatibility with conventional CMOS processing technology make both nitride gate dielectrics attractive candidates for post-SiO₂ scaling. The fact that two significantly different technologies produced identical results suggests that the process window should be quite large     

Partial Crystallization of HfO2 for Two-Bit/Four-Level SONOS-Type Flash Memory

The nonvolatile memory properties of the partially crystallized HfO₂ charge storage layer are investigated using short-channel devices of gate length L_g down to 80 nm. Highly efficient two-bit and four-level device operation is demonstrated by channel hot electron injection programming and hot hole injection erasing for devices of L_g > 170 nm, although the reduction of the memory window is observed for devices of L_g < 170 nm. A memory window of 5.5 V, ten-year retention of V_th clearance larger than 1.5 V between adjacent levels, endurance for 10⁵ programming/erasing cycles, and immunity to programming disturbances are demonstrated. Flash memory with partially crystallized HfO₂ shows a larger memory window than HfO₂ nanodot memory, assisted by the enhanced electron capture efficiency of an amorphous HfO₂ matrix, which is lacking in other types of reported nanodot memory. The scalability, programming speed, V_th control for two-bit and four-level operation, endurance, and retention are also improved, compared with NROM devices that use a Si₃N₄ trapping layer.     

Plasma-charging effects on submicron MOS devices

Plasma-charging damage on gate dielectrics of MOS devices is an important issue because of shrinking dimension, plasma nonuniformity, and effects on high-k gate dielectrics. A comprehensive study of plasma-charging effects on the electrical properties of MOS devices was investigated in this work. Shunt diodes were used to estimate the charging polarity distribution. For high-frequency application, the 1/f noise was found to be a promising index for assessing plasma-charging damage. Gate oxynitride formed by two-step nitridation was demonstrated to have better electrical reliability as compared to the conventional one-step nitridation, especially accompanied by amorphous silicon gate electrode. This improvement could be attributed to the relaxation of interface stress by amorphous silicon gate electrode and the suppression of hydrogen effects by gate oxynitride using two-step nitridation. Plasma-charging damage on Si₃N₄ and Ta₂O₅ gate dielectrics with high dielectric constant was also investigated. For MOS devices with Si₃N₄ film, the leakier characteristic and shorter time to breakdown reveal its inferior reliability. For MOS devices with Ta₂O₅ gate dielectric, the trap-assisted current mechanism makes a thicker physical thickness of Ta₂O₅ film more susceptible to plasma-charging-induced damage. Smaller physical thickness of Ta₂O₅ film in MOS devices is favorable due to the better reliability and comparable plasma-induced electrical degradation     

High-speed enhancement-mode InP MISFET's grown by chloridevapor-phase epitaxy

The properties of enhancement-mode InP metal-insulator-semiconductor field-effect transistors fabricated on semi-insulating InP substrates are reported. The epitaxial layers of the device structure have been grown by chloride vapor-phase epitaxy. Short-circuit current gain cutoff frequencies of 29.6 GHz were measured for 1-μm-gate-length devices. For devices with submicrometer gate lengths, extrinsic transconductance values up to 300 mS/mm and short-circuit current-gain cutoff frequencies of 38.1 GHz were measured. SiO₂ deposited by electron beam evaporation and plasma-enhanced CVD Si₃N₄ have been utilized as gate insulators, and a drain current drift of 30% within the first 50 h of operation has been observed. The high-speed performance of these devices represent to the authors' knowledge the fastest InP-based MIS field-effect transistor demonstrated     

Performance and hot-carrier reliability of 100 nm channel lengthjet vapor deposited Si3N4 MNSFETs

Metal-nitride-semiconductor FETs (MNSFETs) having channel lengths down to 100 mm and a novel jet vapor deposited (JVD) Si₃N₄ gate dielectric have been fabricated and characterized. When compared with MOSFETs having a thermal SiO₂ gate insulator, the MNSFETs show a comparable drain current drive, transconductance, subthreshold slope and pre-stress interface quality. A novel charge pumping technique is employed to characterize the hot-carrier induced interface-trap generation in MNSFETs and MOSFETs. Under identical substrate current during stress, MNSFETs show less interface-state generation and drain current degradation, for various channel lengths, stress times and supply voltages, despite the fact that the Si-Si₃N₄ barrier (2.1 eV) is lower than the Si-SiO₂ barrier (3.1 eV). The time and voltage dependence of hot-carrier degradation has been found to be distinctly different for MNSFETs compared to SiO₂ MOSFETs     

Border-Trap Characterization in High-κ Strained-Si MOSFETs

In this letter, we focus on the border-trap characterization of TaN/HfO₂/Si and TaN/HfO₂/strained-Si/Si_0.8Ge_0.2 n-channel MOSFET devices. The equivalent oxide thickness for the gate dielectrics is 2 nm. Drain-current hysteresis method is used to characterize the border traps, and it is found that border traps are higher in the case of high-kappa films on strained- Si/Si_0.8Ge_0.2 .These results are also verified by the 1/f-noise measurements. Possible reasons for the degraded interface quality of high-kappa films on strained-Si are also proposed.     

GaAs metal insulator field effect transistors with excellentintrinsic transconductance and stable drain currents using (NH4)2Sx chemical treatment

Metal insulator semiconductor field effect transistors (MISFETs) and MIS capacitors are fabricated using Al metal-gate and PECVD silicon nitride (Si₃N₄) gate-insulator on commercial GaAs epitaxial wafers after treating the channel regions with (NH₄)₂S_x. It is shown that the post metallization annealing (PMA) of these devices improves the transconductance and reduces the interface state density (D_it) considerably. This is attributed to the additional passivation effect of hydrogen diffusing to the interface from the Si ₃N₄ during the PMA. An intrinsic transconductance of 30.7 mS/mm which is 75% of the theoretical maximum limit of 40.5 mS/mm has been achieved using silicon nitride gate insulator thickness of 1100 Å. Stability of the drain currents in these devices is demonstrated to be excellent     

Vertical Enhancement-Mode InAs Nanowire Field-Effect Transistor With 50-nm Wrap Gate

We present results on fabrication and dc characterization of vertical InAs nanowire wrap-gate field-effect transistor arrays with a gate length of 50 nm. The wrap gate is defined by evaporation of 50-nm Cr onto a 10-nm-thick HfO₂ gate dielectric, where the gate is also separated from the source contact with a 100-nm SiO_x, spacer layer. For a drain voltage of 0.5 V, we observe a normalized transconductance of 0.5 S/mm, a subthreshold slope around 90 mV/dec, and a threshold voltage just above 0 V. The highest observed normalized on current is 0.2 A/mm, with an off current of 0.2 mA/mm. These devices show a considerable improvement compared to previously reported vertical InAs devices with SiN_x, gate dielectrics.     

Electrical Characteristics of Memory Devices With a High- k HfO2 Trapping Layer and Dual SiO2/Si3N4 Tunneling Layer

A novel device structure with a high-k HfO₂ charge storage layer and dual tunneling layer (DTL) (SiO₂/Si₃N₄) is presented in this paper. Combining advantages of the high trapping efficiency of high-k materials and enhanced charge injection from the substrate through the DTL, the device achieves a fast program/erase speed and a large memory window. The device demonstrates excellent retention due to its physically thick DTL and also improved endurance without any increase of programming V_th throughout the cyclic test as compared with SONOS Flash memory devices using an Si₃N₄ trapping layer.     

Atomic layer deposited HfO/sub 2/in metal?insulator?metal capacitor for RF IC applications

DC and RF characteristics of Si/SiO₂(~4 mum)/Ti/Pt-HfO₂-Al metal-insulator-metal (MIM) devices were investigated with atomic layer-deposited (ALD) high-k HfO₂ films. Excellent DC and RF properties were obtained compared to those using either SiO₂ or Si₃N₄. Both high capacitance density and small frequency-dependent capacitance reduction were observed in the MIM capacitors, in which ALD HfO₂ was used as an insulator.     

A high performance MIM capacitor using HfO2 dielectrics

Metal-insulator-metal (MIM) capacitors with a 56 nm thick HfO₂ high-κ dielectric film have been fabricated and demonstrated for the first of time with a low thermal budget (~200°C). Voltage linearity, temperature coefficients of capacitance, and electrical properties are all characterized. The results show that the HfO₂ MIM capacitor can provide a higher capacitance density than Si₃N₄ MIM capacitor while still maintaining comparable voltage and temperature coefficients of capacitance. In addition, a low leakage current of 2×10^-9 A/cm² at 3 V is achieved. All of these make the HfO ₂ MIM capacitor to be very suitable for use in silicon RF and mixed signal IC applications     

Effects of post-deposition anneal on the electrical properties ofSi3N4 gate dielectric

The effects of postdeposition anneal of chemical vapor deposited silicon nitride are studied. The Si₃N₄ films were in situ annealed in either H₂(2%)/O₂ at 950°C or N₂O at 950°C in a rapid thermal oxidation system. It is found that an interfacial oxide was grown at the Si₃N₄/Si interface by both postdeposition anneal conditions. This was confirmed by thickness measurement and X-ray photoelectronic spectroscopy (XPS) analysis. The devices with H₂ (2%)/O₂ anneal exhibit a lower gate leakage current and improved reliability compared to that of N₂O anneal. This improvement is attributed to a greater efficiency of generating atomic oxygen in the presence of a small amount of hydrogen, leading to the elimination of structural defects in the as-deposited Si₃N ₄ film by the atomic oxygen. Good drivability is also demonstrated on a 0.12 μm n-MOSFET device     

Effects of high-κ gate dielectric materials on metal andsilicon gate workfunctions

The dependence of metal and polysilicon gate work-functions on the underlying gate dielectric in advanced MOS gate stacks is explored. We observe that the metal workfunctions on high-κ dielectrics differ appreciably from their values on SiO₂ or in a vacuum. We also show the first application of the interface dipole theory on the metal-dielectric interface and obtained excellent agreement with experimental data. Important parameters such as the slope parameters for SiO₂, Si₃N₄, ZrO₂, and HfO ₂ are extracted. In addition, we also explain the weaker dependence of n+ and p+ polysilicon gate workfunctions on the gate dielectric. Challenges for gate workfunction engineering are highlighted. This work provides additional guidelines on the choice of gate materials for future CMOS technology incorporating high-κ gate dielectrics     

The effect of surface passivation on the microwave characteristicsof undoped AlGaN/GaN HEMTs

Surface passivation of undoped AlGaN/CaN HEMT's reduces or eliminates the surface effects responsible for limiting both the RF current and breakdown voltages of the devices. Power measurements on a 2×125×0.5 μm AlGaN/GaN sapphire based HEMT demonstrate an increase in 4 GHz saturated output power from 1.0 W/mm [36% peak power-added efficiency (PAE)] to 2.0 W/mm (46% peak PAE) with 15 V applied to the drain in each case. Breakdown measurement data show a 25% average increase in breakdown voltage for 0.5 μm gate length HEMT's on the same wafer. Finally, 4 GHz power sweep data for a 2×75×0.4 μm AlGaN/GaN HEMT on sapphire processed using the Si₃N₄ passivation layer produced 4.0 W/mm saturated output power at 41% PAE (25 V drain bias). This result represents the highest reported microwave power density for undoped sapphire substrated AlGaN/GaN HEMT's     

Electrical Properties of Low-Temperature-Compatible P-Channel Polycrystalline-Silicon TFTs Using High-$kappa$ Gate Dielectrics

In this paper, we describe a systematic study of the electrical properties of low-temperature-compatible p-channel polycrystalline-silicon thin-film transistors (poly-Si TFTs) using HfO₂ and HfSiO_x, high-k gate dielectrics. Because of their larger gate capacitance density, the TFTs containing the high-k gate dielectrics exhibited superior device performance in terms of higher I_on/I_off current ratios, lower subthreshold swings (SSs), and lower threshold voltages (V_th), relative to conventional deposited-SiO₂, albeit with slightly higher OFF-state currents. The TFTs incorporating HfSiO_x, as the gate dielectric had ca. 1.73 times the mobility (mu_FE) relative to that of the deposited-SiO₂ TFTs; in contrast, the HfO₂ TFTs exhibited inferior mobility. We investigated the mechanism for the mobility degradation in these HfO₂ TFTs. The immunity of the HfSiO_x, TFTs was better than that of the HfO₂ TFTs-in terms of their V_th shift, SS degradation, mu_FE degradation, and drive current deterioration-against negative bias temperature instability stressing. Thus, we believe that HfSiO_x, rather than HfO₂, is a potential candidate for use as a gate-dielectric material in future high-performance poly-Si TFTs.     

Design optimization of stacked layer dielectrics for minimum gate leakage currents

An effective model to evaluate the leakage currents for different stacked gates deep submicron MOS transistors is presented. For a given equivalent oxide thickness of a stacked gate, the gate leakage current decreases with an increase of high-k dielectric thickness or a decrease of interlayer thickness. Turning points at high gate biases of the I–V curves are observed for Si₃N₄/SiO₂, Ta₂O₅/SiO₂, Ta₂O₅/SiO_2−yN_y, Ta₂O₅/Si₃N₄, and TiO₂/SiO₂ stacked gates except for Al₂O₃/SiO₂ structure. Design optimization for the stacked gate architecture to obtain the minimum gate leakage current is evaluated.     

Enhanced H2-plasma effects on polysilicon thin-filmtransistors with thin ONO gate-dielectrics

This letter reports that passivation effects of the H₂-plasma on the polysilicon thin-film transistors (TFT's) were greatly enhanced if the TFT's have a thin Si₃N₄ film on their gate-dielectrics. Compared to the conventional devices with only the SiO₂ gate dielectric, the TFT's with Si ₃N₄ have much more improvement on their subthreshold swing and field-effect mobility after H₂-plasma treatment     

The performance and reliability of PMOSFET's with ultrathin siliconnitride/oxide stacked gate dielectrics with nitrided Si-SiO2interfaces prepared by remote plasma enhanced CVD and post-depositionrapid thermal annealing

Ultrathin (~1.9 nm) nitride/oxide (N/O) dual layer gate dielectrics have been prepared by the remote plasma enhanced chemical vapor deposition (RPECVD) of Si₃N₄ onto oxides. Compared to PMOSFET's with heavily doped p⁺-poly-Si gates and oxide dielectrics, devices incorporating the RPECVD stacked nitrides display reduced tunneling current, effectively no boron penetration and improved interface characteristics. By preventing boron penetration into the bulk oxide and channel region, gate dielectric reliability and short channel effects are significantly improved. The hole mobility in devices with N/O dielectrics with equivalent oxide thickness between 1.8 nm and 3.0 nm is not significantly degraded. Because nitrogen is transported to the substrate/dielectric interface during post-deposition annealing, degradation of mobility during hot carrier stressing is significantly reduced for N/O devices. Compared with oxide, the tunneling current for N/O films with ~1.9 nm equivalent oxide thickness is lower by about an order of magnitude due to the larger physical thickness. Suppression of boron transport in nitride layers is explained by a percolation model in which boron transport is blocked in sufficiently thick nitrides, and is proportional to the oxide fraction in oxynitride alloys     

Off-state gate current in n-channel MOSFETs with nitrided oxidegate dielectrics

The authors report on the off-state gate current (I_g ) characteristics of n-channel MOSFETs using thin nitrided oxide (NO) gate dielectrics prepared by rapid thermal nitridation at 1150°C for 10-300 s. New phenomena observed in NO devices are a significant I_g at drain voltages as low as 4 V and an I_g injection efficiency reaching 0.8, as compared to 8.5 V and 10^-7 in SiO₂ devices with gate dielectrics of the same thickness. Based on the drain bias and temperature dependence, it is proposed that I_g in MOSFETs with heavily nitrided oxide gate dielectrics arises from hot-hole injection, and the enhancement of gate current injection is due to the lowering of valence-band barrier height for hole emission at the NO/Si interface. The enhanced gate current injection may cause accelerated device degradation in MOSFETs. However, it also presents potential for device applications such as EPROM erasure     

AlGaN/GaN MOS-HEMT With $hbox{HfO}_{2}$ Dielectric and $hbox{Al}_{2}hbox{O}_{3}$ Interfacial Passivation Layer Grown by Atomic Layer Deposition

We have developed a novel AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistor using a stack gate HfO₂/Al₂O₃ structure grown by atomic layer deposition. The stack gate consists of a thin HfO₂ (30-A) gate dielectric and a thin Al₂O₃ (20- A) interfacial passivation layer (IPL). For the 50-A stack gate, no measurable C-V hysteresis and a smaller threshold voltage shift were observed, indicating that a high-quality interface can be achieved using a Al₂O₃ IPL on an AlGaN substrate. Good surface passivation effects of the Al₂O₃ IPL have also been confirmed by pulsed gate measurements. Devices with 1- mum gate lengths exhibit a cutoff frequency (fT) of 12 GHz and a maximum frequency of oscillation (f _MAX) of 34 GHz, as well as a maximum drain current of 800 mA/mm and a peak transconductance of 150 mS/mm, whereas the gate leakage current is at least six orders of magnitude lower than that of the reference high-electron mobility transistors at a positive gate bias.