铁电存储器和IC卡

铁电薄膜与半导体集成产生了新一代非易失存储器，与传统的半导体非易失存储器比较具有突出的优点，是新一代ＩＣ卡的理想存储芯片。     

Effective march algorithms for testing single-order addressed memories

Today's commonly used macro generators provide for read/write memories of type SRAM, Register File, Multi-Port RAM, Single-Order Addressed Memory (e.g. FIFO), CAM (Content Addressable Memory), etc. In addition to automatically generating the required momory, the appropriate test, which may be applied externally or internally as a BIST, has to be determined.Current literature provides tests for most memory types; however, tests for single-order addressed (SOA) memories, whereby the address can only change in one direction (e.g. from address 0 ton-1) have not been published yet. SOA memories are used in FIFOs and in applications where the BIST area overhead and/or speed penalty for normal (dual) order addressing are not acceptable.This article illustrates the testing problems and presents a family of march algorithms optimized for testing SOA memories.     

Large-capacity semiconductor memory

Integrated-circuit memories using bipolar transistor technology are compared with memories based on various forms of the insulated-gate field-effect transistor (IGFET). A combination of p-channel IGFET memory cells with bipolar transistor access circuits appears to offer a desirable combination of characteristics. Memory organization, chip design, packaging, and interconnection alternatives are considered. Beam-lead sealed-junction technology has significant advantages over other packaging and interconnection technologies in the realization of semiconductor memory. Some of the problems expected in the design of a million-bit computer memory are examined with attention to power dissipation, interconnections, reliability, maintainability, and cost. Finally, the potential characteristics of a million-bit semiconductor memory based on today's technology are compared with the characteristics of ferrite core, planar film, and cylindrical film magnetic memories. The conclusion drawn from this exploratory study is that semiconductor memory has attractive potential for both small- and large-capacity memory applications.     

Electrically Driven Random Laser Memory

The first electrically driven random laser diode with nonvolatile resistive random access memory functionality is designed and demonstrated. To illustrate the working principle, a metal–insulator–semiconductor structure based on Pt/MgO/ZnO thin‐film layers is fabricated on indium tin oxide glass. The current–voltage curve of the dual‐function random laser memory (RLM) device exhibits an excellent electrical bistability with a high ON/OFF current ratio (≈10⁷). The random lasing behavior is simultaneously demonstrated by using electrical pumping with the appearance of sharp‐peak emissions and a drastic enhancement of peak intensity. A wide angle‐dependent electroluminescence not only reveals its emitting advantage but also further supports the origin of random lasers. The first proof‐of‐concept presentation of RLM possesses several advantages of dual memory and lasing functions, which enables to open up new avenues to practical applications, such as light emitting memories for electrical and optical communication. This new horizon for the realization of all optical memories should therefore be able to attract academic as well as industrial interests. It is stressed here that the electrical reading of conventional memory array is usually in serial sequence, which limits the maximum data throughput. This hurdle can be overcome by optically readable memory devices.     

SoC嵌入式flash存储器的内建自测试设计

深亚微米技术背景下，嵌入式存储器在片上系统芯片(system-on-a-chip，SoC)中占有越来越多的芯片面积．嵌入式存储器的测试正面临诸多新的挑战。本文论述了两种适合SoC芯片中嵌入式flash存储器的内建自测试设计方案。详细讨论了专用硬件方式内建自测试的设计及其实现，并且提出了一种新型的软硬协同方式的内建自测试设计。这种新型的测试方案目标在于结合专用硬件方式内建自测试方案并有效利用SoC芯片上现有的资源，以保证满足测试过程中的功耗限制，同时在测试时间和芯片面积占用及性能之间寻求平衡。最后对两种方案的优缺点进行了分析对比。     

嵌入式存储器空间单粒子效应失效率评估方法研究

嵌入式存储器易受到空间单粒子效应(Single-Event Effects, SEE)的影响。该文提出了一种单粒子效应失效率评估的方法,包含了单粒子翻转和单粒子瞬态扰动等效应对嵌入式存储器不同电路单元的具体影响,可对不同存储形式、不同容错方法的嵌入式存储器单粒子效应失效率进行定量评估。该文提出的评估方法在中国科学院电子学研究所自主研制的嵌入式可编程存储器试验芯片上得到了验证,地面单粒子模拟实验表明该文方法预测的失效率评估结果与实验测试结果的平均偏差约为10.5%。     

存储器故障诊断算法的研究与实现

集成电路工艺的改进使存储器的测试面临着更大的挑战。文中从存储器的故障模型入手,着重描述了存储器常见的诊断算法。诊断算法和诊断策略要在诊断时间、故障覆盖率、面积开支之间进行权衡。因此要根据存储器的故障类型和测试需求来选择合适的诊断算法,才能达到比较满意的效果。     

地址数据复用型Flash存储器测试技术研究

随着半导体技术的迅猛发展,移动存储设备快速增长。Flash芯片作为移动存储设备中最常用的器件,得到了日趋广泛的应用,对Flash芯片的测试要求也越来越高。地址数据复用型Flash存储器测试技术研究及电路设计,设计改善大规模数字集成电路测试系统数字系统算法图形功能。对K9F2G08R0A进行了测试并通过对数字系统算法图形功能进行改善,算法图形发生器由多个算术逻辑单元、多路选择器以及操作寄存器组成,可以实现复杂的逻辑操作和算术运算,可以更快、更简便地对地址复用型Flash存储器进行测试,减少测试程序开发难度。     

纳米晶浮栅存储器的模拟、制备和电学特性

介绍了在纳米晶浮栅存储器数据保持特性方面的研究工作,重点介绍了纳米晶材料的选择与制备和遂穿介质层工程。研究证明,金属纳米晶浮栅存储器比半导体纳米晶浮栅存储器具有更好的电荷保持特性。并且金属纳米晶制备方法简单,通过电子束蒸发热退火的方法就能够得到质量较好的金属纳米晶,密度约4×1011cm-2,纳米晶尺寸约6～7nm。实验证明,高介电常数隧穿介质能够明显改善浮栅存储器的电荷保持特性,所以在引入金属纳米晶和高介电常数遂穿介质之后,纳米晶浮栅存储器可能成为下一代非挥发性存储器的候选者。     

Flash memory architecture

Flash memories entered the nonvolatile memory scenario only a few years ago, and now these kind of memories are battling to substitute either EEPROM or EPROM. In fact, their peculiarities are becoming quite interesting in present day applications.In system updating, low power consumption, embedded algorithm for program and erase, high density, low cost packages are some of the items which are making the Flash grow in the nonvolatile memory market share.Some words must be spent in explaining what the market is asking of Flash, which are the main applications for these memories, and how their architecture is arranged.The Flash memory cell behaviour will be described, then the fundamental operations (read, program and erase) are explained and some words are used to introduce the redundancy and device testability concept.     

A Die‐Selection Method Using Search‐Space Conditions for Yield Enhancement in 3D Memory

Three‐dimensional (3D) memories using through‐silicon vias (TSVs) as vertical buses across memory layers will likely be the first commercial application of 3D integrated circuit technology. The memory dies to stack together in a 3D memory are selected by a die‐selection method. The conventional die‐selection methods do not result in a high‐enough yields of 3D memories because 3D memories are typically composed of known‐good‐dies (KGDs), which are repaired using self‐contained redundancies. In 3D memory, redundancy sharing between neighboring vertical memory dies using TSVs is an effective strategy for yield enhancement. With the redundancy sharing strategy, a known‐bad‐die (KBD) possibly becomes a KGD after bonding. In this paper, we propose a novel die‐selection method using KBDs as well as KGDs for yield enhancement in 3D memory. The proposed die‐selection method uses three search‐space conditions, which can reduce the search space for selecting memory dies to manufacture 3D memories. Simulation results show that the proposed die‐selection method can significantly improve the yield of 3D memories in various fault distributions.     

Novel Photoinduced Recovery of OFET Memories Based on Ambipolar Polymer Electret for Photorecorder Application

A new design concept for novel photoresponsive flash organic field‐effect transistor (OFET) memory is demonstrated by employing the carbazoledioxazine polymer (Poly CD) as an electret. Photoactive electrets that can absorb the light effectively rather than photoactive semiconductors are proposed by the “photoinduced recovery” mechanism in the literature; however, the correlation between the chemical structure and photoresponsive electrical performances is ambiguous. In this study, it is reported for the first time that the OFET memory with trapped charges can be optically recovered by a polymer electret and the working mechanism can be explained by the structural design. The highly planar Poly CD electret exhibits photoluminescence quenching in film states, resulting in the generation of sufficient excitons to eliminate trapped charges under light excitation. Additionally, the Poly CD electret with coplanar donor–acceptor moieties is suitable for both p‐channel and n‐channel semiconductors. For p‐type memory devices, a large memory window (82 V) and stable nonvolatile retention performance with high ON/OFF ratio could be obtained. The memories also display good switching reliability for voltage‐programming and light‐erasing cycles. This study provides useful information for the development of polymer‐based photoresponsive flash OFET memories and demonstrates the practical applications of photorecorder and photosensitive smart tag.     

A survey of circuit innovations in ferroelectric random-accessmemories

This paper surveys circuit innovations in ferroelectric memories at three circuit levels: memory cell, sensing and architecture. A ferroelectric memory cell consists of at least one ferroelectric capacitor, where binary data are stored, and one or two transistors that either allow access to the capacitor or amplify its contents for a read operation. Once a cell is accessed for a read operation, its data are presented in the form of an analog signal to a sense amplifier, where it is compared against a reference voltage to determine its logic level. The circuit techniques used to generate the reference voltage must be robust to semiconductor processing variations across the chip and the device imperfections of ferroelectric capacitors. We review six methods of generating a reference voltage, two being presented for the first time in this paper. These methods are discussed and evaluated in terms of their accuracy, area overhead and sensing complexity. Ferroelectric memories share architectural features such as addressing schemes and input/output circuitry with other types of random-access memories such as dynamic random-access memories. However, they have distinct features with respect to accessing the stored data, sensing, and overall circuit topology. We review nine different architectures for ferroelectric memories and discuss them in terms of speed, density and power consumption     

Comparison of three different architectures for active resistive memories

Resistive memory (RRAM) is one of the strong emerging technologies in modern memory field. This type of memories has the potential to be the replacement of several current memory types. As any new technology, RRAM brings new challenges concerning technology and design. This work discusses some aspects concerning the design of active resistive memories and compares three possible memory architectures.     

Configurable Data Memory for Multimedia Processing

In modern multimedia applications, memory bottleneck can be alleviated with special stride data accesses. Data elements in stride access can be retrieved in parallel with parallel memories, in which the idea is to increase memory bandwidth with several memory modules working in parallel and feed the processor with only necessary data. Arbitrary stride access capability with interleaved memories is described in previous research where the skewing scheme is changed at run time according to the currently used stride. This paper presents the improved schemes which are adapted to parallel memories. The proposed novel parallel memory implementation allows conflict free accesses with all the constant strides which has not been possible in prior application specific parallel memories. Moreover, the possible access locations are unrestricted and the accessed data element count equals to the number of memory modules. Timing and area estimates are given for Altera Stratix FPGA and 0.18 micrometer CMOS process with memory module count from 2 to 32. The FPGA results show 129 MHz clock frequency for a system with 16 memory modules when read and write latencies are 3 and 2 clock cycles, respectively. The complexity of the proposed system is shown to be a trade-off between application specific and highly configurable parallel memory system.     

Flash存储器的冗余实现

Flash存储器是在20世纪80年代末逐渐发展起来的一种新型半导体非挥发性存储器,它具有结构简单、高密度、低成本、高可靠性和系统的电可擦除性等优点,是当今半导体存储器市场中发展最为迅速的一种存储器。文章对Flash存储器的发展现状及发展趋势进行了介绍,分析了Flash存储器的工作机理;并针对Flash存储器是一种数据正确性非理想的器件,在使用中可能会有坏损单元,探讨了Flash存储器冗余技术的种类和实现方法。     

单电子存储器

介绍了单电子存储器的发展情况和几种单电子存储器的基本特性,并将库仑阻塞效应作为存储器工作的理论基础进行了讨论。随着传统存储器集成度的不断提高,每个存储单元的电子数目不断减少,并逐渐接近其极限,使传统存储器的发展面临困难。采用单电子存储器有望解决这个困难,它们通常具有单个量子点或者是多隧穿结结构,存储一个比特的信息只需要精确控制增加或者减少一定数目的电子就可以实现。单电子器件的工作通常只需要很少的电子甚至一个电子就可以实现,具有高速和低功耗的特点,因此可以实现信息超高密度存储。与单电子逻辑电路相比,单电子存储器更容易解决随机背景电荷涨落的问题,因此从实际应用的角度来看,单电子存储器的应用前景更为光明。     

高维量子态存储

量子通信网络主要由用于存储和操纵量子态的存储单元和联络存储单元之间的信息载体构成。光子是信息载体的最佳选择,存储单元可以由固态材料或气态原子组成。相对于二维空间,编码于一个高维空间的光子可以携带更大的信息量。若能够实现编码于高维空间的量子态存储,则在增大存储单元存储容量的同时,还可以提高网络的信道容量和传输效率,因而高维量子态的存储研究成为当前量子信息领域的热点领域。本文简要回顾了国内外在高维量子态存储方面进展,着重介绍了近期基于冷原子系综实现单光子条件下高维量子态存储的突破性进展,提出了构建高维量子网络需要解决的关键问题。     

基于高密度闪速存储器的研究和应用

主要介绍闪速存储器的技术分类,以及各类技术架构的特点和功能,简要对比了目前市场上各大存储器厂商的主要产品;并结合高分辨率数码相机实例分析了NAND型闪存K9W8G08的优缺点以及解决方案.