Exploiting electrothermal oscillations for identifying MOSFET thermal parameters

Electrothermal oscillations in electronic circuits are in general regarded as parasitic dynamic phenomena. This paper shows how these phenomena may be exploited to identify the value of thermal resistance and capacitance of the RC network modelling heat diffusion. Measurement of the period of oscillations and bifurcation analysis of the stability of the equilibrium point are two approaches that may possibly lead to a reasonable estimate of these parameters. In this paper, we present both methods applied to two specific MOSFET circuits. In particular, the oscillation period of a current-mirror circuit and bifurcation analysis of a simple one-MOSFET circuit are analysed in detail. For the bifurcation analysis approach, theory and experimental results are successfully compared to simulation in order to validate the proposed model.     

Design considerations for high-frequency crystal oscillators

The deleterious effects of crystal shunt capacitance and series resistance on the performance of series-mode oscillators are discussed. When the parasitic capacitance across the crystal significantly modifies the transconductance of the amplifying stage the circuits can become susceptible to a parasitic second mode of oscillation above the series-resonance frequency of the crystal. A simple model that can sufficiently describe such crystal oscillator circuits was developed and used to derive simple design equations that can accurately predict the behavior of these circuits. The design equations should be especially useful for a reliable design in cases when it is not practical to use an additional inductor to compensate for the parasitic shunt capacitance of the crystal. It is shown theoretically that the inclusion of this capacitance in the feedback path reduces the total effective capacitance in the tank circuit, which is tuned to the desired overtone frequency. This creates a second mode of oscillation frequency which is higher than the desired crystal resonance frequency. The ranges of loop-gain and tank resistance values that can prevent this parasitic mode of oscillations are derived. It is also shown that the useful loop gain for the desired oscillations to start is restricted to a similar region by the crystal shunt capacitance and series resistance     

Capacitive effects in IGBTs limiting their reliability under short circuit

The short-circuit oscillation mechanism in IGBTs is investigated in this paper by the aid of semiconductor device simulation tools. A 3.3-kV IGBT cell has been used for the simulations demonstrating that a single IGBT cell is able to oscillate together with the external circuit parasitic elements. The work presented here through both circuit and device analysis, confirms that the oscillations can be understood with focus on the device capacitive effects coming from the interaction between carrier concentration and the electric field. The paper also shows the 2-D effects during one oscillation cycle, revealing that the gate capacitance changes according with the shape of the electric field due to the charge distribution in the n-base. It has been identified that the time-varying capacitance leads to parametric oscillations together with the stray gate inductance, which limit the reliability of the IGBT.     

An Electronically Tunable Sinusoidal Oscillator Suitable for High Frequencies Operation Based on a Single Dual-Output Variable-Gain CCII

A novel sinusoidal oscillator, constructed from only one CCII with variable current gain, is presented and analyzed. The oscillator provides electronically tunable frequency, with good stability and low sensitivities, while variation of current gain does not affect the condition of oscillations. By the proposed circuit topology, the parasitic elements which exist at current conveyor terminals are absorbed by the external components and their action is diminished. Moreover, the parasitic poles of the current conveyor are taken into account and compensation technique and design criteria are applied, so that the oscillator can operate above 35 MHz.     

The roles of the surface and bulk of the semi-insulating substrate in low-frequency anomalies of GaAs integrated circuits

We investigate in detail two anomalies in metal-semiconductor field-effect transistors (MESFET) which are detrimental to their operation in a GaAs integrated circuit (IC). The first of these is side-gating and consists in a parasitic very-low-frequency transconductance between a MESFET and an isolated electrode or side gate sharing the same semi-insulating (SI) substrate. The second anomaly is kinetic and consists in a parasitic transient in the drain-source current following an abrupt change in drain-source voltage. The time constants of the transients are observed to be very sensitive to the side-gate electrode potential. The effects of different technological and operational parameters are studied. One surprising result is the very high sensitivity of side-gating to chemical wet and dry treatments and to dielectric encapsulation of the unprotected substrate surfaces. We also report low-frequency oscillations related to side-gating. Physical models are proposed and yield consistent interpretations of our experimental observations.     

延长分米波电视发射管使用寿命的探讨（上）

文章从原理上讨论了影响分米波电视发射管寿命的若干因素。并提出了若干延长寿命的建议：（１）正确的灯丝加热方法是行之有效的措施，经验证明：过分强调降低灯丝电压往往得到相反的效果。（２）必须有良好的冷却方式。（３）通过对帘栅电路的分析，说明对此电路必须作很好的处理以消除故障和防止寄生振荡。     

Dual-Band Platform Tolerant Antennas for Radio-Frequency Identification

A technique for tuning a single-element planar inverted F-antenna (PIFA) to provide a dual-band operation is introduced. The tuning is possible due to the particular impedance level typical to radio-frequency identification microchips. As the desired impedance level resides near the outer rim of the Smith chart, a single impedance locus may be arranged to pass the input impedance twice resulting in dual-band operation. The tuning of the impedance locus is based on the feed inductance and capacitive coupling at the open end of the patch. In this paper, also a discussion about the principles of platform tolerance of small antennas is provided. A design, circuit model, simulations, and measurement results of dual-band platform tolerant PIFAs are reported and discussed.     

使用大规模存储器电路的PEX技术研究

随着集成电路(IC)制造工艺向深亚微米逐渐深入,寄生参数对IC的性能影响越来越大,因此对寄生参数的提取及分析(后仿真)也就显得愈发重要。文章以寄生参数提取的原理及基本方法为引入,分析寄生RC参数产生机制和计算方法,并以含有大规模存储单元的IC设计为例,研究如何利用现有的提取工具解决提取效率的问题,提出了模块划分、重复利用、参数定位和反标配置等操作方案,重点分析基于calibre XRC的PEX在IC设计中遇到的问题,并结合实际情况给出合适的解决方案。     

Complex oscillations in a double-circuit self-oscillator built on a field-effect transistor on the basis of the inductive three-point circuit

The existence of irregular complex oscillations in a double-circuit self-oscillator built on a field-effect transistor on the basis of the inductive three-point circuit is revealed. The dynamics of the circuit model is analyzed by means of a computer simulation program for construction of the boundaries of the regions of complex oscillations existing in several parameter planes of the system and for determination of the parameters corresponding to the highest intensity of complex oscillations. The necessary conditions for excitation of complex oscillations are obtained in the form of restrictions imposed on the values of the so-called active and passive Q factors of the transistor drain circuit. The value of the allowable external load in the oscillating loop of the drain circuit is estimated from the viewpoint of excitation of complex oscillations.     

电子电路图的识图方法

介绍了在无线电电路图中比较重要的集成电路应用电路图和印制线路图的识图方法,并对集成电路应用电路图的功能、特点、电路分析方法以及印制线图的种类、功能、特点和识图技巧做了说明。对集成电路图识图和电子电路阅读过程中应注意的牢记电子元器件符号,加强检查以及区别焊完和未焊完接头等事项做了归纳,最后介绍了印制线路图的识图方法和识图的一些技巧。     

Reflection Charts Relating to Impedance Matching

A reflection chart is some grid of coordinates on which to plot an impedance locus over a frequency range. Taking as a reference a constant real impedance, one may construct contours of the reflection coefficient (or the related VSWR, reflection loss, etc.). The reference may be the wave impedance of a transmission line. This may be a line connecting radio equipment with an antenna or it may be a standard line used in measuring the impedance. The reflection chart in widest use is the so-called "Smith Chart" proposed by Philip H. Smith in 1939. It is one form of the hemisphere chart, which was proposed, also in 1939, by Philip S. Carter. Its properties, uses are described. It has some limitations. A reference value must be assigned, after which the shape of a locus depends on this value. Also, a locus is crowded toward the rim of the chart. A logarithmic reflection chart has recently been proposed by the author, which overcomes these limitations but loses some desirable features of the hemisphere chart.     

反激变压器高频寄生参数的仿真分析研究

在DC-DC变换器变压器寄生参数模型基础上,利用有限元仿真分析方法求解变压器寄生参数。结合电路仿真分析方法,通过研究不同的变压器绕制策略,分析了不同绕组策略对变压器寄生参数,以及对电路电压应力和噪声的影响。     

Forced oscillations in an oscillating circuit utilising nonlinear capacitance

This letter deals with forced oscillations in an oscillating circuit with nonlinear capacitance. The method in Reference 6 is used, which does not put limitations on the amplitude of the oscillations or on the degree of nonlinearity in the circuit. The resonance characteristic and the conditions for monostable and bistable régimes of the circuit oscillations are examined.     

精确区分器件和互连寄生电阻电容的方法研究

随着器件线宽的不断缩小,在集成电路仿真中互连线延迟所占的比重逐渐变大,而MOSFET延迟所占的比重慢慢减小,这就意味着互连的寄生电阻电容对延迟的影响越来越大.研究了如何区分并计算器件部分和互连部分的寄生电阻电容.其中区分本地互连寄生电阻电容和器件电阻电容是关键.以90 nm器件为例,通过提取不同部分的寄生电阻电容,对环形振荡器进行延迟仿真,得到了它们对延迟的影响.通过不同的测试结构达到精确计算器件寄生电阻电容的目的,最终实现了对电路的精确仿真.     

Large-signal computer simulations of the contact, circuit, and bias dependence of X-band transferred electron oscillators

We present a treatment synthesizing the roles of the contact and the circuit forX-band length transferred electron devices sustaining self-excited oscillations. The contact is modeled with specific cathode electric-field relations. The circuit is modeled with lumped elements. The scope of the simulation is relevant to both high-efficiency InP oscillations and the moderate-efficiency GaAs oscillations.     

人工电源网络阻抗高频特性及其校准精度研究

本文根据人工电源网络的原理图,建立了阻抗测量的高频寄生参数模型,并分析了适配器寄生参数以及各独立元件在电路中的作用。通过分析接地和金属板的两种基本串扰形式,建立人工电源网络相应的等效电路模型,运用MATLAB仿真软件仿真分析了两种模型下的寄生参数对阻抗的影响。仿真得到的随频率变化的曲线表明,寄生参数及其耦合关系对阻抗测量有重要影响。     

The effect of parasitic capacitances on the circuit speed of GaAs MESFET ring oscillators

Circuit parasitic capacitances for GaAs ring oscillators (RO's) were calculated and used for SPICE2 circuit simulation. The simulated delays agreed with the measured data to within ∼10 percent. The results indicate that the effect of the circuit parasitic capacitances are dominant in determining circuit speed for high-density IC's at the microwave frequency.     

Low-frequency stability of impatt-diode circuits

The maximum available stability of an impatt-diode circuit depends on the parasitic capacitance measured at the diode terminals. A formula is given relating the microwave characteristics of the circuit to the maximum parasitic capacitance compatible with freedom from spurious oscillation.     

Performance-driven circuit and layout co-optimization for deep-submicron analog circuits

The deep sub-micron (DSM) process nodes are increasingly marred by layout-dependent effects. The principal reason preventing layout synthesis during circuit design is the cost of edition, verification and extraction of the intermediate solutions repeatedly. This paper proposes a circuit and layout co-optimization scheme through a novel parasitic model-building scheme that exchanges information between the two flows. A placement-based parasitic estimation method to provide parasitic estimations to schematic optimization tools while retaining their efficiency. Extracted parasitics and simulated performance data are imparted into parasitic macro-devices and performance sensitivities. As proved by experimental results, the flexibility of the parasitic models bridges the efficiency and accuracy void between schematic and physical design optimization to ensure rapid DSM design closure.