5G LDPC码译码器实现

该文介绍了5G标准中LDPC码的特点,比较分析了各种译码算法的性能,提出了译码器实现的总体架构：将译码器分为高速译码器和低信噪比译码器。高速译码器适用于码率高、吞吐率要求高的情形,为译码器的主体;低信噪比译码器主要针对低码率、低信噪比下的高性能译码,处理一些极限情形下的通信,对吞吐率要求不高。分别对高速译码器和低信噪比译码器进行了设计实践,给出了FPGA综合结果和吞吐率分析结果。     

带复位的高性能译码器设计

译码器是寄存器文件中的关键部件.为了实现高性能的寄存器文件,结合寄存器文件的设计,实现了一款带复位的高性能译码器,并分析了这款译码器的性能和功能.设计中,使用了偏斜逻辑的设计方法,有效地提高了译码器的速度.同时,采用特殊的复位电路,可以精确地控制字线维持时间,降低功耗.在0.13μm工艺下对译码器进行模拟分析并与传统的译码器进行比较,结果表明,相对于传统静态译码器,该译码器的速度增加了43.24%,延时为210ps,相对于传统动态译码器,平均功耗降低了37.56%.     

数字集成电路讲座(8) 第五讲 编译码器

<正> 在数字电路系统中,编译码器的功能是将一种数码变换成另一种数码。编译码器的输出状态是其输入变量各种组合的结果。编译码器的输出既可操作或控制系统其它部分,也可驱动显示器,实现数字、符号的显示。 编译码器通常是一种组合电路,其工作状态的改变无需依赖时序脉冲。这里介绍的译码器分为数码译码器和显示译     

循环汉明码编译码器的设计与FPGA实现

分析了循环码的特性,提出一种循环汉明码编译码器的设计方案。编译码器中编码采用除法电路,译码采用梅吉特译码器,易于工程应用。对编译码器在FPGA上进行了实现,通过参数化设置,具有较高的码率,适用于(255,247)及其任意缩短码的循环汉明码,并给出了译码器的仿真和测试结果。结果表明:编译码器运行速率高、译码时延小,在Virtex-5芯片上,最高工作时钟频率大于270 MHz。在码组错误个数确定的系统应用中,可以有效降低误码率,一般可将误码率降低一个量级。实践表明,该设计具有很强的工程实用价值。     

5G LDPC码译码器实现

该文介绍了5G标准中LDPC码的特点，比较分析了各种译码算法的性能，提出了译码器实现的总体架构:将译码器分为高速译码器和低信噪比译码器。高速译码器适用于码率高、吞吐率要求高的情形，为译码器的主体；低信噪比译码器主要针对低码率、低信噪比下的高性能译码，处理一些极限情形下的通信，对吞吐率要求不高。分别对高速译码器和低信噪比译码器进行了设计实践，给出了FPGA综合结果和吞吐率分析结果。     

二进制译码器逻辑功能的Multisim仿真方案

介绍了用Multisim仿真软件分析二进制译码器工作过程的方法,即用Multisim仿真软件中字组产生器产生二进制译码器的使能控制信号和地址输入信号。字组产生器的字组内容反映二进制译码器输入端的不同输入情况,用Multisim中逻辑分析仪多踪同步显示二进制译码器的各个输入信号及输出信号波形,可直观描述二进制译码器的译码工作过程。该方法解决了二进制译码器的工作波形无法用电子实验仪器进行分析验证的问题。     

LDPC译码器信道似然比信息存储模块优化设计

以CCSDS(太空数据系统咨询委员会)标准中1/2码率的LDPC码为例,分析了低密度奇偶校验码(LDPC)译码算法的特点,提出了在译码器的FPGA实现中采用乒乓操作的设计方法,优化译码器信道似然比信息存储模块结构,交替接收两帧数据,使译码器不间断地工作,提高了硬件资源利用率,使译码器的吞吐量增加一倍.     

气象卫星数据传输中RS编译码器的设计

介绍了气象卫星数据传输中RS编码器及译码器的应用背景,同时给出了数据传输的主要技术要求,数据传输中采用的交错深度为4的RS编码器及译码器的设计原理。详细给出了实现编译码器所采用的FPGA的主要性能,编码及译码器的设计方法、实现框图、编程方法、仿真波形、结果及调试过程。     

（2,1,7）卷积码编译码器的FPGA实现

卷积码是一种重要的前向纠错信道编码方式,其纠错性能常常优于分组码,且（2,1,7）卷积码已应用于现代卫星通信系统中。Viterbi译码算法能最大限度地发挥卷积码的优异性能。这里采用Verilog HDL语言设计出（2,1,7）卷积码的编码器模块和基于Viterbi算法的译码器模块,译码器采用全并行结构,译码速度快。阐述了编译码器各模块的设计原理,并在ModelSim给出各模块的仿真测试结果。同时对译码器进行纠错性能测试,测试结果表明该Viterbi译码器有良好的纠错性能。     

CCSDS标准LDPC部分并行译码器实现

针对CCSDS标准中近地通信的LDPC码,为了提高准循环低密度奇偶校验（QC-LDPC）译码器的吞吐率和资源利用率,设计实现了一种低复杂度高速并行译码器。译码器整体采用流水线结构,通过改进校验节点与变量节点的更新方式,在不增加运算复杂度的情况下使信息处理所消耗的时间更短,压缩单次迭代所需时间,提高了译码器的吞吐量。以现场可编程门阵列（FPGA）作为实现平台,仿真并实现了基于归一化最小和算法的（8176,7154） LDPC译码器。结果表明,当译码器工作频率为200 MHz、迭代次数为10次的情况下,译码吞吐量可达到160 Mbit/s,满足大多数场景的应用需求。     

一种高速自适应Reed-Solomon译码结构及其VLSI优化实现

该文给出了一种自适应Reed-Solomon(RS) 译码器结构。该结构可以自适应地处理长度变化的截短码编码数据块,适合于高速译码处理。该结构使译码处理不受数据块间隙长短的约束,既可以处理独立的编码数据块也可以处理连续发送的编码数据块。另外本译码器结构可以保证输出数据块间隔信息的完整性,满足无线通信和以太网中特殊业务的要求。本文还基于该结构对RS(255,239)译码器予以实现,该译码器经过Synopsys综合工具综合并用TSMC 0.18 CMOS工艺实现,测试结果验证了该译码器的自适应功能和译码正确性,其端口处理速率可达1.6Gb/s。     

On general linear block code decoding using the sum-product iterative decoder

The sum-product iterative decoder, conventionally used for low-density parity-check (LDPC) codes, hold promise as a decoder for general linear block code decoding. However, the promise is only partly fulfilled because, as we show experimentally, the decoder performance degrades rapidly as a function of parity check matrix weight. Even in the case of decoder failure, however, we demonstrate that there is information present in the decoder output probabilities that can still help with the decoding problem.     

The TAR decoder-a bandpass Viterbi/FFT decoder for convolutionalencoded spread-spectrum signals

A new form of bandpass convolutional decoder termed the TAR decoder is presented. The decoder has as its basis the classic Viterbi algorithm, but uses a fast Fourier transform (FFT) in order to cope with a frequency offset, phase rotating, received signal. The TAR decoder also uses a two-dimensional (2-D) despread signal history array in addition to the usual path history registers. The advantage of the TAR decoder is that the decoder does not need to be preceded by a modem and is not subject to the problems of cycle slips. It can operate at negative input signal-to-noise ratio (SNR) values and is well suited to the decoding of low rate convolutional codes as may be used in code-division multiple-access (CDMA) systems. Symbol timing recovery is still required but this is straightforward in practical cases down to ≃-15 dB SNR     

FPGA implementation of low complexity LDPC iterative decoder

Low-density parity-check (LDPC) codes, proposed by Gallager, emerged as a class of codes which can yield very good performance on the additive white Gaussian noise channel as well as on the binary symmetric channel. LDPC codes have gained lots of importance due to their capacity achieving property and excellent performance in the noisy channel. Belief propagation (BP) algorithm and its approximations, most notably min-sum, are popular iterative decoding algorithms used for LDPC and turbo codes. The trade-off between the hardware complexity and the decoding throughput is a critical factor in the implementation of the practical decoder. This article presents introduction to LDPC codes and its various decoding algorithms followed by realisation of LDPC decoder by using simplified message passing algorithm and partially parallel decoder architecture. Simplified message passing algorithm has been proposed for trade-off between low decoding complexity and decoder performance. It greatly reduces the routing and check node complexity of the decoder. Partially parallel decoder architecture possesses high speed and reduced complexity. The improved design of the decoder possesses a maximum symbol throughput of 92.95 Mbps and a maximum of 18 decoding iterations. The article presents implementation of 9216 bits, rate-1/2, (3, 6) LDPC decoder on Xilinx XC3D3400A device from Spartan-3A DSP family.     

An artificial neural net Viterbi decoder

The Viterbi algorithm is a maximum likelihood means for decoding convolutional codes and has thus played an important role in applications ranging from satellite communications to cellular telephony. In the past, Viterbi decoders have usually been implemented using digital circuits. The speed of these digital decoders is directly related to the amount of parallelism in the design. As the constraint length of the code increases, parallelism becomes problematic due to the complexity of the decoder. In this paper an artificial neural network (ANN) Viterbi decoder is presented. The ANN decoder is significantly faster than comparable digital-only designs due to its fully parallel architecture. The fully parallel structure is obtained by implementing most of the Viterbi algorithm using analog neurons as opposed to digital circuits. Several modifications to the ANN decoder are considered, including an analog/digital hybrid design that results in an extremely fast and efficient decoder. The ANN decoder requires one-sixth the number of transistors required by the digital decoder. The connection weights of the ANN decoder are either +1 or -1, so weight considerations in the implementation are eliminated. This, together with the design's modularity and local connectivity, makes the ANN Viterbi decoder a natural fit for VLSI implementation. Simulation results are provided to show that the performance of the ANN decoder matches that of an ideal Viterbi decoder     

An evaluation of the systolic stack sequential decoder

The performance of a sequential stack decoder based on a new systolic priority queue is evaluated using extensive simulations over both memoryless Gaussian channels and Rayleigh fading channels. The results are used to determine interrelations between the decoder parameters, providing a simple way to design a systolic stack sequential decoder with an overall erasure probability approximately equal to the probability of a correct path overflow, while keeping the bit error rate of the decoder almost as low as that of the code. It is shown that this decoder circumvents some of the limitations inherent to usual stack decoders, while offering an increased decoding speed and being well suited for vlsi implementation.     

Twin-stack decoding of recursive systematic convolutional codes

We present a method for soft-in/soft-out sequential decoding of recursive systematic convolutional codes. The proposed decoder, the twin-stack decoder, is an extension of the well-known ZJ stack decoder, and it uses two stacks. The use of the two stacks lends itself to the generation of soft outputs, and the decoder is easily incorporated into the iterative “turbo” configuration. Under thresholded decoding, it is observed that the decoder is capable of achieving near-maximum a posteriori bit-error rate performance at moderate to high signal-to-noise ratios (SNRs). Also, in the iterative (turbo) configuration, at moderate SNRs (above 2.0 dB), the performance of the proposed decoder is within 1.5 dB of the BCJR algorithm for a 16-state, R=1/3, recursive code, but this difference narrows progressively at higher SNRs. The complexity of the decoder asymptotically decreases (with SNR) as 1/(number of states), providing a good tradeoff between computational burden and performance. The proposed decoder is also within 1.0 dB of other well-known suboptimal soft-out decoding techniques     

Universal decoding for frequency-selective fading channels

We address the problem of universal decoding in unknown frequency-selective fading channels, using an orthogonal frequency-division multiplexing (OFDM) signaling scheme. A block-fading model is adopted, where the bands' fading coefficients are unknown yet assumed constant throughout the block. Given a codebook, we seek a decoder independent of the channel parameters whose worst case performance relative to a maximum-likelihood (ML) decoder that knows the channel is optimal. Specifically, the decoder is selected from a family of quadratic decoders, and the optimal decoder is referred to as a quadratic minimax (QMM) decoder for that family. As the QMM decoder is generally difficult to find, a suboptimal QMM decoder is derived instead. Despite its suboptimality, the proposed decoder is shown to outperform the generalized likelihood ratio test (GLRT), which is commonly used when the channel is unknown, while maintaining a comparable complexity. The QMM decoder is also derived for the practical case where the fading coefficients are not entirely independent but rather satisfy some general constraints. Simulations verify the superiority of the proposed QMM decoder over the GLRT and over the practically used training sequence approach.     

Gear-Shift Decoding

This paper considers a class of iterative message-passing decoders for low-density parity-check codes in which the decoder can choose its decoding rule from a set of decoding algorithms at each iteration. Each available decoding algorithm may have different per-iteration computation time and performance. With an appropriate choice of algorithm at each iteration, overall decoding latency can be reduced significantly, compared with standard decoding methods. Such a decoder is called a gear-shift decoder because it changes its decoding rule (shifts gears) in order to guarantee both convergence and maximum decoding speed (minimum decoding latency). Using extrinsic information transfer charts, the problem of finding the optimum (minimum decoding latency) gear-shift decoder is formulated as a computationally tractable dynamic program. The optimum gear-shift decoder is proved to have a decoding threshold equal to or better than the best decoding threshold among those of the available algorithms. In addition to speeding up software decoder implementations, gear-shift decoding can be applied to optimize a pipelined hardware decoder, minimizing hardware cost for a given decoder throughput.     

Low-complexity maximum-likelihood detection of coded signals sentover finite-state Markov channels

We propose a decision-feedback decoder for coded signals transmitted over finite-state Markov channels. The decoder achieves maximum-likelihood sequence detection (in the absence of feedback errors) with very low complexity by exploiting previous bit decisions and the Markov structure of the channel. We also propose a similar decoder, the output-feedback decoder, that does not use previous bit decisions and therefore does not suffer from error propagation. The decoder performance is determined using a new sliding window analysis technique as well as by simulation. Both decoders exhibit excellent bit error rate performance with a relatively low complexity that is independent of the channel decorrelation time