Investigation of Ta2O5/SiO2/4H-SiC MIS capacitors

Tantalum pentoxide (Ta₂O₅) deposited by pulsed DC magnetron sputtering technique as the gate dielectric for 4H-SiC based metal-insulator-semiconductor (MIS) structure has been investigated. A rectifying current-voltage characteristic was observed, with the injection of current occurred when a positive DC bias was applied to the gate electrode with respect to the n type 4H-SiC substrate. This undesirable behavior is attributed to the relatively small band gap of Ta₂O₅ of around 4.3 eV, resulting in a small band offset between the 4H-SiC and Ta₂O₅. To overcome this problem, a thin thermal silicon oxide layer was introduced between Ta₂O₅ and 4H-SiC. This has substantially reduced the leakage current through the MIS structure. Further improvement was obtained by annealing the Ta₂O₅ at 900 °C in oxygen. The annealing has also reduced the effective charge in the dielectric film, as deduced from high frequency C-V measurements of the Ta₂O₅/SiO₂/4H-SiC capacitors.     

Comparative study of AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors with Al2O3 and HfO2 gate oxide

AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOSHFETs) with Al₂O₃ gate oxide which was deposited by atomic layer deposition (ALD) were fabricated and their performance was then compared with that of AlGaN/GaN MOSHFETs with HfO₂ gate oxide. The capacitance (C)-voltage (V) curve of the Al₂O₃/GaN MOS diodes showed a lower hysteresis and lower interface state density than the C-V curve of the HfO₂/GaN diodes, indicating better quality of the Al₂O₃/GaN interface. The saturation of drain current in the I_D-V_GS relation of the Al₂O₃ AlGaN/GaN MOSHFETs was not as pronounced as that of the HfO₂ AlGaN/GaN MOSHFETs. The gate leakage current of the Al₂O₃ MOSHFET was five to eight orders of magnitude smaller than that of the HfO₂ MOSHFETs.     

原子层沉积氧化铝薄膜对多晶太阳能电池表面钝化的影响

A stack of Al2O3/SiNx dual layer was applied for the back side surface passivation of p-type multi-crystalline silicon solar cells, with laser-opened line metal contacts, forming a local aluminum back surface field （local Al-BSF） structure. A slight amount of Al2O3, wrapping around to the front side of the wafer during the thermal atomic layer deposition process, was found to have a negative influence on cell performance. The different process flow was found to lead to a different cell performance, because of the Al2O3 wrapping around the front surface. The best cell performance, with an absolute efficiency gain of about 0.6% compared with the normal full Al-BSF structure solar cell, was achieved when the Al2O3 layer was deposited after the front surface of the wafer had been covered by a SiNx layer. We discuss the possible reasons for this phenomenon, and propose three explanations as the Ag paste, being hindered from firing through the front passivation layer, degraded the SiNx passivation effect and the Al2O3 induced an inversion effect on the front surface. Characterization methods like internal quantum efficiency and contact resistance scanning were used to assist our understanding of the underlying mechanisms.     

Enhanced efficiency and stability of polymer solar cells with TiO2 nanoparticles buffer layer

TiO₂ sols synthesized with a facile solution-based method were used as a buffer layer between the active layer and the cathode Al in conventional structure polymer solar cells (PSCs). Using transmission electron microscopy (TEM), selected area electron diffraction (SAED), X-ray diffraction (XRD) and atomic force microscopy (AFM), the morphological and crystallographic properties of synthesized TiO₂ nanoparticles (TiO₂ NPs) as well as the buffer layer were studied in detail. It was observed that by increasing H₂O in the process of peptization both the crystallinity and particle size of TiO₂ NPs were enhanced, while the particles in sol showed a narrower size distribution conformed by dynamic light scattering. Inserting TiO₂ NPs as a buffer layer in conventional structure PSCs, both the power conversion efficiency (PCE) and stability were improved dramatically. PSCs based on the structure of ITO/PEDOT:PSS/P3HT:PCBM/TiO₂ NPs/Al showed the short-circuit current (J_sc) of 12.83 mA/cm² and the PCE of 4.24%, which were improved by 31% and 37%, respectively comparing with the reference devices without a TiO₂ buffer layer. The stability measurement showed that PSC devices with a TiO₂ NPs buffer layer could retain 80% of the original PCEs after exposed in air for 200 h, much better than the devices without such a buffer layer. The effect can be attributed to the protection by the buffer layer against oxygen and H₂O diffusion into the active layers. The observations indicate that TiO₂ NPs synthesized by facile solution-based method have great potential applications in PSCs, especially for large-area printed PSCs.     

Atomic-layer-deposited Al2O3 and HfO2 on GaN: A comparative study on interfaces and electrical characteristics

Al₂O₃, HfO₂, and composite HfO₂/Al₂O₃ films were deposited on n-type GaN using atomic layer deposition (ALD). The interfacial layer of GaON and HfON was observed between HfO₂ and GaN, whereas the absence of an interfacial layer at Al₂O₃/GaN was confirmed using X-ray photoelectron spectroscopy and transmission electron microscopy. The dielectric constants of Al₂O₃, HfO₂, and composite HfO₂/Al₂O₃ calculated from the C-V measurement are 9, 16.5, and 13.8, respectively. The Al₂O₃ employed as a template in the composite structure has suppressed the interfacial layer formation during the subsequent ALD-HfO₂ and effectively reduced the gate leakage current. While the dielectric constant of the composite HfO₂/Al₂O₃ film is lower than that of HfO₂, the composite structure provides sharp oxide/GaN interface without interfacial layer, leading to better electrical properties.     

Study of nitrogen impact on VFB-EOT roll-off by varying interfacial SiO2 thickness

Flat band voltage (V_FB) roll-off in long channel devices at thin equivalent oxide thickness (EOT) is studied on SiO₂/nitrided-HfSiO stacks. V_FB increases when SiO₂ interfacial layer thickness decreases, and charges pumping (CP) frequency sweep analysis shows higher trap density near Si/SiO₂ interface. Based on this observation, an atomic diffusion model is introduced. Higher concentration of nitrogen atom in the HfSiO(N) layer diffuses to the Si/SiO₂ interface through the SiO₂ layer in thinner SiO₂ device, and accumulates near Si/SiO₂ interface which can introduce higher density of interfacial traps. Lifetime extracted from negative bias temperature instability (NBTI), and mobility are also degraded in thinner SiO₂ devices due to the higher interfacial trap density.The V_FB roll-off can be improved by lowering nitrogen concentration in the HfSiO(N) layer from optimizing plasma nitridation pressure, decreasing post deposition anneal temperature, or using defect absorbing layer on the high-k oxide.     

Charge trapping and interface characteristics in normally-off Al2O3/GaN-MOSFETs

Normally-off GaN-MOSFETs with Al₂O₃ gate dielectric have been fabricated and characterized. The Al₂O₃ layer is deposited by ALD and annealed under various temperatures. The saturation drain current of 330 mA/mm and the maximum transconductance of 32 mS/mm in the saturation region are not significantly modified after annealing. The subthreshold slope and the low-field mobility value are improved from 642 to 347 mV/dec and from 50 to 55 cm² V⁻¹ s⁻¹, respectively. The I_D-V_G curve shows hysteresis due to oxide trapped charge in the Al₂O₃ before annealing. The amount of hysteresis reduces with the increase of annealing temperature up to 750 °C. The Al₂O₃ layer starts to crystallize at a temperature of 850 °C and its insulating property deteriorates.     

Efficient electron-blocking layer-free planar heterojunction perovskite solar cells with a high open-circuit voltage

Perovskite solar cells (PSCs) with a simple device structure are particularly attractive due to their low cost and convenient fabrication process. Herein, highly efficient, electron-blocking layer (EBL)-free planar heterojunction (PHJ) PSCs with a structure of ITO/CH₃NH₃PbI₃/PCBM/Al were fabricated via low-temperature, solution-processed method. The power conversion efficiency (PCE) of over 11% was achieved in EBL-free PHJ-PSCs, which is closed to the value of PSC devices with the PEDOT:PSS as the EBL. It is impressed that the open-circuit voltage (V_oc) up to 1.06 V, an average value of 1.0 V for 43 devices, was obtained in EBL-free PHJ-PSCs. The electrochemical impedance spectroscopy (EIS) results suggested that the high PCE and V_oc are attributed to the relatively large recombination resistance and low contact resistance in EBL-free PHJ-PSCs. The solution-processed, EBL-free PHJ structure paves a boulevard for fabricating high-efficiency and low-cost PSCs.     

Electroluminescence of SrAl2O4:Eu phosphor

The SrAl₂O₄:Eu²⁺ phosphor powders have been synthesized by sol-gel process. Electroluminescent (EL) properties of the SrAl₂O₄:Eu²⁺ phosphor were investigated using a convenient thick film device. Green light emitting at a peak of 508 nm was obtained when driven by sine alternating current (AC). The color coordinate of the emission was x=0.148 and y=0.635. Luminance-voltage and afterglow characteristics of the SrAl₂O₄:Eu²⁺ EL devices were studied. The results show that SrAl₂O₄:Eu²⁺ can be used as green phosphor for EL displays.     

Efficient and stable inverted polymer solar cells using TiO2 nanoparticles and analysized by Mott-Schottky capacitance

The performance of both inverted and conventional polymer solar cells (PSCs) were examined with a low-temperature, solution-processed synthesized TiO₂ nanoparticles (TiO₂ NPs) as the electron extraction layer. The performance of inverted PSCs based on P3HT:PCBM bulk-heterojunction with a TiO₂ NPs layer was dramatically improved and the highest power conversion efficiency (PCE) of 4.56% was achieved via 24 h exposure in air, which is one of the highest PCEs for P3HT:PCBM bulk-heterojunction PSCs using TiO₂ as electron extraction layer. Meanwhile, the performance of inverted PSCs was superior to regular PSCs. Mott-Schottky capacitance analysis was carried out for both inverted and regular PSCs to obtain the built-in potential, the depletion width, as well as the doping level of the active layer, which all support the performance improvement of PSCs devices with inverted structure. In addition, inverted PSCs show excellent stability in air without encapsulation. The PCE can retain 87% of its original values after 400 h exposure in air, which is much better than that of regular PSCs. The results indicate that solution-processed TiO₂ NPs shows great potential applications in the fabrication of highly efficient and stable inverted PSCs as well as large-area, flexible printed PSCs.     

MOS devices with tetragonal ZrO2 as gate dielectric formed by annealing ZrO2/Ge/ZrO2 laminate

A Ge-stabilized tetragonal ZrO₂ (t-ZrO₂) film with permittivity (κ) of 36.2 was formed by depositing a ZrO₂/Ge/ZrO₂ laminate and a subsequent annealing at 600 °C, which is a more reliable approach to control the incorporated amount of Ge in ZrO₂. On Si substrates, with thin SiON as an interfacial layer, the SiON/t-ZrO₂ gate stack with equivalent oxide thickness (EOT) of 1.75 nm shows tiny amount of hysteresis and negligible frequency dispersion in capacitance-voltage (C-V) characteristics. By passivating leaky channels derived from grain boundaries with NH₃ plasma, good leakage current of 4.8 × 10⁻⁸ A/cm² at V_g = V_fb − 1 V is achieved and desirable reliability confirmed by positive bias temperature instability (PBTI) test is also obtained.     

Influence of post deposition annealing on Y2O3-gated GaAs MOS capacitors and their reliability issues

The feasibility of employing yttrium oxide (Y₂O₃) as high-k gate dielectrics for GaAs metal-oxide-semiconductor (MOS) devices has been investigated. MOS capacitors were fabricated using RF-sputtered deposited Y₂O₃ films on NH₄OH treated n-GaAs substrate. Indeed high-k (Y₂O₃)/GaAs MOS capacitors exhibiting fairly good electrical characteristics, for instance, especially low leakage current density, low hysteresis and allowable density of interface states, have been achieved. The effects of several annealing treatments on Y₂O₃-gated GaAs MOS capacitors have been investigated in order to optimize the process conditions. A decrease in accumulation capacitance (C_acc) following PDA effectively increases the equivalent oxide thickness (EOT), which is predicted to be correlated with the growth and continuous increase in the physical thickness of a lower-k inter-layer sandwiched between Y₂O₃ and GaAs. However, leakage currents and interface trap densities are reduced with higher values of annealing temperature. The variation of current density with an equivalent oxide thickness (EOT) has also been investigated.     

Effective formation of interface controlled Y2O3 thin film on Si(1 0 0) in a metal-(ferroelectric)-insulator-semiconductor structure

Yttrium was deposited on the chemical oxide of Si and annealed under vacuum to control the interface for the formation of Y₂O₃ as an insulating barrier to construct a metal-ferroelectric-insulator-semiconductor structure. Two different pre-annealing temperatures of 600 and 700 °C were chosen to investigate the effect of the interface state formed after the pre-annealing step on the successive formation of Y₂O₃ insulator and Nd₂Ti₂O₇ (NTO) ferroelectric layer through annealing under an oxygen atmosphere at 800 °C. Pre-anneal treatments of Y-metal/chemical-SiO₂/Si at 600 and 700 °C induced a formation of Y₂O₃ and Y-silicate, respectively. The difference in the pre-anneal temperature induced almost no change in the electrical properties of the Y₂O₃/interface/Si system, but degraded properties were observed in the NTO/Y₂O₃/interface/Si system pre-annealed at 600 °C when compared with the sample pre-annealed at 700 °C. C-V characteristics of the NTO/Y₂O₃/Si structured system showed a clockwise direction of hysteresis, and this gap could be used as a memory window for a ferroelectric-gate. A smaller hysteric gap and electrical breakdown values were observed in the NTO/Y₂O₃/Si system pre-annealed at 600 °C, and this was due to an unintentional distribution of the applied field from the presence of an interfacial layer containing Y-silicate and SiO₂ phases.     

High-k HfO2-Ta2O5 mixed layers: Electrical characteristics and mechanisms of conductivity

Electrical properties of mixed HfO₂-Ta₂O₅ films (10;15 nm) deposited by rf sputtering on Si have been studied from the view point of their applications as high-k layers, by standard capacitance-voltage and temperature dependent current-voltage characteristics. The effect of HfO₂ addition to the Ta₂O₅ is thickness dependent and the thicker layers exhibit advantages over the pure Ta₂O₅ (higher dielectric constant, enhanced charge storage density and improved interface quality). The process of HfO₂ and Ta₂O₅ mixing introduces negative oxide charge, tends to creates shallow bulk traps and modifies the dominant conduction mechanisms in the stack capacitors as compared to the Ta₂O₅-based one (a contribution of tunneling processes through traps located below the conduction band of mixed layers to the leakage current in the HfO₂-Ta₂O₅ stacks is observed). The traps involved in both Poole-Frenkel and tunneling processes are identified.     

Co3O4/Fe2O3异质结复合材料的制备及其紫外光光电探测性能

分别采用旋涂法和水热法在FTO衬底上制备Co₃O₄种子层和Co₃O₄薄膜,再在Co₃O₄薄膜上水热生长Fe₂O₃纳米棒,获得了高质量的Co₃O₄/Fe₂O₃异质结复合材料。通过改变Fe₂O₃前驱体溶液浓度来改变异质结复合材料中Fe₂O₃组分的含量。结果表明,Fe₂O₃纳米棒覆盖在呈网状结构的Co₃O₄薄膜上,随着Fe₂O₃前驱体溶液浓度即Fe₂O₃组分含量的增加,Co₃O₄/Fe₂O₃异质结复合材料对紫外光的响应逐渐增强,当Fe₂O₃前驱体溶液浓度为0.015mol/L时,异质结复合材料有着很好的光电稳定性,并表现出较高的响应率(12.5mA/W)和探测率(4.4×10¹⁰Jones)。     

Fabrication and electrical characteristics of ultrathin (HfO2)x(SiO2)1−x films by surface sol-gel method and reaction-anneal treatment

Hafnium oxide (HfO₂) films were deposited on Si substrates with a pre-grown oxide layer using hafnium chloride (HfCl₄) source by surface sol-gel process, then ultrathin (HfO₂)_x(SiO₂)_1−x films were fabricated due to the reaction of SiO₂ layer with HfO₂ under the appropriate reaction-anneal treatment. The observation of high-resolution transmission electron microscopy indicates that the ultrathin films show amorphous nature. X-ray photoelectron spectroscopy analyses reveal that surface sol-gel derived ultrathin films are Hf-Si-O alloy instead of HfO₂ and pre-grown SiO₂ layer, and the composition was Hf_0.52Si_0.48O₂ under 500 °C reaction-anneal. The lowest equivalent oxide thickness (EOT) value of 0.9 nm of film annealed at 500 °C has been obtained with small flatband voltage of −0.31 V. The experimental results indicate that a simple and feasible solution route to fabricate (HfO₂)_x(SiO₂)_1−x composite films has been developed by means of combination of surface sol-gel and reaction-anneal treatment.     

Effects of surface passivation during atomic layer deposition of Al2O3 on In0.53Ga0.47As substrates

In this work we investigate the effect of different III-V surface passivation strategies during atomic layer deposition of Al₂O₃. X-ray photoelectron spectroscopy indicates that bare As-decapped and sulfur passivated In_0.53Ga_0.47As present residual oxides on the surface just before the beginning of the Al₂O₃ deposition while the insertion of a Ge interface passivation layer results in an almost oxide free Ge/III-V interface. The study of the initial growth regimes, by means of in situ spectroscopic ellipsometry, shows that the growth of Al₂O₃ on Ge leads to an enhanced initial growth accompanied by the formation of Ge-O-Al species thus affecting the final electrical properties of the stack. Alternatively, deposition on decapped and S-passivated In_0.53Ga_0.47As results in a more controlled growth process. The sulfur passivation leads to a better electrical response of the capacitor that can be associated to a lower oxide/semiconductor interface trap density.     

Materials and interfaces issues in pentacene/PTCDI-C8 ambipolar organic field-effect transistors with solution-based gelatin dielectric

Gelatin is a natural protein, which works well as the gate dielectric for pentacene/N,N-dioctyl-3,4,9,10-perylene tetracarboxylic diimide (PTCDI-C₈) ambipolar organic field-effect transistors (OFETs) in air ambient and in vacuum. An aqueous solution process was used to form the gelatin gate dielectric film on poly(ethylene terephthalate) (PET) by spin-coating and subsequent casting. Pentacene morphology and interface roughness are two major factors affecting the electron and hole field-effect mobility (μ_FE) values of pentacene/PTCDI-C₈ ambipolar OFETs in vacuum and in air ambient. In contrast, water absorption in gelatin has higher contribution to the electron and hole μ_FE values in air ambient. The ambipolar performance of pentacene/PTCDI-C₈ ambipolar OFETs depends on their layer sequence. For example, when PTCDI-C₈ is deposited onto pentacene, i.e. in the structure of PTCDI-C₈/pentacene, unbalanced ambipolar characteristics appear. In contrast, better ambipolar performance occurs in the structure of pentacene/PTCDI-C₈. The optimum ambipolar characteristics with electron μ_FE of 0.85 cm² V⁻¹ s⁻¹ and hole μ_FE of 0.95 cm² V⁻¹ s⁻¹ occurs at the condition of pentacene (40 nm)/PTCDI-C₈ (40 nm). Surprisingly, water absorption plays a crucial role in ambipolar performance. The device performance changes tremendously in pentacene/PTCDI-C₈ ambipolar OFETs due to the removal of water out of gelatin in vacuum. The optimum ambipolar characteristics with electron μ_FE of 0.008 cm² V⁻¹ s⁻¹ and hole μ_FE of 0.007 cm² V⁻¹ s⁻¹ occurs at the condition of pentacene (65 nm)/PTCDI-C₈ (40 nm). The roles of layer sequence, relative layer thickness, and water absorption are proposed to explain the ambipolar performance.     

Infrared spectroscopy and X-ray diffraction studies on the crystallographic evolution of La2O3 films upon annealing

Rare earth oxides (REOs) have lately received extensive attention in relation to the continuous scaling down of non-volatile memories (NVMs). In particular, La₂O₃ films are promising for integration into future NVMs because they are expected to crystallize above 400 °C in the hexagonal phase (h-La₂O₃) which has a higher κ value than the cubic phase (c-La₂O₃) in which most of REOs crystallize. In this work, La₂O₃ films are grown on Si by atomic layer deposition using La(C₅H₅)₃ and H₂O. Within the framework of the h-La₂O₃ formation, we systematically study the crystallographic evolution of La₂O₃ films versus annealing temperature (200-600 °C) by Fourier transform infrared spectroscopy (FTIR) and grazing incidence X-ray diffraction (GIXRD). As-grown films are chemically unstable in air since a rapid transformation into monoclinic LaO(OH) and hexagonal La(OH)₃ occurs. Vacuum annealing of sufficiently thick (>100 nm) La(OH)₃ layers induces clear changes in FTIR and GIXRD spectra: c-La₂O₃ gradually forms in the 300-500 °C range while annealing at 600 °C generates h-La₂O₃ which exhibits, as inferred from our electrical data, a desirable κ ∼ 27. A quick transformation from h-La₂O₃ into La(OH)₃ occurs due to H₂O absorption, indicating that the annealed films are chemically unstable. This study extends our recent work on the h-La₂O₃ formation.     

Analysis of interface trap density of metal-oxide-semiconductor devices with Pr2O3 gate dielectric using conductance method

In this study, the interface trap density of metal-oxide-semiconductor (MOS) devices with Pr₂O₃ gate dielectric deposited on Si is determined by using a conductance method. In order to determine the exact value of the interface trap density, the series resistance is estimated directly from the impedance spectra of the MOS devices. Subsequently, the dispersion characteristics are numerically analyzed on the basis of a statistical model. Lastly, the process-dependent interface trap density of Pr₂O₃ is evaluated. It is concluded that high-pressure annealing and a superior quality interfacial SiO₂ layer are of crucial importance for achieving a sufficiently low interface trap density.