A single-chip CMOS PCM codec with filters

A complete PCM codec using charge redistribution and switched-capacitor techniques will be described. The device is implemented in a two-level polysilicon CMOS technology using 23.4 mm/SUP 2/ of active area. It features all the required transmission filters needed for telephony, two on-chip voltage references, TTL compatible digital interfaces, and low-power dissipation. The architecture of the chip allows asynchronous operation, a variable PCM data rate from 100 kbit/s to 4.096 Mbit/s, /spl mu//A law operation via pin selection, and gain selection at either of two levels in each direction.     

An integrated single-chip PCM voice codec with filters

A new single-chip monolithic compressed/expanded (companded) pulse-code modulation (PCM) coder/decoder (codec) is described. The associated switched-capacitor filters and reference voltage are also implemented on the chip, using a silicon-gate CMOS process. The DAC and ADC used incorporate a binary-weighted capacitor array and a string of equal-valued resistors. The circuit operators from a/spl plusmn/5 V supply and it consumes 65 mW in normal operation and 5 mW in the power-down condition. The implementation of the critical circuits in CMOS technology is discussed in detail.     

A single-chip CMOS PCM codec

Describes a single-chip full duplex per channel PCM codec implemented in a metal gate CMOS process. An 8-bit companding DAC, a novel autozeroed analog subsystem, and a 3.5-MHz frame interface control logic comprise the 175/spl times/195-mil integrated circuit. The DAC is implemented with matched n channel devices and utilizes redundancy and feedback to achieve the required accuracy. The analog subsystem contains two sample and hold circuits, autozeroing circuitry, CMOS amplifiers, and a fast CMOS comparator.     

A single-chip CMOS filter/codec

A second generation LSI codec has been implemented. In this chip, switched-capacitor filters, a charge redistribution encoder and decoder, voltage references, a signaling logic circuit, and all necessary functions for voice-PCM conversion are integrated. The authors describe the codec and summarizes its characteristics.     

A single-chip adaptive DPCM video codec

A differential pulse-code modulation (DPCM) video codec with two-dimensional intrafield prediction and adaptive quantizer is presented. An approach for the arithmetic implementation of the DPCM structure and the design of a test chip, fabricated in a 1.5 μm CMOS technology, is described. This is the first VLSI realization of a DPCM codec with adaptive quantizer. For the test chip transmitter or receiver mode, application as part of a three-dimensional interframe codec and processing of luminance or chrominance signals are optional. A line buffer and ten different quantizer characteristics are realized on-chip. Correct operation has been verified up to 26 MHz     

A PCM voice codec with on-chip filters

Describes a monolithic NMOS coder/decoder (codec) with associated CCD transversal minimum phase filters which has been successfully implemented. The codec operates by charge redistribution in a binary-weighted capacitor array, with a resistor chain to define individual steps. The experimental performance compares well with PCM codecs implemented with discrete components.     

MOS switched-capacitor filters

In the past several years, much progress has been made in bringing the economies of integrated-circuit technology to bear on the realization of voiceband frequency selective filters. This paper will review one approach to this problem, the use of switched-capacitor techniques. The paper emphasizes the practical aspects of switched-capacitor filter design under the constraints imposed by MOS integrated-circuit technology. The basic operation of switched-capacitor filters is reviewed, followed by a discussion of the properties of the various circuit building blocks in MOS technology. Finally, a summary of several filter organizations which appear to be well suited to switched-capacitor implementation is presented.     

Testable switched-capacitor filters

A design-for-testability (DFT) methodology for switched-capacitor (SC) filters is presented, based on an architecture using some additional circuitry and providing extra capabilities for both off- and online test. A programmable biquad is used for on-chip comparison of the transfer functions for every filter stage. Test area overhead consists of the programmable biquad, a set of switches, and a finite-sequential-machine (FSM) control part. The design and implementation of an example filter are included to assess the potential usefulness of this approach     

Ladder-simulation switched-capacitor filters with inductor loops

In ladder-simulation switched-capacitor filters, offset voltages of the op-amps can cause the output simulating inductor currents to build up if the LC prototype contains an inductor loop. This problem is eliminated by a novel technique where the sum of inductor currents flowing into each node is simulated by one op-amp output.     

New switched-capacitor ladder filters

A method is described and implemented for the derivation of switched-capacitor discrete-time filters from analogue passive filters of the ladder doubly terminated kind. The method is based on linear transformation active (LTA) synthesis, and yields some very interesting results.     

Offset-compensated switched-capacitor leapfrog filters

Offset-compensated SC leapfrog filters can be realised as shown in the letter. The filters are parasitic-insensitive and the switches are controlled by a 3-phase clock. A 5th-order lowpass filter is given as an example.     

Pseudopower in switched-capacitor filters

The concepts of pseudopower, pseudopassivity, and pseudolosslessness are introduced in connection with switched-capacitor filters employing voltage invertor switches. With such concepts the verification of the low sensitivity and stability properties is straightforward.     

A single-chip I/SUP 2/L PCM codec

A single chip CPCM codec is described. This chip, which is fabricated in bipolar technology, meets all the D3 specifications. The circuit is capable of operating in a fully asynchronous transmit and receive mode, and provisions are made for zero code suppression and A/B signaling. Even with this signaling, the codec achieves a worst case idle channel noise of 13 dBrnC0.     

Parasitics-insensitive switched-capacitor ladder filters

A simple method for designing parasitics-insensitive switched-capacitor (s.c.) ladder filters is described. The response of the s.c. filter is related to that of a continuous-time prototype circuit by the bilinear z-transform.     

A single-chip MPEG-2 codec based on customizable media embedded processor

A single-chip MPEG-2 MP@ML codec, integrating 3.8M gates on a 72-mm/sup 2/ die, is described. The codec employs a heterogeneous multiprocessor architecture in which six microprocessors with the same instruction set but different customization execute specific tasks such as video and audio concurrently. The microprocessor, developed for digital media processing, provides various extensions such as a very-long-instruction-word coprocessor, digital signal processor instructions, and hardware engines. Making full use of the extensions and optimizing the architecture of each microprocessor based upon the nature of specific tasks, the chip can execute not only MPEG-2 MP@ML video/audio/system encoding and decoding concurrently, but also MPEG-2 MP@HL decoding in real time.     

Stability test for switched-capacitor filters

A general stability test is described which may be employed in the analysis of all switched-capacitor filters of the lossless discrete integrator (LDI) type.     

CMOS high-frequency switched-capacitor filters fortelecommunication applications

A digitally programmable high-frequency switched-capacitor filter for use in a switched digital video (SDV/VDSL) link is described. The highest available clock frequency in the system is 51.84 MHz (f_s =2f_clock=103.68 MHz for double sampling) while the three desired low-pass corner frequencies (f_c) are 8,12, and 20 MHz. The double-sampling, bilinear, elliptic, fifth-order switched-capacitor filter meets the desired -40-dB attenuation at 1.3 f _c, and -30 dB at 1.25 f_c. For the 12-MHz corner frequency setting, given the 2V_pp differential input, the measured worst case total harmonic distortion is -60 dB, with signal-to-noise ratio of 54 dB. The analog power dissipation is 125 mW from a 5-V power supply. The test results indicate that the clock frequency can be increased to 73 MHz without any ill effects. More measurements verify that an all-digital CMOS implementation, utilizing metal-sandwich capacitors, performs as well as the special-layer analog capacitors implementation, with a small reduction in the absolute corner frequencies. The prototype IC's are fabricated in a 0.35-μm 5-V (0.48 μm drawn) CMOS process     

Improving the testability of switched-capacitor filters

A design-for-test methodology for SC filters is presented, based on an architecture using some additional circuitry and providing extra capabilities for both off- and on-line tests. The approach uses a comparison (voting) mechanism to indicate whether or not two copies of a filter element (a biquad, for instance) have a similar response during their actual operation. The design and implementation of a few filter examples are included to assess the potential usefulness of this new approach.     

Power-supply rejection in differential switched-capacitor filters

The principal motivation of using a fully differential configuration is to reduce power supply coupling. For this reason, an analysis of some of the mechanisms associated with this effect and the usefulness of some forms of common mode feedback are discussed. Experimental results obtained from a CMOS integrated circuit realization are also included. The circuit achieves 50 dB of power supply rejection ratio across the passband.     

Improving the testability of switched-capacitor filters

A design-for-test methodology for SC filters is presented, based on an architecture using some additional circuitry and providing extra capabilities for both off-and on-line tests. The approach uses a comparison (voting) mechanism to indicate whether or not two copies of a filter element (a biquad, for instance) have a similar response during their actual operation. The design and implementation of a few filter examples are included to assess the potential usefulness of this new approach.