基于STM32处理器的存储器IAP编程技术

本文针对存储器程序更新的问题,提出一种基于STM32的IAP程序更新方法-通过STM32的FSMC接口实现NOR Flash访问,并以JFM-F512K32芯片为例,说明FSMC接口的配置方法,通过IAP程序运行实现Flash存储器数据的更新.该设计成功实现Flash程序的自动更新功能,操作简单、速度快、正确率高.     

基于TMS320C6713及AM29LV800B的上电自举设计

基于DSP的系统设计中,由于部分DSP内部无非易失性存储器,为了保证该系统设计掉电时程序不丢失,因此必须外部扩展ROM或Flash用于存储数据.以TMS320C6713型浮点DSP和AM29LV800B型Flash存储器为例,阐述了上电自举的硬件设计,JTAG程序加载,上电自举过程,Flash的擦除及烧写,链接命令文件和编写,并详细说明各部分相互联系及作用.     

基于TMS320C6713及AM29LV800B的上电自举设计

基于DSP的系统设计中．由于部分DSP内部无非易失性存储器,为了保证该系统设计掉电时程序不丢失,因此必须外部扩展ROM或Flash用于存储数据。以TMS320C6713型浮点DSP和AM29LV800B型Flash存储器为例,阐述了上电自举的硬件设计,JTAG程序加载,上电自举过程,Flash的擦除及烧写,链接命令文件和编写,并详细说明各部分相互联系及作用。     

单片机实用技术讲座(2) 第一讲 单片机的基本结构与工作原理(中)

<正> 存储器结构和地址空间 89C51单片机系列的存储器采用的是哈佛(Har-vard)结构,即将程序存储器和数据存储器截然分开,程序存储器和数据存储器各有自己的寻址方式、寻址空间和控制系统。 这种结构对于单片机“面向控制”的实际应用极为方便、有利。在89C51单片机中不仅在片内驻留了一定容量的程序存储器和数据存储器及众多的特殊功能寄存器,而且还具有极强的外部存储器扩展能力,寻址范围分别可达64K字节,寻址和操作简单方便。图5为89C51单片机存储器映像图。     

一种新型SoC启动方案的设计与实现

传统片上系统（System on Chip,SoC）启动方案中通常采用ROM（Read-Only Memory）或Flash等非易失性存储器来存储程序并引导内核启动,但是ROM在制造之后不能更改数据内容;Flash等可擦写存储器则需要专用的擦写接口,且制造费用高昂。针对以上问题,设计了SoC启动控制器和引导加载程序,通过读取片外Micro SD（Secure Digital）卡中存储的程序,提出了一种直接从片内SRAM（Static Random Access Memory）中启动SoC的新型方案,从速度、面积和成本等方面折中考虑,给出了设计过程并进行验证分析。结果表明,所设计的SoC启动控制器完成数据加载并直接从SRAM引导SoC启动。该方案采用SMIC 0.13 μm CMOS 1P6M工艺流片验证测试,在800 ms内将64 kB数据加载到片上SRAM并成功引导SoC启动,系统工作频率32 MHz,SoC面积为2 mm2,其中启动控制器面积仅为0.3 mm2。相比于传统片内ROM/Flash启动方式和片外Flash加载方式,所提方案无需使用片内ROM或Flash IP核,面积减少了20%,IO管脚减少了6个,为SoC提供了一种新型的低成本启动方案。     

存储器类型综述及DDR接口设计的实现(下)

用FPGA器件实现DDR存储器接口现在我们已经详细说明了一个典型的DDR接口的要求,我们能够转而在一个FPGA中实现这一DDR存储器接口了。存储器读的实现在这里我们将检查一下设计一个读接口要遇到的挑战以及可获取的解决方案。在存储器读时FPGA遇到的挑战:1.DQS-DQ的对齐-在狭窄的数据有效窗口中,DQS必须重新对齐(移相90度)来捕捉数据。系统歪斜和多个DQ线之间的歪斜必须得到处理。2.数据多路合成和多路分解-在读期间,DDR输入数据必须多路分解成两个SDR流。时钟域转换-数据经多路分解后,它必须和一个公共时钟边沿对齐,然后和一个…     

Flash M25P64驱动开发与应用

M25P64是一款8 M字节串行Flash存储器.利用其诸多特性可为大容量数据存储提供一种解决方案.介绍了M25P64的主要特点,工作原理,驱动程序的开发以及典型应用实例.在其典型应用实例中,基于SPI接口的数据存储系统能简单有效稳定运行.     

一种Flash安全存储控制器的设计与实现

针对当前对Flash存储器中敏感数据的安全存储需求,设计实现了一种Flash安全存储控制器。通过数据加密技术和访问地址加扰技术保证存储数据的安全,并建立了一种分区访问控制机制,实现了不同等级用户的访问控制。对该存储控制器设计进行验证和分析,结果表明,设计的Flash安全存储控制器在保证Flash访问速率的基础上,实现了对Flash存储器的硬件级安全防护和分区访问控制,方法不仅可行,而且具有较强的实用性。     

浅谈单片机的存储器结构

<正> 典型微型计算机的存储器都是采用冯诺依曼结构,也称普林斯顿结构,即存放程序指令的存储器——程序存储器和存放数据的存储器——数据存储器采取统一的地址编码结构。 1976年英特尔公司推出的MCS-48系列单片机,采用了将程序存储器与数据存储器分开的地址编码结构,即哈佛结构,此后MCS-51系列单片机也采用了这种结构,而1983年英特尔公司推出的MCS-96系列单片机,又采用了传统微机     

基于闪存阵列的高速存储方法

针对单片Flash存储速度过慢的情况,提出了一种利用DMA(直接存储器访问)技术和流水线Flash存储来实现高速存储的方法.该方法通过AVR单片机和CPLD控制产生DMA和Flash片选时序不经过处理器,直接往Flash里写一页数据,在第一片Flash进行数据编程而无法对其进行其他操作时,继续往下一片Flash里写一页...     

On-chip error correcting techniques for new-generation flash memories

In new-generation flash memories, issues such as disturbs and data retention become more and more critical as a consequence of reduced cell size and decreased oxide thickness. Furthermore, the progressive increase in the cell count within a single die tends to decrease device reliability. In particular, reliability issues turn out to be more critical in multilevel (ML) flash memories, due to the reduced spacing between adjacent programmed levels. It is therefore deemed that the use of on-chip error correction codes (ECCs) will gain widespread acceptance in large-capacity flash memories. ECCs for flash memories must have very fast and compact encoding/decoding circuitry so as to have a minimum impact on memory access time. The area penalty due to check cells must also be minimized. Moreover, specific codes must be developed for ML storage. This paper presents error control coding techniques and schemes for new-generation flash memories, focusing on ML devices. The basic concepts of error control coding are reviewed, and the on-chip ECC design procedure is analyzed. Dedicated codes such as polyvalent ECCs, able to correct data stored in ML memories working at a variable number of bits per cell, and bit-layer organized ECCs are described.     

Memory on the move

The author describes how, competing for the US $ 11 billion portable electronic device memory market are several venerable but revitalized memory systems as well as new storage technologies: flash memory cards; PC memory cards; and small disk drives. Flashers, a relatively young technology contain one or more nonvolatile solid-state memory chips. They have no moving parts and retain data in the absence of power. Like these, but an industry unto itself, is the PC Card; now almost 10 years old, the business-card-sized memory and application device is heavily used to add functions to mobile computers. The spinners are a completely upgraded group of rotating disk drive systems based on both magnetic and optical technologies     

通用存储装置设计

提出了一种多接口的通用存储装置,该装置具有良好的NAND Flash管理.它向用户提供线性的NAND Flash地址空间,使用户可以对NAND Flash进行透明的访问,而不需要深入了解NAND Flash的具体技术细节.同时,该装置具有多种接口,可以在多种不同接口的电子产品中作为数据存储介质使用.这样,不同接口的电子产品不用通过额外的设计或者转接器就可以使用本装置,给电子设备的设计和使用带来便利.     

Anticipatory I/O Management for Clustered Flash Translation Layer in NAND Flash Memory

Recently, NAND flash memory has emerged as a next generation storage device because it has several advantages, such as low power consumption, shock resistance, and so on. However, it is necessary to use a flash translation layer (FTL) to intermediate between NAND flash memory and conventional file systems because of the unique hardware characteristics of flash memory. This paper proposes a new clustered FTL (CFTL) that uses clustered hash tables and a two‐level software cache technique. The CFTL can anticipate consecutive addresses from the host because the clustered hash table uses the locality of reference in a large address space. It also adaptively switches logical addresses to physical addresses in the flash memory by using block mapping, page mapping, and a two‐level software cache technique. Furthermore, anticipatory I/O management using continuity counters and a prefetch scheme enables fast address translation. Experimental results show that the proposed address translation mechanism for CFTL provides better performance in address translation and memory space usage than the well‐known NAND FTL (NFTL) and adaptive FTL (AFTL).     

Flash memory complexity

Driven by the demand for more versatile personal electronic devices such as cellular phones and handheld computers, flash memory has advanced rapidly to higher volume density and performance levels. Today, semiconductor manufacturers find a growing opportunity for more advanced flash memories delivered either as standalone flash devices; embedded as cores with logic in single-chip devices; or packaged as stacked dice with microcontrollers, logic, or static RAM. For flash manufacturers, however, success in these highly competitive markets requires tight control over the cost of test, despite rising device complexity. As flash memory grows in size, speed, and complexity, manufacturers are seeking more cost-effective, single-insertion test solutions capable of addressing resulting test challenges. With the development of new test architectures, manufacturers can more efficiently address emerging flash complexity using cost-effective, next-generation test platforms.     

FTL algorithms for NAND-type flash memories

Flash memory is being rapidly deployed as data storage for embedded devices such as PDAs, MP3 players, mobile phones and digital cameras due to its low electronic power, non-volatile storage, high performance, physical stability and portability. The most prominent characteristic of flash memory is that prewritten data can only be dynamically updated via the time consuming erase operation. Furthermore, every block in flash memory has a limited program/erase cycle. In order to manage these issues, the flash memory controller can be integrated with a software module called the flash translation layer (FTL). This paper surveys the state-of-art FTL algorithms. The FTL algorithms can be classified by the complexity of the algorithms: basic and advance. Furthermore, they can be classified by their corresponding tasks: performance enhancement and durability enhancement. The FTL algorithms corresponding to each classification are further broken down into various schemes depending on the methods they adopt. This paper also provides the information of hardware features of flash memory for FTL programmers.     

一种基于闪存物理镜像的FAT文件系统重组方法

文件系统重组是闪存设备取证研究进行数据恢复的主要手段.传统的文件系统重组方法需要同时获取闪存设备在同一时刻的逻辑镜像和物理镜像,该条件在取证实践中常常难以满足,故提出一种仅依赖闪存物理镜像重组文件分配表(FAT)文件系统的方法.在引入统计分析法从物理镜像中提取逻辑地址字段和页状态字段的基础上,给出利用最新页状态值准确重组闪存设备最新FAT文件系统镜像的算法.最后以MTK6229闪存设备物理镜像的FAT文件系统重组过程为例,验证上述重组算法及相关方法是正确的.     

3D NAND闪存数据保持力与初始状态依赖性研究

数据保持力是NAND闪存重要的可靠性指标,本文基于用户在使用模式下,通过设计测试方法,研究了电荷捕获型3D NAND闪存初始阈值电压-2V至3V的范围内数据保持力特性.结果表明初始状态为编程态时,可以有效降低NAND闪存高温数据保留后的误码率,特别是随着擦写次数的增加,不同初始状态下电荷捕获型3D NAND闪存数据保持力差异更加明显,结论表明闪存最适宜存放的状态为0-1V,电荷捕获型3D NAND闪存器件应避免长期处于深擦除状态.并基于不同初始状态闪存高温数据保留后的数据保持力特性不同的现象进行了建模和演示,通过设计实验验证,机理解释模型符合实验结果.该研究可为电荷捕获型3D NAND闪存器件的长期存放状态提供理论参考.     

Employing vertical dielectric layers to improve the operation performance of flash memory devices

A number of new device structures have been reported recently to improve the operation performance of flash memory. In this work, a novel flash device with a vertical dielectric layer in the depletion region is proposed through simulation approach. The simulation results show that the employment of a vertical dielectric layer in the depletion region can improve the operation performance of flash memory. The improvement can be attributed to a lower potential in the central region of device channel and the increase of the potential drop in the channel direction near drain junction. Thus, this proposed vertical dielectric layer increases the electrical field of the channel and thus the probability and the momentum of electron injection. The operation characteristics of the flash device with a vertical dielectric layer in the depletion region of source and drain are superior to those without. In addition, it is found that a vertical dielectric layer with lower dielectric constant can enhance the operation performance of flash device even more.     

An overview of logic architectures inside flash memory devices

In the past few years, the complexity of logic functions and architectures inside a flash memory device has grown in order to face the need for more complex system interfaces and to manage the increased amount of stored data. In this paper, an overview of these developments will be given. The paper is divided into sections describing areas where logic circuits play a key role: program/erase algorithms handling and user interface, redundancy management for yield enhancement, error correction codes to enhance reliability, and burst and page mode access control to enhance read bandwidth.