Accurate statistical process variation analysis for 0.25-μm CMOSwith advanced TCAD methodology

Effects of statistical process variation on the 0.25-μm CMOS performance have been accurately characterized by using a new calibrated TCAD methodology. To conduct the variation analysis, a series of TCAD simulations was conducted on the basis of DoE (design of experiments) with optimum variable transformations, which resulted in RSF's (response surface functions) for threshold voltage (V_th) and saturation drain current (I_ds). A new global calibration of the RSF model based on experimental data gives excellent accuracy within 0.02 V error in V_th and 3% error in I_ds. Using calibrated RSF, statistical process variation effects on the device characteristics have been quantitatively evaluated for each process recipe. It is found that variation of the gate-oxide formation process shows the most significant effect on the NMOS ΔI_ds in the production process. Furthermore we have designed an optimized 0.25-μm CMOS process and device on the basis of the RSF and also predicted the process variation effects on the device performance. It is shown that the V_th and I_ds variations of the 0.25-μm CMOS exhibit less than 10% I_ds variation in the production level process, which is similar to the value of 0.35-μm CMOS experimental data. Additional TCAD simulations for MOS model parameter generation of the 0.25-μm device was also conducted to allow circuit-designers to use predictive worst case circuit design parameters before experimental chip fabrication     

A new 0.25-μm recessed-channel MOSFET with selectivelyhalo-doped channel and deep graded source/drain

To improve the performance and reliability of deep submicron MOS devices, a gate-recessed MOSFET (GR-MOSFET), which has a selectively halo-doped recessed channel and a deep graded source/drain formed without counterdoping, is proposed. The GR-MOS structure, which adopts a new doping concept, eliminates the tradeoff between drain-induced barrier lowering (DIBL) and hot-carrier effect, which are important to deep submicron device design. It also reduces the V_T lowering effect and the lateral electric field at the drain. A 0.25-μm GR-MOSFET with a 10-nm gate oxide has exhibited 15% higher transconductance and 10% increased saturation current at V_D=V _G=3.3 V, 1 V higher BV_DSS, and six times less substrate current compared with an LDD-MOSFET of the same device dimensions     

Short-channel effect improved by lateral channel-engineering indeep-submicronmeter MOSFET's

The normal and reverse short-channel effect of LDD MOSFET's with lateral channel-engineering (pocket or halo implant) has been investigated. An analytical model is developed which can predict V_th as a function of L_eff, V_DS, V_BS, and pocket parameters down to 0.1-μm channel length. The new model shows that the V_th roll-up component due to pocket implant has an exponential dependence on channel length and is determined roughly by (N_p)^¼L_p. The validity of the model is verified by both experimental data and two-dimensional (2-D) numerical simulation. On the basis of the model, a methodology to optimize the minimum channel length L_min is presented. The theoretical optimal pocket implant performance is to achieve an L_min approximately 55~60% that of a uniform-channel MOSFET without pocket implant, which is a significant (over one technology generation) improvement. The process design window of pocket implant is analyzed. The design tradeoff between the improvement of short-channel immunity and the other device electrical performance is also discussed     

Modeling statistical dopant fluctuations in MOS transistors

The impact of statistical dopant fluctuations on the threshold voltage V_T and device performance of silicon MOSFET's is investigated by means of analytical and numerical modeling. A new analytical model describing dopant fluctuations in the active device area enables the derivation of the standard deviation, σV_T , of the threshold voltage distribution for arbitrary channel doping profiles. Using the MINIMOS device simulator to extend the analytical approach, it is found that σV_T, can be properly derived from two-dimensional (2-D) or three-dimensional (3-D) simulations using a relatively coarse simulation grid. Evaluating the threshold voltage shift arising from dopant fluctuations, on the other hand, calls for full 3-D simulations with a numerical grid that is sufficiently refined to represent the discrete nature of the dopant distribution. The average V_T-shift is found to be positive for long, narrow devices, and negative for short, wide devices. The fast 2-D MINIMOS modeling of dopant fluctuations enables an extensive statistical analysis of the intrinsic spreading in a large set of compact model parameters for state-of-the-art CMOS technology. It is predicted that V_T-variations due to dopant fluctuations become unacceptably large in CMOS generations of 0.18 μm and beyond when the present scaling scenarios are pursued. Parameter variations can be drastically reduced by using alternative device designs with ground-plane channel profiles     

A floating-body charge monitoring technique for partially depleted SOI technology

This paper presents a floating-body charge monitoring technique, which does not require the use of body contacts on the device being monitored. A charge monitor is placed along side with the circuit that is susceptible to the floating-body effects in partially depleted (PD) SOI CMOS circuits. It mimics the circuit topology and operating history of a concerned circuit, specifically the worst-case body voltage of the critical device(s) under consideration. The monitoring is achieved by intentionally triggering a parasitic bipolar current pulse and setting the a state recording latch, which subsequently activates the speed recovering circuitry that compensates the loss of performance at critical circuit nets due to the presence of parasitic bipolar current. Implementation examples are given and described. This technique restores performance and improves timing robustness of the MUX-type and SRAM bit line circuits by minimizing the delay degradation or variation from parasitic bipolar currents.     

Electrical characteristics of0°/±45°/90°-orientation CMOSFET with source/drainfabricated by various ion-implantation methods

Electrical characteristics of 0°/±45°/90°-orientation 0.5-μm CMOSFETs with source/drain regions fabricated by three ion-implantation methods are discussed. For asymmetrical one-sided 7°-implantation method, large-device-orientation dependent fluctuation and asymmetry were observed in (saturation drain current I_D and maximum substrate current I_B of both n- and p-MOSFETs/threshold voltage V_T of p-MOSFETs) and (I_D of n-MOSFETs/I _B of both n- and p-MOSFETs), respectively. Almost comparable characteristics were obtained for n-MOSFETs fabricated by symmetrical 0°-implantation and 7°×4-implantation methods. However, I _D difference in p-MOSFETs between 0°/90°- and ±45°-orientation devices, which may be affected by intraplanar anisotropy of hole drift velocity, was observed independently of the ion-implantation method     

High-performance 0.07-μm CMOS with 9.5-ps gate delay and 150 GHzfT

We report room-temperature 0.07-μm CMOS inverter delays of 13.6 ps at 1.5 V and 9.5 ps at 2.5 V for an SOI substrate; 16 ps at 1.5 V and 12 ps at 2.5 V for a bulk substrate. This is the first room-temperature sub-10 ps inverter ring oscillator delay ever reported. PFETs with very high drive current and reduction in parasitic resistances and capacitances for both NFETs and PFETs, realized by careful thermal budget optimization, contribute to the fast device speed. Moreover, the fast inverter delay was achieved without compromising the device short-channel characteristics. At V_dd=1.5 V and I_off ~2.5 nA/μm, minimum L_eff is about 0.085 μm for NFETs and 0.068 μm for PFETs. PFET I_on is 360 μA/μm, which is the highest value ever reported at comparable V_dd and I_off. The SOI MOSFET has about one order of magnitude higher I_off than a bulk MOSFET due to the floating-body effect. At around 0.07 μm L_eff, the NFET cut-off frequencies are 150 GHz for SOI and 135 GHz for bulk. These performance figures suggest that subtenth-micron CMOS is ready for multi-gigahertz digital circuits, and has good potential for RF and microwave applications     

On “effective channel length” in 0.1-μm MOSFETs

The conventional, 1-D definition of “effective channel length” (L_eff) is examined in light of the spatial dependence of channel sheet resistance in 0.1-μm MOSFETs calculated from a 2-D device model. For short-channel devices, the sheet resistance deviates significantly from the uniform, long-channel behavior that L _eff in general is different from the “metallurgical channel length”, L_met. While geometrical (charge-sharing) effects tend to make L_eff slightly shorter than L_met, lateral source-drain doping gradients, especially when coupled with retrograde channel doping, can make L_eff substantially longer than L_met. The latter might help explain the apparent “excess” short channel effect often observed in 0.1-μm CMOS devices     

0.1-μm p+-GaAs gate HJFET's fabricated using two-stepdry-etching and selective MOMBE growth techniques

This paper reports the first successful fabrication of high-performance, 0.1-μm p⁺-gate pseudomorphic heterojunction-FET's (HJFET's). By introducing the two-step dry-etching technique which compensates for the poor dry-etching resistance of PMMA, 0.1-μm or less gate-openings with a high aspect-ratio of 3.5 in SiO ₂ film are achieved. In addition, by using the gate electrode filling technique with selective MOMBE p⁺-GaAs growth, 0.1-μm voidless p⁺-GaAs gate electrodes with a high aspect-ratio are achieved for the first time. The fabrication technology leads to a reduction of external gate fringing capacitance (Ce^ext _f) in a T-shaped gate-structure and an improvement in gate turn-on voltage. The fabricated 0.1-μm, T-shaped, p⁺-gate n-Al_0.2Ga_0.8As/In_0.25Ga_0.75 As HJFET exhibits a high gate turn-on voltage (V_f) of about 0.9 V, and a good gm_max of 435 mS/mm. Also, an excellent microwave performance of f_T=121 GHz and f_max =144 GHz is achieved due to the C^ext_f reduction. The technology and device show great promise for future high-speed applications, such as in power devices, MMIC's, and digital IC's     

Pre-silicon parameter generation methodology using BSIM3 forcircuit performance-oriented device optimization

We present a physical parameter extraction methodology for BSIM3v3 to generate accurate pre-silicon parameters (parameters created before device fabrication). Using this method, the parameters of the 0.20-μm process device can be generated from a 0.25-μm technology with 5% accuracy in a few minutes. We applied this method in optimizing the devices of our microprocessor in the early stages of design     

Thermionic-emission-based barrier height analysis for preciseestimation of charge handling capacity in CCD registers

In designing charge-coupled device (CCD) image sensors, it is essential to be able to estimate charge handling capacity. Because electrons have thermal energy, storing electrons in a well in a CCD register requires a sufficient potential barrier height to keep them from overflowing. As the quantity of electrons in a well depends on the barrier height, knowledge of this height is indispensable for precise estimation of the charge handling capacity. The authors have derived an expression describing the barrier height on the basis of thermionic emission, assuming current coefficient I₀ and well capacitance C. We derived the current coefficient I₀ and well capacitance C with computer simulations and from the results estimate the magnitude of the barrier height for a typical Vertical-CCD (V-CCD) structure. We have also examined barrier height dependence on structural parameters. Finally, we determined the barrier heights experimentally, and our results support the values obtained in the simulation     

Trapped charge modulation: a new cause of instability inAlGaAs/InGaAs pseudomorphic HEMT's

A new degradation mechanism of PM-HEMT's subsequent to hot electron stress tests or high temperature storage tests is presented. A noticeable increase in drain-to-source current, I_DS, is observed after the tests. We show that this I_DS variation is slowly recoverable and is correlated with the presence of deep levels in the device. Stress tests cause a variation of trapped charge. Trapping of holes created by impact-ionization and/or thermally stimulated electron detrapping induce a variation of the net negative trapped charge, leading to a decrease in the threshold voltage, V_T and a consequent increase in I_DS. The correlation between g _mΔV_T and ΔI_DS clearly demonstrates that the variation of trapped charge induced by hot electron tests is localized under the gate     

A CMOS bandgap reference circuit with sub-1-V operation

This paper proposes a CMOS bandgap reference (BGR) circuit, which can successfully operate with sub-1-V supply, In the conventional BGR circuit, the output voltage V_ref is the sum of the built-in voltage of the diode V_f and the thermal voltage V_T of kT/q multiplied by a constant. Therefore, V_ref is about 1.25 V, which limits a low supply-voltage operation below 1 V. Conversely, in the proposed BGR circuit, V_ref has been converted from the sum of two currents; one is proportional to V_f and the other is proportional to V_T. An experimental BGR circuit, which is simply composed of a CMOS op-amp, diodes, and resistors, has been fabricated in a conventional 0.4-μm flash memory process. Measured V_ref is 518±15 mV (3σ) for 23 samples on the same wafer at 27-125°C     

Characteristics of GaAsSb single-quantum-well-lasers emitting near1.3 μm

We report data on GaAsSb single-quantum-well lasers grown on GaAs substrates. Room temperature pulsed emission at 1.275 μm in a 1250-μm-long device has been observed. Minimum threshold current densities of 535 A/cm² were measured in 2000-μm-long lasers. We also measured internal losses of 2-5 cm^-1, internal quantum efficiencies of 30%-38% and characteristic temperatures T₀ of 67°C-77°C. From these parameters, a gain constant G₀ of 1660 cm^-1 and a transparency current density J_tr of 134 A/cm² were calculated. The results indicate the potential for fabricating 1.3-μm vertical-cavity surface-emitting lasers from these materials     

High-frequency characterization of sub-0.25-μm fully depletedsilicon-on-insulator MOSFETs

A cutoff frequency, f_T, of 85 GHz was measured on a fully-depleted silicon-on-insulator (FDSOI) n-MOSFET with a gate length of 0.15 μm. The p-MOSFET with 0.22-μm gate length has an f_T of 42 GHz. The high-frequency equivalent circuits were derived from scattering parameters for MOSFETs with various gate lengths. The effects of gate length and other device parameters on the performance of FDSOI MOSFETs at RF are discussed     

Microwave performance of AlInAs-GaInAs HEMTs with 0.2- and0.1-μm gate length

The millimeter-wave performance is reported for Al_0.48In_0.52As-Ga_0.47In_0.53 As high-electron-mobility transistors (HEMTs) with 0.2-μm and 0.1-μm-long gates on material grown by molecular-beam epitaxy on semi-insulating InP substrates. Devices of 50-μm width exhibited extrinsic transconductances of 800 and 1080 mS/mm, respectively. External f_T (maximum frequency of oscillation) of 120 and 135 GHz, respectively, were measured. A maximum f_T of 170 GHz was obtained from a 0.1×200-μm² device. A minimum noise figure of 0.8 dB and associated gain of 8.7 dB were obtained from a single-stage amplifier at frequencies near 63 GHz     

Characteristics including electron velocity overshoot for0.1-μm-gate-length GaAs SAINT MESFET's

Short-channel effects, substrate leakage current, and average electron velocity are investigated for 0.1-μm-gate-length GaAs MESFETs fabricated using the SAINT (self-aligned implantation for n⁺-layer technology) process. The threshold-voltage shift was scaled by the aspect ratio of the channel thickness to the gate length ( a/L_g). The substrate leakage current in a sub-quarter-micrometer MESFET is completely suppressed by the buried p layers and shallow n⁺-layers. The average electron velocity for 0.1- to 0.2-μm-gate-length FETs is estimated to be 3×10⁶ cm/s from the analysis of intrinsic FET parameters. This high value indicates electron velocity overshoot. Moreover, a very high f_T of 93.1 GHz has been attained by the 0.1-μm SAINT MESFET     

Submicron transferred-substrate heterojunction bipolar transistors

We report submicron transferred-substrate AlInAs/GaInAs heterojunction bipolar transistors (HBT's). Devices with 0.4-μm emitter and 0.4-μm collector widths have 17.5 dB unilateral gain at 110 GHz. Extrapolating at -20 dB/decade, the power gain cutoff frequency f_max is 820 GHz. The high f_max, results from the scaling of HBT's junction widths, from elimination of collector series resistance through the use of a Schottky collector contact, and from partial screening of the collector-base capacitance by the collector space charge     

Effects of silicon layer properties on device reliability for0.1-μm SOI n-MOSFET design strategies

We employ an advanced simulation method to investigate the effects of silicon layer properties on hot-electron-induced reliability for two 0.1-μm SOI n-MOSFET design strategies. The simulation approach features a Monte Carlo device simulator in conjunction with commercially available process and device simulators. The two channel designs are: 1) a lightly-doped (10¹⁶ cm^-3) channel and 2) a heavily-doped (10¹⁸ cm^-3) channel. For each design, the silicon layer thicknesses (T_Si) of 30, 60, and 90 nm are considered. The devices are biased under low-voltage conditions where the drain voltage is considerably less than the Si/SiO₂ barrier height for electron injection. A comparative analysis of the Monte Carlo simulation results shows that an increase in T_Si results in decreasing hot electron injection into the back oxide in both device designs. However, electron injection into the front oxide exhibits opposite trends of increasing injection for the heavily-doped channel design and decreasing injection for the lightly-doped channel design. These important trends are attributed to highly two-dimensional electric field and current density distributions. Simulations also show that the lightly-doped channel design is about three times more reliable for thick silicon layers. However, as the silicon layer is thinned to 30 nm, the heavily-doped channel design becomes about 10% more reliable instead     

Self-aligned bottom-gate submicrometer-channel-length a-Si-:Hthin-film transistors

Fully self-aligned bottom-gate thin-film transistors (TFTs) fabricated by using a back substrate exposure technique combined with a metal lift-off process are discussed. Ohmic contact to the sources and drains is accomplished by a 40-nm-thick layer of phosphorous-doped microcrystalline silicon. Devices with channel lengths ranging from 0.4 to 12 μm are processed with overlap dimensions between the gate and the source and the gate and the drain ranging from 0.0 to 1.0 μm. Analysis of the conductance data in the linear voltage regime reveals a parasitic drain-to-channel and source-to-channel resistance that is 14% of the channel resistance for a 10-μm device and 140% for a 1-μm device. Thus, increase in the device speed caused by reducing the channel length does not follow expected behavior. A similar situation exists in the nonlinear regime. The on-current of the devices starts to saturate below channel lengths of 2 μm. Current on/off ratios taken at V_d=5 V and V_G=15 V and 0 V, respectively, are approximately 1×10⁶ for the 1- and 12-μm-long devices. The on/off ratio is reduced to 1×10⁵ for the 0.4-μm device