共查询到18条相似文献,搜索用时 120 毫秒
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为了解决内部结构日益复杂的片上网络系统故障测试的问题,在研究3×3 2D-Mesh体系结构的NoC系统、边界扫描测试技术和资源节点故障类型的基础上,以FPGA为核心器件设计边界扫描测试系统。完成了数据采集、频率计、放大器、SRAM、IEEE1500 Wrapper等资源节点电路以及资源节点边界扫描链路的接口电路设计,并利用测试软件、信号发生器、万用表和数字示波器,通过边界扫描链路完成对整个硬件设计的测试。测试结果表明该设计性能稳定,为研究NoC系统的边界扫描测试技术提供了硬件平台。 相似文献
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基于边界扫描的板级互连测试模型研究 总被引:1,自引:1,他引:0
主要研究边界扫描技术在电路板互连测试中的应用,对互连测试的故障模型和测试方法进行优化.根据电路板制造故障的具体成因和分布情况,对基于边界扫描的板级互连测试模型进行扩展.提出以元器件焊点故障作为基本参考点,增加了网络两端发生不同故障的情况,从而总结出新的故障模型,并给出了针对新故障模型的测试方案.基于新的故障模型的测试可以更加全面地发现电路板的潜在问题,避免在生产测试中因为故障的漏判而反复维修,从而提高生产的效率. 相似文献
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分析了混合信号边界扫描测试的工作机制对测试系统的功能需求,实现了符合IEEE1149.4标准的混合信号边界扫描测试系统。仿真和测试实践表明,该测试系统具有对系统级、PCB级和芯片级电路进行简单互连测试、差分测试和参数测试等功能,结构简单、携带方便、工作可靠。 相似文献
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M.H. Tehranipour S.M. Fakhraie Z. Navabi M.R. Movahedin 《Journal of Electronic Testing》2004,20(2):155-168
We have introduced a low-cost at-speed BIST architecture that enables conventional microprocessors and DSP cores to test their functional blocks and embedded SRAMs in system-on-a-chip architectures using their existing hardware and software resources. To accommodate our proposed new test methodology, minor modifications should be applied to base processor within its test phase. That is, we modify the controller to interpret some of the instructions differently only within the initial test mode. In this paper, we have proposed a fuctional self-test methodology that is deterministic in nature. In our proposed architecture, a self test program called BIST Program is stored in an embedded ROM as a vehicle for applying tests. We first start with testing processor core using our proposed architedture. Once the testing of the processor core is completed, this core is used to test the embedded SRAMs. A test algorithm which utilizes a mixture of existing memory testing techniques and covers all important memory faults is presented in this paper. The proposed memory test algorithm covers 100% of the faults under the fault model plus a data retention test. The hardware overhead in the proposed architecture is shown to be negligible. This architecture is implemented on UTS-DSP (University of Tehran and Iran Communicaton Industries (SAMA)) IC which has been designed in VLSI Circuits and Systems Laboratory. 相似文献
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A custom-designed silicon-based 50-GHz interconnect is integrated for packaging demonstrations of broadband optoelectronic (OE) applications in silicon optical microbench technology. The half-shielded (or partially shielded) 0.5-cm interconnect has 25-dB isolation and 0.9-dB transmission loss over 50 GHz. When implemented in this packaged architecture, the nature of the interconnect minimizes coupling and eliminates the need for an external test fixture that is prevalent in a more conventional approach. The interconnect is further demonstrated in a multiport electrical package to illustrate the potential of this architecture up to 40-Gb data rates, and the resulting package has insertion loss less than 5 dB at 50 GHz. 相似文献
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A New Algorithm for the Selection of Control Cells in Boundary-Scan Interconnect Test 总被引:1,自引:0,他引:1
This paper presents an algorithm for the generation of the values to be loaded in the control cells of a Boundary-Scan (BS) chain during an interconnect test. The algorithm selects several groups of control cells while avoiding that two or more drivers excite the same net at the same time, allowing every net to be active for every test vector and testing every driver after the execution of the overall test process. It allows for 100% detection of short, open, stuck-at and driver transition faults on fully controllable and observable BS nets on virtually any BS board. In fact, only two minor requirements are imposed: (1) the sets of nets affected by two different control cells must be disjoint or one of them must be included in the other; (2) every net of a set affected by a control cell must have the same number of drivers. In addition, the algorithm can be implemented very easily, avoiding the need to explore all the possible combinations of values to be loaded in the control cells. 相似文献
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The speed of VLSI chips is increasingly limited by signal delay in long interconnect lines. A simple analysis shows that major speed improvements are possible when using current-mode rather than conventional voltage-mode signal transporting techniques. The key to this approach is the use of low-resistance current-signal circuits to drastically reduce the impedance level and the voltage swings on long interconnect lines. As an example, a simple four-transistor current-sense amplifier for fast CMOS SRAMs is proposed. The circuit presents a virtual short circuit to the bit lines, thus reducing the sensing delay, which is rendered practically insensitive to the bit-line capacitance. In addition, the virtual short circuit ensures equal bit-line voltages, thus eliminating the need for bit-line equalization during a read access 相似文献
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P. Gogna E. Suarez M. Lingalugari J. Chandy E. Heller E.-S. Hasaneen F.-C. Jain 《Journal of Electronic Materials》2013,42(11):3337-3343
This paper describes novel multibit static random-access memories (SRAMs) implemented using four-channel spatial wavefunction switched field-effect transistors (SWS FETs) with Ge quantum wells and ZnSSe barriers. A two-bit SRAM cell consists of two back-to-back connected four-channel SWS FETs, where each SWS FET serves as a quaternary inverter. This architecture results in a reduction of the field-effect transistor (FET) count by 75% and data interconnect density by 50%. The designed two-bit SRAM cell is simulated using Berkeley short-channel insulated-gate field-effect transistor equivalent-channel models (for 25-nm FETs). In addition, the binary interface logic and conversion circuitry are designed to integrate the SWS SRAM technology. Our motivation is to stack up multiple bits on a single SRAM cell without multiplying the transistor count. The concept of spatial wavefunction switching (SWS) in the FET structure has been verified experimentally for two- and four-well structures. Quantum simulations exhibiting SWS in four-well Ge SWS FET structures, using the ZnSe/ZnS/ZnMgS/ZnSe gate insulator, are presented. These structures offer higher contrast than Si-SiGe SWS FETs. 相似文献
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A novel built-in self-test (BIST) architecture and a test pattern generator (TPG) design methodology to program this architecture are presented for inter-IC interconnects among combinational non-boundary scan ICs (often called cluster-ICs) via IEEE 1149.1 boundary scan architecture (BSA). Due to the expense and complexity of BSA circuitry, cluster-ICs are still widely used in modern circuit boards. Since combinational logic and 3-state cluster nets exist within cluster interconnect, in order to test all detectable faults in inter-IC nets that include cluster-ICs, newly identified TPG requirements are used to guarantee fault coverage during the design of proposed BIST architecture. This architecture contains a two-level C-TPG that generates constrained pseudo-random patterns for boundary scan cells (BSCs) of cluster control cones, a D-TPG that generates patterns for BSCs of cluster data cones, and a look-up table which is programmed to select, for each BSC, a specific C-TPG or D-TPG stage whose content is shifted into that BSC. This test architecture provides a true BIST solution for cluster testing. The proposed methodology generates TPGs that (i) guarantee the avoidance of multi-driver conflicts when testing via BSA, (ii) guarantee the detection of all testable interconnect faults, (iii) have low area overheads, and (iv) have short test lengths. 相似文献