模拟型演化硬件中可重构器件的比较研究

演化硬件的研究者受困于满足可演化要求的灵活可重构硬件平台的匮乏.一方面,虽然现有商用可重构平台多数具有动态可局部重构能力,但是其设计目的不是用来研究演化硬件的.另外一方面,用户定制的面向演化硬件研究的芯片没有商用化,而且也不太可能在最近走向商用市场.本文研究了两类用来进行模拟演化硬件研究的可重构器件:商用的现场可编程模拟阵列和用户定制的现场可编程三极管阵列.通过比较研究,作者认为在FPTA类定制用于演化的可重构平台商用化之前,在FPAA平台上开展EHW的研究是有意义的,因为FPAA已经具有充分灵活的重构接口和充足的可重配置资源.     

基于UDP协议的卫星用户地面站维护平台的设计及可靠性研究

卫星用户地面站作为卫星应急通信设备具有使用方便、组网灵活的特点。本文针对这些特点设计出了具有快速配置、可靠传输的维护平台。文中介绍了卫星用户地面站维护平台的接口、基本功能、通信协议以及通信流程。     

基于IP核的加油机编码器芯片设计

描述了一种基于微处理器IP核的加油机编码器芯片的设计.从扩展微处理器的在线调试功能、Flash接口设计、标准外设接口和中断管理等几个方面,详细讲述了该芯片的设计要点;芯片设计完成后,经过FPGA验证和ASIC实现.该芯片具有功能齐全、便于移植、可灵活配置等优点.     

基于FPGA的可配置IIC总线接口设计

针对传统IIC总线接口的FPGA设计可重用性不高的问题,提出了一种基于FPGA的可配置IIC总线接口设计方案。该方案采用同步有限状态机设计方法和硬件描述语言Verilog HDL, 对IIC总线的数据传输时序进行模块化设计,采用Signal Tap II对设计模块进行仿真验证。实验结果表明,该设计接口作为一种主控制器接口,可实现与具有IIC总线接口的从机器件100kb/s和400kb/s的可靠数据传输。该方案具有可重用度高、可配置性强、控制灵活等优点,并已成功运用于工程实践中。     

基于增强型SPI接口的大容量Flash扩展实现

TI最新的32位定点DSP TMS320F2812自身带有增强型SPI接口,具有占用硬件资源少、通信速率高、可灵活配置和可连续操作的特性.充分利用其SPI接口的增强特性,并运用ST公司的高速、大容量、高性价比串行接口Flash M25P80,实现了控制系统中对系统存储容量的高效扩展.详细描述了硬件设计和软件实现的具体方法和步骤,试验验证了设计的正确性,具有很大的参考价值和推广意义.     

语言加密系统

据《通信新闻》最新消息报道:美国通用电气公司移动通信商业分公司生产了一种语言加密系统,这种称为“VGE话音卫士”的系统是为国内和国际使用而设计的,它具有一个数字表式决系统,以增加加密方式的内部对讲通信范围。而且在MASTR Ⅱ工作站中的新话音卫士模块可与任何声音遥控控制台接口,以给用户控制通路通明话和控制RF通路通加密话音的灵活机动性。     

基于SOPC技术的USB2.0设备实现

通用串行总线USB是当前主流的计算机外设接口总线标准,设计实现灵活高效的USB设备控制器具有重要的现实意义.文中基于SOPC技术构建了一个完整的USB2.0设备系统,实现了USB大容量存储设备的功能.由于处理器和USB2.0设备控制器都是以IP软核的形式嵌入到FPGA中,整个系统具有灵活的可配置性.     

一种基于IIC总线的计算机接口板的设计

文章介绍了一种基于IIC总线的计算机接口板的硬件和软件的设计和实现.该接口板使用方便,接口功能齐全,配置灵活,性能可靠,具有实用价值.     

USB接口设计

随着计算机技术的飞速发展,PC的用户不断扩大.然而一些系统I/O(如IRQ、DMA和I/O端口地址)限制了它的使用.于是一些新的接口标准如USB、IEEE1394应运而生,本文着重介绍USB接口设计.使用了USB接口,用户不需要打开机盖、手工配置系统I/O、并为不同的外设接口发愁,而只需极其简单的安装与配置即可使用外设.     

ICS1523型高性能可编程行同步时钟发生器的原理及应用

ICS1523是一种高性能可编程行同步信号发生器,它带有一个I2C串行总线接口,可以方便地对内部寄存器进行配置,能产生用户需要的同步信号.详细介绍该电路的工作原理和寄存器格式,给出ICS1523与S1D13806的实际接口电路及程序设计.     

A DAB transmitter prototype with high flexibility and low cost

The design and implementation of a DAB transmitter prototype is proposed. The system architecture, ensemble multiplexer, channel encoder, OFDM (orthogonal frequency division multiplexing) modulator and other digital baseband parts are described. The prototype is fully compatible with ETS 300 401 and other related standards. It supports different services with various data formats and provides a convenient PC-based user interface. All I/Os and core parts are based on a modular design with a universal internal interface, hence the prototype can be flexibly configured to adapt to different requirements. Compared with existing products, the proposed transmitter prototype offers higher flexibility and lower cost.     

A microprocessor-compatible high-speed 8-bit DAC

The increasing use of microprocessors in systems which receive or generate analog signals has created a need for data converters which interface to those processors. A D/A converter which includes all registers and logic required for 8-bit microprocessor interface, and can be fabricated with a standard bipolar linear process is described. The system interface timing is specified such that the converter appears as a memory location to the microprocessor. It can be programmed to operate in a wide variety of modes and can interface with the fastest MOS and TTL microprocessors. The converter offers high-speed multiplying operation and an output current mode multiplexer. Status latches are provided to store multiplexer and code select commands. Nonsaturating multilevel logic operating nearly in the linear region provides gate delays of less than 5 ns when fabricated on the same chip with precision linear functions.     

10 Gb/s silicon bipolar 8:1 multiplexer and 1:8 demultiplexer

High-speed multiplexer and demultiplexer circuits are key components in high-speed optical communication systems such as SONET. As optical communication link speeds increase, faster electronic interface circuitry is required. The use of multiplexer circuits allows most of the electronic circuitry to operate on parallel data at a lower speed, reducing the speed requirements of much of the system. A retimed 8:1 multiplexer and a 1:8 demultiplexer which operate at 10 Gb/s are described. These circuits were fabricated in high-speed silicon bipolar process. Design optimization techniques were used to achieve maximum performance. The retimed multiplexer and the demultiplexer dissipate 3.8 and 4.3 W, respectively     

程控多路开关的研制

介绍了一种低热电势程控多路开关的工作原理和使用方法。该多路开关配以双地址只听ＩＥＥＥ－４８８接口，可用微机控制，也便于手动操作。本多路开关可为１６通道（每通道４个接点），也可为３２通道（每通道两个接点）。     

Computer-aided design of a singly-matched (S-M) multiplexer with acommon junction

Formulas based on scattering parameters are presented for the design of a multiplexer composed of n-1 channel equalizers connected either in parallel or in series at a common junction with a 1-Ω resistive generator and n-1 channel complex loads. It is shown as the singly-matched (S-M) multiplexer. A two-stage computer-aided design (CAD) approach is developed for the S-M multiplexer. A design example of a three-channel S-M multiplexer including the designs of three individual S-M channel equalizers is given to demonstrate the approach     

Current-mode multiplexer for interrogating resistive sensor arrays

A current-mode multiplexer for interrogating resistive sensor arrays has been fabricated in a commercial 2 μm BiCMOS process under the EUROCHIP initiative. The multiplexer allows a programmable voltage to be forced across the required sensor(s) and the resulting current can be offset by a programmable current source. Control of the device is via a simple serial digital interface     

Analyzing the Impact of Augmented Transistor NMOS Configuration on Parameters of 4x1 Multiplexer

This paper represents the power and delay analysis of 4×1 multiplexer based on Augmented Transistor NMOS (AT-NMOS) configurations. Transistor’s total channel width at multiple levels are considered to determine the leakage power and delay performance at 45 nm technology. It is evaluated that the performance parameter is improved in the proposed design based on Augmented Shorted Gate-Source PMOS with NMOS (ASG-S PMOS-NMOS) configuration as compared to the 4×1 multiplexer based on Static Threshold AT-NMOS (ST-ATNMOS) configuration. Using this combination, we obtain the desired performance parameters of the design. In this paper, two types of 4×1 multiplexer models are introduced. It is shown that the leakage power can be largely reduced. The delay performance is also improved up to 5% at 1 V power supply under consideration of multiple levels of transistor’s channel width due to evaluation of differentAT-NMOSconfigurations based 4×1 multiplexer models. The simulation work has been carried out using the Cadence Analog Virtuoso Spectre Simulator at 45 nm CMOS technology.     

DWDM用光学滤光片制造监控系统设计

分波/合波器是DWDM系统的核心器件之一,可采用光学滤光片镀膜实现,合格的膜系需要实现膜层厚度的精确控制。介绍一种自动控制镀膜系统,在国产镀膜系统的基础上,采用工业计算机进行自动控制,采用LabVIEW和Matlab混合编程,LabVIEW编写控制界面,实时显示监控曲线和数据存储,调用Matlab完成算法,该系统能完成复杂膜系的精确控制。     

Transmission characteristics of arrayed waveguide N×Nwavelength multiplexer

To realize practical wavelength division multiplexing (WDM) systems, a high-performance N×N wavelength multiplexer is introduced that is based on an arrayed-waveguide grating. Its transmission characteristics are theoretically derived and experimentally confirmed. A prototype is constructed using the previously proposed techniques that attain low insertion loss and polarization independent operation. It has 16 channels (N=16) with a spacing of 0.8 mn, or 100 GHz, in the 1.55-μm band. Frequency relation between input and output ports, free spectral range, and passband width are determined. A demonstration of IM-DD pulse transmission shows that there is no degradation of bit error rate resulting from the finite passband width and crosstalk of the multiplexer. It is confirmed that the multiplexer can realize highly reliable N-channel WDM and WDM-based N×N interconnect optical networks     

An N*N optical multiplexer using a planar arrangement of two star couplers

The author describes the design of an integrated N*N multiplexer capable of simultaneously multiplexing and demultiplexing a large number (up to about 50) of input and output wavelength channels. The multiplexer is a generalization of the 2*2 Mach-Zehnder multiplexer. It consists of two N*M star couplers connected by M paths of unequal length. Aberrations caused by mutual coupling in the waveguide arrays are minimized by a correction scheme that causes each star coupler to accurately perform a Fourier transformation. The multiplexer should be useful as a wavelength routing device for long haul and local area networks.<>