A single-chip 12.7 Mchips/s digital IF BPSK direct sequencespread-spectrum transceiver in 1.2 μm CMOS

This paper describes a fully integrated digital-spread spectrum transceiver chip fabricated through MOSIS in 1.2 μm CMOS. It includes a baseband spread spectrum transmitter and a coherent intermediate frequency (IF) receiver consisting of a Costas loop, an acquisition loop for the pseudo-noise (PN) sequence, and a clock recovery loop with a 406.4 MHz onchip numerically controlled oscillator (NCO). The transceiver is capable of operating at a maximum IF sampling rate of 50.8 MS/s and a maximum chip rate of 12.7 R Mchips/s (Mcps) with selectable data rates of 100, 200, 400, and 800 kbps. At the maximum operating speed of 50.8 R MS/s, it dissipates 1.1 W. In an additive white Gaussian noise channel the IF receiver achieves a receiver output SNR within 1 dB of theory and can acquire code with a wide range of input SNR from -17 dB to over 30 dB. The transceiver chip has been interfaced to an RF up/down converter to demonstrate a wireless voice/data/video link operating in the 902-928 MHz band     

A 2.6-V, 44-MHz all-digital QPSK direct-sequence spread-spectrumtransceiver IC [wireless LANs]

In this paper, an all-digital differentially encoded quaternary phase shift keying (DEQPSK) direct sequence spread-spectrum (DSSS) transceiver is proposed. The transceiver consists of two parts: a baseband/IF spread-spectrum transmitter and a coherent intermediate frequency (IF) receiver. The center frequency of this IF receiver is 11 MHz and the sampling rate is 44 Msamples/s. Modulation/demodulation, carrier recovery, PN acquisition, and differential coding are all provided within a single chip. Functional optimization and architecture design were performed before layout implementation. The 0.8-μm N-well CMOS chip has a complexity of 56000 transistors with a core area of 3.5×3.5 mm². Power dissipation is 92 and 145 mW at 2.6 and 3.3 V, respectively     

A frequency-agile single-chip QAM modulator with beamformingdiversity

Architecture and circuit design techniques for VLSI implementation of a single-chip quadrature amplitude modulation (QAM) modulator with frequency agility and antenna beamforming characteristics are presented. In order to achieve reliable wireless communication modem function, the single chip all-digital QAM modulator implements various features, including high data rates with bandwidth efficiency, flexibility, meeting a wide variety of user throughput requirements with variable and width and data rates in a multi-user system, and robustness, incorporating diversity and redundancy techniques to guarantee robust communication for various operating environments. The modulator components consist of several digital processing building blocks, including various finite-impulse-response (FIR) filters, an innovative variable interpolation filter, a four-channel frequency translator with quadrature mixer for antenna beamforming diversity, a quadrature direct digital frequency synthesizer (QDDFS), a numerically controlled oscillator (NCO), a QAM formatter, a pseudorandom noise (PN) generator, an x/sinx filter, and a microcontroller interface. An optimized architecture and chip implementation for the variable modulator is derived and evaluated which will support symbol rates from 6 kBaud to 8.75 MBaud continuously and digitally flexible IF frequencies up to 70 MHz with four-channel antenna beamforming function     

All-digital reverse modulation architecture based carrier recoveryimplementation for GMSK and compatible FQPSK

A carrier recovery circuit implementation with an all-digital reverse modulation approach for coherent detection in the GSM/GMSK system as well as the GMSK compatible improved efficiency cross-correlated FQPSK system is presented. The proposed carrier recovery implementation utilizes all-digital reverse modulation circuit in a feedback loop to remove the modulated signal from the received intermediate frequency (IF) signal and to estimate the phase error of this carrier signal using a phase-locked loop (PLL). The digital reverse modulation approach avoids the multipliers required in an analog reverse modulation design, so that it can be implemented in a single chip FPGA. Hardware implementation of the coherent detection demonstrates that cross-correlated FQPSK is completely compatible with GMSK in the system performance and the receiver structure for GSM. Experimental performance evaluations show that the proposed carrier recovery circuit provides a Bit Error Rate (BER) performance within 0.3 dB in a non-linearly amplified channel corrupted by additive white Gaussian noise (AWCN) as compared with the simulated performance of the GSM/GMSK system     

利用采样点选择法实现DS-CDMA中频接收机的码片同步

在ＤＳ－ＣＤＭＡ接收机中,正确解调的首要条件是实现本地扩频码与发送扩频码的码片同步。本文根据全数字接收机的实现方式和扩频解调的特点,提出了一种新颖的码片同步方式一采样点选择法。文中大致介绍了ＤＳ－ＣＤＭＡ全数字中频接收机的结构,重点讨论了利用采样点选择法实现码片同步的可行性,采样点选择法的性能。     

带残余频偏的QPSK-DSSS信号参数盲估计

本文对带残余频偏的正交相移键控(QPSK)调制的直接序列扩频(DSSS)信号参数估计问题展开研究.将二次谱法拓展到带残余频偏的QPSK-DSSS信号伪码周期估计中,即对信号的功率谱再进行傅氏变换并取模平方.其原理在于信号的二次谱将在伪码周期的整数倍处出现代表信号存在的尖锐三角形脉冲.对于残余频偏大小以及伪码码片速率的估...     

Third-generation TDRSS-compatible direct-sequence spread-spectrumdigital receiver

A digital communication receiver, called a third-generation receiver, has been developed. This receiver takes samples of the direct-sequence spread signal at a nonzero intermediate frequency (IF) instead of the zero IF (baseband), and quantizes the samples by employing a 1-b analog-to-digital (A/D) converter at the receiver front end. These 1-b samples are digitally processed for pseudonoise (PN) code, carrier, bit synchronization, and bit decision with the use of an application-specific integrated circuit. The effects of the IF sampling and 1-b A/D conversion on PN code synchronization are analyzed for a PN spread-spectrum communication system with oversampling rate, e.g., 12 samples per chip. In addition, the bit-error rate (BER) degradation due to the 1-b A/D conversion is studied by assuming perfect PN code, carrier, and bit synchronization. It is observed that the BER degradation due to the 1-b A/D is significant, e.g., 2.4 dB, when decimation is made after IF sampling such that only one sample per chip is used for bit decision. These analyzed BER results agree well with the simulated results. However, if no decimation is made and oversampling is used for bit decision, BER degradation due to 2-b A/D conversion is insignificant, e.g., 0.6 dB     

一种应用于图像传感器的全数字锁相环设计

针对图像传感器中传统锁相环(PLL)存在的功耗高、抖动大,以及锁定时长等问题,提出了一种基于计数器架构的低功耗、低噪声、低抖动、快速锁定的分数分频全数字锁相环(ADPLL)设计方法。首先,采用动态调节锁定控制算法来降低回路噪声,缩短锁定时间。其次,设计了一个通用单元来实现数字时间转换器(DTC)和时间数字转换器(TDC)的集成,以降低该部分由于增益不匹配引起的抖动。基于180nm CMOS工艺的仿真结果表明,在1.8V电源电压下,该ADPLL能够实现250MHz~2.8GHz范围的频率输出,锁定时间为1.028μs,当偏移载波频率为1MHz时,相位噪声为-102.249dBc/Hz,均方根抖动为1.7ps。     

600MHz BiCMOS digitally controlled oscillator for clock recovery and frequency synthesis PLLs

A 16-bit digitally controlled BiCMOS ring oscillator (DCO) is described. This BiCMOS DCO design provides improved frequency stability under thermal fluctuations. Simulations of a 5-stage DCO using 1μm BiCMOS process parameters achieved a controllable frequency range of 90-640MHz with a linear/quasi-linear range of around 300MHz. A tiny test chip was fabricated using MOSIS Orbit 2μm low-cost analogue CMOS process technology that provides a lateral NPN bipolar device option. Monotone frequency gain (frequency vs control-word transfer function) with fine stepping (tuning) over several kHz was verified experimentally, thus auguring the prospect of accurate frequency lock in an all-digital phase-locked loop (ADPLL) application. Worstcase jitter due to digital control transitions at pathological control-word boundaries for the BiCMOS DCO was observed to be less than 50 ps. This BiCMOS design would thus provide performance enhancement in PLL applications such as clock recovery and frequency synthesis.     

A 35-mW 3.6-mm/sup 2/ fully integrated 0.18-/spl mu/m CMOS GPS radio

A single-chip CMOS Global Positioning System (GPS) radio has been integrated using only a couple of external passive components for the input matching network and one external reference for the synthesizer. The receiver downconverts the GPS L1 signal at 1575.42 MHz to an IF of 9.45 MHz. The complete front-end and frequency synthesizer section have been integrated: low noise amplifier, image rejection mixer, IF active filter, and the full phase-locked loop synthesizer, including voltage-controlled oscillator and loop filter. The front-end measured performances are 81-dB maximum gain, 5.3-dB noise figure, and >30-dB image rejection. The synthesizer features a phase noise of -95 dBc/Hz at 1-MHz offset and a total integrated phase noise of less than 7/spl deg/ rms in the 500-Hz-1.5-MHz band. The front-end and the synthesizer draw, respectively, 11 and 9 mA from a 1.8-V supply. The architecture of the front-end and synthesizer has been geared to high level of integration and reduction of silicon area at the lowest possible power consumption. Consequently, the one reported here is the smallest and most integrated CMOS GPS receiver reported so far.     

Dual-band RF receiver for GPS-L1 and compass-B1 in a 55-nm CMOS

A fully integrated dual-band RF receiver with a low-IF architecture is designed and implemented for GPS-L 1 and Compass-Bl in a 55-nm CMOS process. The receiver incorporates two independent IF channels with 2 or 4 MHz bandwidth to receive dual-band signals around 1.57 GHz respectively. By implementing a flexible frequency plan, the RF front-end and frequency synthesizer are shared for the dual-band operation to save power consumption and chip area, as well as avoiding LO crosstalk. A digital automatic gain control （AGC） loop is utilized to improve the receiver＇s robustness by optimizing the conversion gain of the analog-to-digital converter （ADC）. While drawing about 20 mA per channel from a 1.2 V supply, this RF receiver achieves a minimum noise figure （NF） of about 1.8 dB, an image rejection （IMR） of more than 35 dB, a maximum voltage gain of about 122 dB, a gain dynamic range of 82 dB, and an maximum input-referred 1 dB compression point of about -36.5 dBm with an active die area of 1.5 × 1.4 mm2 for the whole chip.     

一种改进型PN码定时跟踪环

该文提出和研究了一种用于直接序列扩频系统的全数字非相干PN码定时跟踪环,除利用超前/滞后支路相关值的差别外,它还利用了准时支路的相关值信息。理论分析和仿真结果表明,在典型AWGN信道条件下,新方案改善了环路性能,并且算法复杂度明显降低。     

用于高能物理实验电子读出芯片的低噪声锁相环芯片设计

基于TSMC 180 nm工艺设计并流片测试了一款用于高能物理实验的电子读出系统的低噪声、低功耗锁相环芯片。该芯片主要由鉴频鉴相器、电荷泵、环路滤波器、压控振荡器和分频器等子模块组成,在锁相环电荷泵模块中,使用共源共栅电流镜结构精准镜像电流以减小电流失配和用运放钳位电压进一步减小相位噪声。测试结果表明,该锁相环芯片在1.8 V电源电压、输入50 MHz参考时钟条件下,可稳定输出200 MHz的差分时钟信号,时钟均方根抖动为2.26 ps(0.45 mUI),相位噪声在1 MHz频偏处为-105.83 dBc/Hz。芯片整体功耗实测为23.4 mW,锁相环核心功耗为2.02 mW。     

Jitter and phase noise of ADPLL due to PSN with deterministic frequency

In this article, jitter and phase noise of all-digital phase-locked loop due to power supply noise (PSN) with deterministic frequency are analysed. It leads to the conclusion that jitter and phase noise heavily depend on the noise frequency. Compared with jitter, phase noise is much less affected by the deterministic PSN. Our method is utilised to study a CMOS ADPLL designed and simulated in SMIC 0.13?µm standard CMOS process. A comparison between the results obtained by our method and those obtained by simulation and measurement proves the accuracy of the predicted model. When the digital controlled oscillator was corrupted by PSN with 100?mVpk-pk, the measured jitters were 33.9?ps at the rate of f_G?=?192?MHz and 148.5?ps at the rate of f_G?=?40?MHz. However, the measured phase noise was exactly the same except for two impulses appearing at 192 and 40?MHz, respectively.     

An all-digital low-power IF GPS synchronizer

An all-digital intermediate frequency (IF) Global Positioning System (GPS) synchronizer for employment in portable electronic applications is presented. The chip performs code and carrier synchronization, decodes received data, and provides pseudorange estimates. To reduce the average power dissipation, the whole receiver is powered down and reactivated only when it needs to update its position estimate. With a lower duty cycle, the receiver spends more time in the power-down mode and the power consumption of the whole receiver is proportionately reduced. The synchronizer is therefore designed to minimize re-acquisition time between position readings. When powered up, the synchronizer searches in parallel over a window of timing uncertainty, then employs near-optimal tracking with a variable loop gain filter. With SNR=-20 dB, phase shift rate of 1 chip/s, and user velocity of 30 m/s, the synchronizer chip dissipates under 4 mW for pseudorange estimate rms error of under 7 m     

Ka-band monolithic GaAs balanced mixers

Monolithic integrated circuits have been developed on semi-insulating GaAs substrates for millimeter-wave balanced mixers. The GaAs chip is used as a suspended stripline in a cross-bar mixer circuit. A double sideband noise figure of 4.5 dB has been achieved with a monolithic GaAs balanced mixer filter chip over a 30- to 32-GHz frequency range. A monolithic GaAs balanced mixer chip has also been optimized and combined with a hybrid MIC IF preamplifier in a planar package with significant improvement in RF bandwidth and reduction in chip size. A double sideband noise figure of less than 6 dB has been achieved over a 31- to 39-GHz frequency range with a GaAs chip size of only 0.5 × 0.43 in. This includes the contribution of a 1.5-dB noise figure due to IF preamplifier (5-500 MHz).     

A hybrid spreading/despreading function with good SNR performancefor band-limited DS-CDMA

Code-division multiple-access (CDMA) implemented with direct-sequence spread spectrum (DS/SS) signaling is a promising multiplexing technique for cellular telecommunications services. The efficiency of a direct-sequence spread-spectrum code-division multiple-access (DS-CDMA) system depends heavily on the shape of the spectrum of the spread signal. Maximum efficiency is obtained with an ideal brick-wall bandpass spectrum. There are two approaches toward achieving such a spectrum. One is to use a simple spreader that produces a broad spectrum and then follow it with a precise, high order filter to band limit the spectrum. A second approach, which is the approach taken in this paper, is to use a spreader that produces a spectrum close to the ideal spectrum and then employ a simple filter to control the out-of-band power. The proposed spreader/despreader is based on a simple hybrid function and can be easily implemented. An analysis provides a compact expression for the signal-to-noise ratio (SNR) of a RAKE receiver. The expression includes the effects of baseband, intermediate frequency (IF) and RF filtering as well as the effects of the spectral densities of the spreading/despreading functions. The analysis shows that the proposed spreader/despreader yields superior performance over a conventional pseudo noise (PN) spreading/despreading mechanism     

DS-UWB信号参数估计的自相关算法

利用DS-UWB信号周期平穗的特性,根据DS-UWB信号与高斯白噪声在自相关域上的差异,提出了一种DS-UWB信号参数估计的自相关算法.该算法可以在自相关积分时间不同的情况下,准确地估计DS-UWB信号伪码周期和伪码码片宽度,为下一步实现DS-UWB信号的细微特征分析提供了参考.理论分析和仿真实验都证明了该方法在低信噪比下非常有效.     

A Fast-Settling Wideband-IF ASK Baseband Circuit for a Wireless Endoscope Capsule

A novel automatic-gain-control (AGC) architecture utilizing wideband current feedback is proposed for the baseband circuit of a wireless endoscope capsule. The baseband circuit consists of a fast-settling wideband AGC loop and an amplitude-shift-keying demodulator. Additional integrators in the reverse signal path provide negative feedback, bandpass-filtering effect, attenuating low-frequency noises, and dc offset from the radio-frequency front end. The baseband circuit fabricated in a 180-nm complementary metal-oxide-semiconductor process achieves a wide-intermediate-frequency (IF) carrier frequency in the range of 0.5-40 MHz, a measured settling time of 2 mus, and an input sensitivity of -57 dBm. The entire baseband demodulator dissipates only 5 mA, with a 1.8-V supply at a data rate of 1.37 Mb/s and an IF carrier frequency of 10 MHz.