A composite CMOS gate array with 4K RAM and 128K ROM

A unique gate array structure, called a composite gate array, incorporating a RAM and a ROM along with ordinary gate arrays, is described. The composite gate array consists of a 128K ROM, a 4K RAM, and a 6K gate array, and is developed using 1.6-/spl mu/m CMOS technology. The RAM and ROM are partitioned into four 1K and eight 16K blocks for increasing flexibility of memory configuration. A distributed arrangement of memory blocks is used to permit completely automatic writing using fewer channels. In circuit performance, gate delay time is 1.0 ns, RAM access time is 25 ns, and ROM access time is 30 ns. A communication control processor for personal computer networks is successfully designed to demonstrate the feasibility of the gate array.     

Failure Analysis of Memory Organization for Utilization in a Self-Repair Memory System

Traditional approaches to memory reliability have been limited to complete redundancy or coding techniques. Redundancy frequently proves too expensive (introducing additional systems faults) and the traditional memory coding techniques have been limited to those areas of memory where a single fault results in a single failure (e.g., a broken core in a magnetic memory) as distinguished from an address decoder fault. To take an integrated approach to this problem, using a variety of coding and modularization techniques on each of the memory subsystems, it is necessary to determine the types of faults and failures caused by these faults that could occur in the system. This paper presents the results of a failure analysis study of typical 2D, 2?D, and 3D memory organizations. Two-way memories are also considered. This study demonstrates that a 2D memory, utilizing a switching array for memory access, is less susceptible to eatastrophic failures than other organizations considered. A memory organization capable of distributing the failures, in a manner permitting correction by linear codes, was adopted. Other techniques for automatic replacement of fault units are also considered.     

An on-line BIST RAM architecture with self-repair capabilities

The emerging field of self-repair computing is expected to have a major impact on deployable systems for space missions and defense applications, where high reliability, availability, and serviceability are needed. In this context, RAM (random access memories) are among the most critical components. This paper proposes a built-in self-repair (BISR) approach for RAM cores. The proposed design, introducing minimal and technology-dependent overheads, can detect and repair a wide range of memory faults including: stuck-at, coupling, and address faults. The test and repair capabilities are used on-line, and are completely transparent to the external user, who can use the memory without any change in the memory-access protocol. Using a fault-injection environment that can emulate the occurrence of faults inside the module, the effectiveness of the proposed architecture in terms of both fault detection and repairing capability was verified. Memories of various sizes have been considered to evaluate the area-overhead introduced by this proposed architecture     

Performance evaluation of a reconfiguration-algorithm for memoryarrays containing clustered faults

Reconfiguration of memory arrays using spare rows and columns is useful for yield-enhancement of memories. This paper presents a reconfiguration algorithm (QRCF) for memories that contain clustered faults. QRCF operates in a branch and bound fashion similar to known optimal algorithms that require exponential time. However, QRCF repairs faults in clusters rather than individually. Since many faults are repaired simultaneously, the execution-time of QRCF does not become prohibitive even for large memories containing many faults. The performance of QRCF is evaluated under a probabilistic model for clustered faults in a memory array. For a special case of the fault model, QRCF solves the reconfiguration problem exactly in polynomial time. In the general case, QRCF produces an optimal solution with high probability. The algorithm is also evaluated through simulation. The performance and execution-time of QRCF on arrays containing clustered faults are compared with other approximation algorithms and with an optimal algorithm. The simulation results show that QRCF outperforms previous approximation algorithms by a wide margin and performs nearly as well as the optimal algorithm with an execution-time that is orders of magnitude less     

Memory LSI reliability

Large-scale integrated (LSI) memory circuit reliability is reviewed. Reliability of large-scale integrated memory circuits is discussed. The major physical mechanisms for failures in memory LSIs and measures to counter these failures are reviewed. Fault-tolerant techniques, divided into the spare row/column line substitution. (SLS) technique and the on-chip error-correcting code (ECC) technique, developed to overcome hard and soft failures are described. Design approaches for realizing high performance and high reliability are also discussed     

0.5-μm 2 M-transistor BiPNMOS channelless gate array

A channelless gate array has been realized using 0.5-μm BiCMOS technology integrating more than two million transistors on a 14-mm×14.4-mm chip. A small-size PMOS transistor and a small-size inverter are added to the conventional BiNMOS gate to form the BiPNMOS gate. The gate is suitable for 3.3-V supply and achieves 230-ps gate delay for a two-input NAND with full-swing output. Added small-size MOS transistors in the BiPNMOS basic cell can also be used for memory macros effectively. A test chip with four memory macros-a high-speed RAM, a high-density RAM, a ROM, and a CAM macro-was fabricated. The high-speed memory macros utilize bipolar transistors in bipolar middle buffers and in sense amplifiers. The high-speed RAM macro achieves an access time of 2.7 ns at 16-kb capacity. The high-density RAM macro is rather slow but the memory cell occupies only a half of the BiPNMOS basic cell using a single-port memory cell     

A circuit design of intelligent cache DRAM with automaticwrite-back capability

An intelligent cache based on a distributed architecture that consists of a hierarchy of three memory sections-DRAM (dynamic RAM), SRAM (static RAM), and CAM (content addressable memory) as an on-chip tag-is reported. The test device of the memory core is fabricated in a 0.6 μm double-metal CMOS standard DRAM process, and the CAM matrix and control logic are embedded in the array. The array architecture can be applied to 16-Mb DRAM with less than 12% of the chip overhead. In addition to the tag, the array embedded CAM matrix supports a write-back function that provides a short read/write cycle time. The cache DRAM also has pin compatibility with address nonmultiplexed memories. By achieving a reasonable hit ratio (90%), this cache DRAM provides a high-performance intelligent main memory with a 12 ns(hit)/34 ns(average) cycle time and 55 mA (at 25 MHz) operating current     

A Highly Reliable Memory Subsystem Design Employing SECDED, Column Sparing, and Paging

This paper develops a reliability model for a paged memory system wherein the pages of memory are physically distributed among several arrays of memory chips. Any of the available pages can be used to satisfy the required memory capacity. This paper also develops a reliability model for a page or block of memory words imbedded in an array. The model assumes that memory chips have failure modes that are catastrophic to a row, to a column, to the whole physical array, or to individual bits. Spare columns or data lines are used to enhance reliability. SECDED (Single Error Correction, Double Error Detection) provides the hard-fault detection mechanism and complete fault coverage for soft faults such as 1-bit upsets. A highly reliable memory system design is described that implements a paging scheme, uses a SECDED code for hard fault detection and isolation, and uses three levels of sparing to recover from failures. The significance of this paper is that it considers failure modes associated with interfacing a memory chip into an array of memory chips. These failure modes have an impact beyond the boundaries of an individual chip; they affect the entire physical array and must be considered in the reliability model. When this is done the reliability model permits trading off page size and array size with reliability.     

含存储器数字电路板的TPS开发研究

提出了含存储器数字电路板的两种测试矢量集(TPS)开发方案.对含少量存储器芯片的电路板采用结构化的测试方案,即将RAM等效成时序电路模型,利用时序电路ATPG软件进行测试生成.对以RAM为主的存储器板提出了一种功能测试方案,采取压缩地址空间的方法,对RAM阵列进行读写操作.实际应用证明,这两种方案较好地满足了实际应用中的需要.     

Mitigating Soft Errors in SRAM Address Decoders Using Built-in Current Sensors

In this paper, we propose a diagnose strategy based on built-in current sensors able to detect the effects of single event transients (SETs) in SRAM memory decoders. By analyzing the effects, it is possible to mitigate the error by warning the system about the erroneous write and read operation or by circuit error correction avoiding catastrophic multiple bit upset errors. While EDAC can only protect faults in the memory cell array, the proposed method can cope with faults in the combinational memory circuitry. This BICS-based technique can be used in combination with EDAC to achieve high reliability in memories fabricated in nanometer technologies. Our methodology has been validated by Spice simulation and results show that our approach presents a low area, performance and power dissipation penalty.     

Overview of CCD memory

This paper summarizes the status and potential of charge-coupled device (CCD) memories. Cost-performance tradeoffs for serial memories are reviewed, and the CCD chip organizations for slow and fast access systems are discussed. Comparisons are made between CCD and MOS random access memory (RAM) chips on the basis of cell area, support circuits, cell operation, and technology.     

Overview of CCD memory

This paper summarizes the status and potential of charge-coupled device (CCD) memories. Cost-performance tradeoffs for serial memories are reviewed, and the CCD chip organizations for slow and fast access systems are discussed. Comparisons are made between CCD and MOS random access memory (RAM) chips on the basis of cell area, support circuits, cell operation, and technology.     

An efficient design of embedded memories and their testability analysis using Markov chains

This article presents a design strategy for efficient and comprehensive random testing of embedded random-access memory (RAM) where neither are the address, read/write and data input lines directly controllable nor are the data output lines externally observable. Unlike the conventional approaches, which frequently employ on-chip circuits such as linear feedback shift register (LFSR), data registers and multibit comparator for verifying the response of the memory-under-test (MUT) with the reference signature of a fault-free gold unit, the proposed technique uses an efficient testable design, which helps accelerate test algorithms by a factor of 0.5n, if the RAM is organized into an n×1 array and improve the test reliability by eliminating the LFSR that is known to have aliasing problems. Another serious problem in embedded memory testing by random test patterns is the problem of memory initialization, which has been tackled here by adding word-line flag registers. The paper has made indepth empirical studies of the functional faults such as stuck-at, coupling, and pattern-sensitive by suitably representing these faults by Markov chains and by simulating these chains to derive various test lengths required for detecting these faults. The simulation results conclusively show that, in order to test a IM-bit RAM for detecting the common functional faults, the proposed technique needs only one second as opposed to about an hour needed by the conventional random testing where memory cells are tested sequentially.An abridged version of this article was published in the IEEE International Conference on Wafer-Scale Integration, January 1989. This research was partially supported by the NSF under grant number MIP-9013092 and by ONR under grant number 85-K-0716.     

A gallium arsenide SDFL gate array with on-chip RAM

Describes a GaAs gate array with on-chip RAM based on the Schottky diode field-effect transistor logic (SDFL) technology. The array features 432 programmable SDFL cells, 32 programmable interface input-output (I/O) buffers, and four 4/spl times/4 bit static random access memories (RAM) on a 147 mil/spl times/185 mil chip. Each SDFL cell can be programmed as a NOR gate with as many as 8 inputs with a buffered or unbuffered output or as a dual OR-NAND gate with four inputs per side. The interface I/O buffer can be programmed for ECL, TTL, CMOS, and SDFL logic families. Each 4/spl times/4 bit RAM is fully decoded using SDFL circuits (depletion-mode MESFET). Preliminary results demonstrate the feasibility of GaAs SDFL for fast gate array and memory applications.     

Reliability of Single-Error Correction Protected Memories

Reliability is a critical factor for systems operating in radiation environments. Among the different components in a system, memories are one of the parts most sensitive to soft errors due to their relatively large area. Due to their large cost, traditional techniques like Triple Modular Redundancy are not used to protect memories. A typical approach is to apply Error Correction Codes to correct single errors, and detect double errors. This type of codes, for example those based on Hamming, provides an initial level of protection. Detected single errors are usually corrected using scrubbing, by which the memory positions are periodically re-written after a fixed (deterministic scrubbing), or variable period (probabilistic scrubbing). These traditional models usually offer good results when calculating the reliability of memories (e.g. through the Mean Time To Failure). However, there are some particularities that are not modeled through these approaches, to the best of our knowledge. One of these particularities is how double errors are handled. In a traditional approach, two errors in the same word produce always a system failure (only single errors can be corrected). However, if the two (or more) errors affect the same bit, either the second one reinforces the first one (keeping just a single error), or corrects it. In both scenarios, the resulting situation does not trigger a system failure, which has a direct impact on the reliability of the memory. In this paper, traditional reliability models are refined to handle the mentioned scenarios, which produces a more precise analysis in the calculation of mean time to failure for memory systems.      

Design of Memories with Concurrent Error Detection and Correction by Nonlinear SEC-DED Codes

In this paper we propose memory protection architectures based on nonlinear single-error-correcting, double-error-detecting (SEC-DED) codes. Linear SEC-DED codes widely used for design of reliable memories cannot detect and can miscorrect lots of errors with large Hamming weights. This may be a serious disadvantage for many modern technologies when error distributions are hard to estimate and multi-bit errors are highly probable. The proposed protection architectures have fewer undetectable errors and fewer errors that are miscorrected by all codewords than architectures based on linear codes with the same dimension at the cost of a small increase in the latency penalty, the area overhead and the power consumption. The nonlinear SEC-DED codes are generalized from the existing perfect nonlinear codes (Vasil’ev codes, Probl Kibern 8:375–378, 1962; Phelps codes, SIAM J Algebr Discrete Methods 4:398–403, 1983; and the codes based on one switching constructions, Etzion and Vardy, IEEE Trans Inf Theory 40:754–763, 1994). We present the error correcting algorithms, investigate and compare the error detection and correction capabilities of the proposed nonlinear SEC-DED codes to linear extended Hamming codes and show that replacing linear extended Hamming codes by the proposed nonlinear SEC-DED codes results in a drastic improvement in the reliability of the memory systems in the case of repeating errors or high multi-bit error rate. The proposed approach can be applied to RAM, ROM, FLASH and disk memories.     

语音合成集成电路中掩模ROM的解决方案

在语音合成集成电路(IC)中,需要存储大量的程序和语音数据,因此内存储器的集成度、读取速度及可靠性成为影响一款芯片生产成本和性能参数的关键指标。存储器有很多分类,掩模只读存储器(ROM)以其较高的集成度和较低的成本在中低档消费类语音合成IC中有着较为广泛的应用。给出一种语音合成IC中掩模ROM的解决方案,分别介绍3个组成部分:存储单元阵列、地址译码器和读出放大器的设计实现。采用该方案可以有效提高掩模ROM的集成度、读取速度及可靠性,有效降低语音合成IC的生产成本、提高其性能和市场竞争力。     

Peripheral circuits for one-transistor cell MOS RAM's

The use of a single transistor and storage capacitor allows MOS dynamic memories to be built with cell areas of less than two square mils. The logic signals then available are unusually small and balanced sensing is commonly used. Such sense amplifiers and other on-chip circuits peripheral to the memory array are increasingly important in determining the total area and cost, the performance and testing difficulties. This paper describes some of the key peripheral circuits used in a practical 4K random-access memory (RAM) design paying particular attention to these factors. A `margin test' facility is designed into the form of sense amplifier used and allows measurement of cell storage levels and sense amplifier offset to ensure that adequate signal margins exist in the memory.     

Techniques for Disturb Fault Collapsing

Disturb faults are considered one the most important failure modes in non volatile memories. Disturb faults are highly dependant on the core memory cell structure, manufacturing technology, and array organization. In this paper, we analyze the origins of such disturbs and propose a method that uses cell structure and array organization information to identify the relevant disturbs and to create a reduced fault list. To demonstrates its effectiveness, the method was used to create minimized fault lists for NOR and NAND flash memory arrays. Moreover, we show how the reduced fault list developed can be used to devise more efficient test algorithms. This work was supported by Kuwait University Research Grant Number EO 01/04.     

A review and projection of semiconductor components for digital storage

Evolution of present integrated-circuit technology over the remainder of the decade should result in semiconductor memories which are competitive with moving-surface memories and other alternatives in many digital storage applications requiring 10⁷-10¹⁰bits capacity. This paper considers MOS, MNOS, CCD, and bipolar component approaches to this objective. Cost, reliability, and power consumption, as affected by technological choices, receive attention. Alternative device technologies and circuit designs are examined. The one-transistor MOS RAM is seen to have potential for considerable growth. Packaging and interconnection methods for low cost and high reliability are considered; evolution of existing techniques is expected. Reliability and maintainability characteristics are seen to be controlled by device technology, component organization, and packaging characteristics. Testing, screening, and error-correction techniques are considered. Projections of component characteristics are extended to outline hypothetical designs for 4-million-bit and 256-million-bit storage systems which might be built by 1980. Features include 64K-bit MOS RAM components on die of area under 100 mm², system selling price of 40 m¢/bit, power consumption well below 1 µW/bit, system MTBF greater than 10⁵h, and physical density on the order of 16000 bits/ cm³. The basis for projected parameters is explained. The advantages and drawbacks of these hypothetical systems relative to moving-surface magnetic storage systems are outlined.