A 47 GHz Cross-Coupled VCO Employing High- Island-Gate Varactor for Phase Noise Reduction

A 47 GHz $LC$ cross-coupled voltage controlled oscillator (VCO) employing the high-$Q$ island-gate varactor (IGV) based on a 0.13 $mu{rm m}$ RFCMOS technology is reported in this work. To verify the improvement in the phase noise, two otherwise identical VCOs, each with an IGV and a conventional multi-finger varactor, were fabricated and the phase noise performance was compared. With $V_{DD}$ of 1.2 V and core power consumption of 3.86 mW, the VCOs with the IGV and the multi-finger varactor have a phase noise of $-$95.4 dBc/Hz and $-$91.4 dBc/Hz respectively, at 1 MHz offset, verifying the phase noise reduction with the introduction of the high-$Q$ IGV. The VCO with IGV exhibited an output power of around $-$15 dBm, leading to a FoM of $-$182.9 dBc/Hz and a tuning range of 3.35% (45.69 to 47.22 GHz).      

Integrated Quadrature Couplers and Their Application in Image-Reject Receivers

Several fully-integrated multi-stage lumped-element quadrature hybrids that enhance bandwidth, amplitude and phase accuracies, and robustness are presented, and a fully-integrated double-quadrature heterodyne receiver front-end that uses two-stage Lange/Lange couplers is described. The Lange/Lange cascade exploits the inherent wide bandwidth characteristic of the Lange hybrid and enables a robust design using a relatively low transformer coupling coefficient. The measured image-rejection ratio is $>$ 55 dB over a 200 MHz bandwidth centered around 5.25 $~$GHz without any tuning, trimming, or calibration; the front-end features 23.5 dB gain, $-$79 dBm sensitivity, 5.6 dB SSB NF, $-$7$~$ dBm IIP3, $-$18 dB $S_{11}$ and a 1 mm $times$ 2 mm die area in 0.18$ mu{hbox {m}}$ CMOS.      

A $Q$ -Band Four-Element Phased-Array Front-End Receiver With Integrated Wilkinson Power Combiners in 0.18-$mu{{hbox{m}}}$ SiGe BiCMOS Technology

A four-element phased-array front-end receiver based on 4-bit RF phase shifters is demonstrated in a standard 0.18- $mu{{hbox{m}}}$ SiGe BiCMOS technology for $Q$-band (30–50 GHz) satellite communications and radar applications. The phased-array receiver uses a corporate-feed approach with on-chip Wilkinson power combiners, and shows a power gain of 10.4 dB with an ${rm IIP}_{3}$ of $-$13.8 dBm per element at 38.5 GHz and a 3-dB gain bandwidth of 32.8–44 GHz. The rms gain and phase errors are $leq$1.2 dB and $leq {hbox{8.7}}^{circ}$ for all 4-bit phase states at 30–50 GHz. The beamformer also results in $leq$ 0.4 dB of rms gain mismatch and $leq {hbox{2}}^{circ}$ of rms phase mismatch between the four channels. The channel-to-channel isolation is better than $-$35 dB at 30–50 GHz. The chip consumes 118 mA from a 5-V supply voltage and overall chip size is ${hbox{1.4}}times {hbox{1.7}} {{hbox{mm}}}^{2}$ including all pads and CMOS control electronics.      

17 GHz RF Front-Ends for Low-Power Wireless Sensor Networks

A 17 GHz low-power radio transceiver front-end implemented in a 0.25 $mu{hbox {m}}$ SiGe:C BiCMOS technology is described. Operating at data rates up to 10 Mbit/s with a reduced transceiver turn-on time of 2 $mu{hbox {s}}$, gives an overall energy consumption of 1.75 nJ/bit for the receiver and 1.6 nJ/bit for the transmitter. The measured conversion gain of the receiver chain is 25–30 dB into a 50 $Omega$ load at 10 MHz IF, and noise figure is 12 $pm$0.5 dB across the band from 10 to 200 MHz. The 1-dB compression point at the receiver input is $-$37 dBm and ${hbox{IIP}}_{3}$ is $-$25 dBm. The maximum saturated output power from the on-chip transmit amplifier is $-$1.4 dBm. Power consumption is 17.5 mW in receiver mode, and 16 mW in transmit mode, both operating from a 2.5 V supply. In standby, the transceiver supply current is less than 1 $mu{hbox {A}}$.      

2 MHz AO $Q$ -switched ${rm TEM}_{00}$ Grazing Incidence Laser With 3 at.% Neodymium Doped Nd:YVO$_{4}$

We present a detailed experimental and theoretical study of the ultrahigh repetition rate AO $Q$ -switched ${rm TEM}_{00}$ grazing incidence laser. Up to 2.1 MHz $Q$-switching with ${rm TEM}_{00}$ output of 8.6 W and 2.2 MHz $Q$ -switching with multimode output of 10 W were achieved by using an acousto-optics $Q$ -switched grazing-incidence laser with optimum grazing-incidence angle and cavity configuration. The crystal was 3 at.% neodymium doped Nd:YVO$_{4}$ slab. The pulse duration at 2 MHz repetition rate was about 31 ns. The instabilities of pulse energy at 2 MHz repetition rate were less than ${pm}6.7hbox{%}$ with ${rm TEM}_{00}$ operation and ${pm}3.3hbox{%}$ with multimode operation respectively. The modeling of high repetition rate $Q$-switched operation is presented based on the rate equation, and with the solution of the modeling, higher pump power, smaller section area of laser mode, and larger stimulated emission cross section of the gain medium are beneficial to the $Q$-switched operation with ultrahigh repetition rate, which is in consistent with the experimental results.      

A 0.55 V 60 dB-DR Fourth-Order Analog Baseband Filter

A 0.55 V supply voltage fourth-order low-pass continuous-time filter is presented. The low-voltage operating point is achieved by an improved bias circuit that uses different opamp input and output common-mode voltages. The fourth-order filter architecture is composed by two Active- ${rm G}_{rm m}{-}{rm RC}$ biquadratic cells, which use a single opamp per-cell with a unity-gain-bandwidth comparable to the filter cut-off frequency. The $-$ 3 dB filter frequency is 12 MHz and this is higher than any other low-voltage continuous-time filter cut-off frequency. The $-$3 dB frequency can be adjusted by means of a digitally-controlled capacitance array. In a standard 0.13 $mu{rm m}$ CMOS technology with ${V}_{THN}approx 0.25 {rm V}$ and ${V}_{THP}approx 0.3 {rm V}$, the filter operates with a supply voltage as low as 0.55 V. The filter $({rm total} {rm area}=0.47 {rm mm}^{2})$ consumes 3.4 mW. A 8 dBm-in-band IIP3 and a 13.3 dBm-out-of-band IIP3 demonstrate the validity of the proposal.      

Q-Band pHEMT and mHEMT Subharmonic Gilbert Upconversion Mixers

This letter makes a comparison between Q-band 0.15 $mu{rm m}$ pseudomorphic high electron mobility transistor (pHEMT) and metamorphic high electron mobility transistor (mHEMT) stacked-LO subharmonic upconversion mixers in terms of gain, isolation and linearity. In general, a 0.15 $mu{rm m}$ mHEMT device has a higher transconductance and cutoff frequency than a 0.15 $mu{rm m}$ pHEMT does. Thus, the conversion gain of the mHEMT is higher than that of the pHEMT in the active Gilbert mixer design. The Q-band stacked-LO subharmonic upconversion mixers using the pHEMT and mHEMT technologies have conversion gain of $-$7.1 dB and $-$0.2 dB, respectively. The pHEMT upconversion mixer has an ${rm OIP}_{3}$ of $-$12 dBm and an ${rm OP}_{1 {rm dB}}$ of $-$24 dBm, while the mHEMT one shows a 4 dB improvement on linearity for the difference between the ${rm OIP}_{3}$ and ${rm OP}_{1 {rm dB}}$. Both the chip sizes are the same at 1.3 mm $times$ 0.9 mm.      

180$^{circ}$ and 90$^{circ}$ Phase Shifting Networks With an Octave Bandwidth and Small Phase Errors

A new phase shifting network for both 180 $^{circ}$ and 90 $^{circ}$ phase shift with small phase errors over an octave bandwidth is presented. The theoretical bandwidth is 67% for the 180$^{circ}$ phase bit and 86% for the 90$^{circ}$ phase bit when phase errors are $pm 2^{circ}$. The proposed topology consists of a bandpass filter (BPF) branch, consisting of a LC resonator and two shunt quarter-wavelength transmission lines (TLs), and a reference TL. A theoretical analysis is provided and scalable parameters are listed for both phase bits. To test the theory, phase shifting networks from 1 GHz to 3 GHz were designed. The measured phase errors of the 180$^{circ}$ and the 90$^{circ}$ phase bit are $pm 3.5^{circ}$ and $pm 2.5^{circ}$ over a bandwidth of 73% and 102% while the return losses are better than 18 dB and 12 dB, respectively.      

Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL

This paper demonstrates that spurious tones in the output of a fractional-N PLL can be reduced by replacing the $DeltaSigma$ modulator with a new type of digital quantizer and adding a charge pump offset combined with a sampled loop filter. It describes the underlying mechanisms of the spurious tones, proposes techniques that mitigate the effects of the mechanisms, and presents a phase noise cancelling 2.4 GHz ISM-band CMOS PLL that demonstrates the techniques. The PLL has a 975 kHz loop bandwidth and a 12 MHz reference. Its phase noise has a worst-case reference spur power of $-$ 70 dBc and a worst-case in-band fractional spur power of $-$64 dBc.      

High- RF-MEMS 4–6-GHz Tunable Evanescent-Mode Cavity Filter

This paper presents a miniature high- $Q$ tunable evanescent-mode cavity filter using planar capacitive RF microelectromechanical system (MEMS) switch networks and with a frequency coverage of 4.07–5.58 GHz. The two-pole filter, with an internal volume of 1.5 cm$^3$ , results in an insertion loss of 4.91–3.18- and a 1-dB bandwidth of 17.8–41.1 MHz, respectively, and an ultimate rejection of $>$ 80 dB. RF-MEMS switches with digital/analog tuning capabilities were used in the tunable networks so as to align the two poles together and result in a near-ideal frequency response. The measured $Q_{u}$ of the filter is 300–500 over the tuning range, which is the best reported $Q$ using RF-MEMS technology. The filter can withstand an acceleration of 55–110 g without affecting its frequency response. The topology can be extended to a multiple-pole design with the use of several RF-MEMS tuning networks inside the evanescent-mode cavity. To our knowledge, these results represent the state-of-the-art in RF-MEMS tunable filters.      

A $W$ -Band Photonic Transmitter/Mixer Based on High-Power Near-Ballistic Uni-Traveling-Carrier Photodiode (NBUTC-PD)

In this letter, we demonstrate a $W$-band photonic transmitter/mixer fabricated by the flip-chip bonding of a high-power back-illuminated near-ballistic uni-traveling-carrier photodiode (NBUTC-PD) and an end-fire quasi-Yagi antenna on an AlN substrate. This end-fire and directional antenna design eliminates the need for the integration of an additional Si-lens into the antenna for directional power transmission. The high bias dependent nonlinearity of the integrated NBUTC-PD means that the bias modulation technique can be used to directly up-convert the intermediate-frequency signal to a millimeter-wave signal at $W$ -band without using a costly high-speed optical modulator. A reasonable detected power ($-$ 17 dBm at 106 GHz) can be achieved with the demonstrated device with a high-output photocurrent (30 mA) and a low internal-conversion loss ($-$2.4 dB) between the radio-frequency and local-oscillator signals at $W$-band.      

Bending and Strain Sensitivities in a Helicoidal Long-Period Fiber Gratings

In this letter, we report bending and strain sensitivities of helicoidal long-period fiber gratings fabricated by twisting single-mode fibers during $hbox{CO}_{2}$ laser irradiation. Linear spectral shifts of the resonant wavelengths under the bending and tensile strain were observed with the sensitivities of $-$11.7 nm/m$^{-1}$ and $-$1.1 $hbox{pm}/muvarepsilon$, respectively. The corresponding transmission power variations at the resonance wavelength were 4.1 $hbox{dB/m}^{-1}$ and $2.2times 10^{-4} hbox{dB}/muvarepsilon$, respectively. Detailed measurement techniques and sensor applications are discussed.      

An 8.1 mW, 82 dB Delta-Sigma ADC With 1.9 MHz BW and $-$98 dB THD

A switched-capacitor low-distortion 15-level delta-sigma ADC is described. It achieves third-order noise shaping with only two integrators by using quantization noise coupling. Realized in a 0.18 $mu{hbox{m}}$ CMOS technology, it provides 81 dB SNDR, 82 dB dynamic range, and $-$98 dB THD in a signal bandwidth of 1.9 MHz. It dissipates 8.1 mW with a 1.5 $~$V power supply (analog power 4.4 mW, digital power 3.7$~$ mW). Its figure-of-merit is 0.25 pJ/conversion-step, which is among the best reported for discrete-time delta-sigma ADCs in wideband applications.      

A 0.13 $mu$ m CMOS Quad-Band GSM/GPRS/EDGE RF Transceiver Using a Low-Noise Fractional-N Frequency Synthesizer and Direct-Conversion Architecture

This paper presents a single-chip CMOS quad-band (850/900/1800/1900 MHz) RF transceiver for GSM/GPRS/EDGE applications which adopts a direct-conversion receiver, a direct-conversion transmitter and a fractional-N frequency synthesizer with a built-in DCXO. In the GSM mode, the transmitter delivers 4 dBm of output power with 1$^{circ}$ RMS phase error and the measured phase noise is ${-}$164.5 dBc/Hz at 20 MHz offset from a 914.8$~$MHz carrier. In the EDGE mode, the TX RMS EVM is 2.4% with a 0.5 $~$dB gain step for the overall 36 dB dynamic range. The RX NF and IIP3 are 2.7 dB/ ${-}$12 dBm for the low bands (850/900 MHz) and 3 dB/${-}$ 11 dBm for the high bands (1800/1900 MHz). This transceiver is implemented in 0.13 $mu$m CMOS technology and occupies 10.5 mm$^{2}$ . The device consumes 118 mA and 84 mA in TX and RX modes from 2.8 V, respectively and is housed in a 5$,times,$ 5 mm$^{2}$ 40-pin QFN package.      

A 10:1 Unequal Wilkinson Power Divider Using Coupled Lines With Two Shorts

A novel unequal Wilkinson power divider is presented. A coupled-line section with two shorts is proposed to realize the high characteristic impedance line, which cannot be implemented by conventional microstrip fabrication technique due to fabrication limitation. The proposed coupled-line structure is compatible with single layer integration and can be easily designed based on an even-odd mode analysis. As a design example, a 10:1 Wilkinson power divider at 2 GHz is fabricated and measured. The measured $-10~{rm dB}$ bandwidth of $S_{11}$ is about 16%, and the isolation $S_{32}$ is better than $-20~{rm dB}$ . The measured amplitude balance between output port 2 and port 3 is between $-10.20~{rm dB}$ and $-9.52~{rm dB}$, and the corresponding phase difference is between 0$^{circ}$ and 4.6$^{circ}$.      

Compact $S$ -/$Ka$-Band CMOS Quadrature Hybrids With High Phase Balance Based on Multilayer Transformer Over-Coupling Technique

This paper presents compact CMOS quadrature hybrids by using the transformer over-coupling technique to eliminate significant phase error in the presence of low-$Q$ CMOS components. The technique includes the inductive and capacitive couplings, where the former is realized by employing a tightly inductive-coupled transformer and the latter by an additional capacitor across the transformer winding. Their phase balance effects are investigated and the design methodology is presented. The measurement results show that the designed 24-GHz CMOS quadrature hybrid has excellent phase balance within ${pm}{hbox{0.6}}^{circ}$ and amplitude balance less than ${pm} {hbox{0.3}}$ dB over a 16% fractional bandwidth with extremely compact size of 0.05 mm$^{2}$. For the 2.4-GHz hybrid monolithic microwave integrated circuit, it has measured phase balance of ${pm}{hbox{0.8}}^{circ}$ and amplitude balance of ${pm} {hbox{0.3}}$ dB over a 10% fractional bandwidth with a chip area of 0.1 mm$^{2}$ .      

Tunable Linear MOS Resistors Using Quasi-Floating-Gate Techniques

A family of tunable MOS resistors based on quasi-floating-gate (QFG) transistors biased in the triode region is analyzed in this paper. From the study results, a new device that outperforms previous implementations, is presented. By means of a capacitive divider, the ac component of the drain-to-source voltage scaled with a factor $alphaleq 1$ is added to the gate-to-source voltage leading to a cancellation of the nonlinear terms. The effect of $alpha$ on resistor linearity is analytically studied. Simulation results are also provided for different technologies. Finally, a complete transconductor has been built which preserves the linearity of the MOS resistor. Three versions of the transconductor have been fabricated for different values of $alpha$ ($alpha=$ 0, 0.5, and 1) in a 0.5 $mu{hbox {m}}$ CMOS technology with $pm$1.65-V supply voltage. Experimental results show (for $alpha=1$ ) a THD of $-$ 57 dB $({rm HD}2=-70 {hbox {dB}})$ at 1 MHz for 2-V peak-to-peak differential input signal with a nominal ac-transconductance of 200 $muhbox{A/V}$ and a power consumption of 3.2 mW.      

$S$ - and $C$ -Band Ultra-Compact Phase Shifters Based on All-Pass Networks

Ultra-compact phase shifters are presented. The proposed phase-shifting circuits utilize the lumped element all-pass networks. The transition frequency of the all-pass network, which determines the size of the circuit, is set to be much higher than the operating frequency. This results in a significantly small chip size of the phase shifter. To verify this methodology, 5-bit phase shifters have been fabricated in the $S$ - and $C$ -band. The $S$ -band phase shifter, with a chip size of 1.87 mm $,times,$0.87 mm (1.63 mm $^{2}$), has achieved an insertion loss of ${hbox{6.1 dB}} pm {hbox{0.6 dB}}$ and rms phase-shift error of less than 2.8$^{circ}$ in 10% bandwidth. The $C$ -band phase shifter, with a chip size of 1.72 mm $,times,$0.81 mm (1.37 mm $^{2}$), has demonstrated an insertion loss of 5.7 dB $pm$ 0.8 dB and rms phase-shift error of less than 2.3 $^{circ}$ in 10% bandwidth.      

A 5-GHz CMOS Type-II PLL With Low $K_{rm VCO}$ and Extended Fine-Tuning Range

A 5-GHz dual-path integer-$N$ Type-II phase-locked loop (PLL) uses an LC voltage-controlled oscillator and softly switched varactors in an overlapped digitally controlled integral path to allow a large fine-tuning range of approximately 160 MHz while realizing a low susceptibility to noise and spurs by using a low $K_{rm VCO}$ of 3.2 MHz/V. The reference spur level is less than $-$70 dBc with a 1-MHz reference frequency and a total loop-filter capacitance of 26 pF. The measured phase noise is $-$75 and $-$115 dBc/Hz at 10-kHz and 1-MHz offsets, respectively, using a loop bandwidth of approximately 30 kHz. This 0.25-${hbox{mm}}^{2}$ PLL is fabricated in a 90-nm digital CMOS process and consumes 11 mW from a 1.2-V supply.      

A 0.1–5 GHz Cryogenic SiGe MMIC LNA

In this letter, the design and measurement of the first SiGe integrated-circuit LNA specifically designed for operation at cryogenic temperatures is presented. At room temperature, the circuit provides greater than 25.8 dB of gain with an average noise temperature $(T_{e})$ of 76 K $(NF=1 {rm dB})$ and $S_{11}$ of $-$ 9 dB for frequencies in the 0.1–5 GHz band. At 15 K, the amplifier has greater than 29.6 dB of gain with an average $T_{e}$ of 4.3 K and $S_{11}$ of $-$14.6 dB for frequencies in the 0.1–5 GHz range. To the authors' knowledge, this is the lowest noise ever reported for a silicon integrated circuit operating in the low microwave range and the first matched wideband cryogenic integrated circuit LNA that covers frequencies as low as 0.1 GHz.