An Overview of a Compiler for Mapping Software Binaries to Hardware

As new applications in embedded communications and control systems push the computational limits of digital signal processing (DSP) functions, there will be an increasing need for software applications to be migrated to hardware in the form of a hardware-software codesign system. In many cases, access to the high-level source code may not be available. It is thus desirable to have a technology to translate the software binaries intended for processors to hardware implementations. This paper provides details on the retargetable FREEDOM compiler. The compiler automatically translates DSP software binaries to register-transfer level (RTL) VHDL and Verilog for implementation on field-programmable gate arrays (FPGAs) as standalone or system-on-chip implementations. We describe the underlying optimizations and some novel algorithms for alias analysis, data dependency analysis, memory optimizations, procedure call recovery, and back-end code scheduling. Experimental results on resource usage and performance are shown for several program binaries intended for the Texas Instruments C 6211 DSP (VLIW) and the ARM 922 T reduced instruction set computer (RISC) processors. Implementation results for four kernels from the Simulink demo library and others from commonly used DSP applications, such as MPEG-4, Viterbi, and JPEG are also discussed. The compiler generated RTL code is mapped to Xilinx Virtex II and Altera Stratix FPGAs. We record overall performance gains of 1.5-26.9 for the hardware implementations of the kernels. Comparisons with the power aware compiler techniques (PACT) high-level synthesis compiler are used to show that software binaries can be used as intermediate representations from any high-level language and generate efficient hardware implementations.     

Compilation Methods for the Address Calculation Units of Embedded Processor Systems

An essential component of today's embedded system is an instruction-set processor running real-time software. All variations of these core components contain at least the minimum data-flow processing capabilities, while a certain class contain specialized units for highly data-intensive operations for Digital Signal Processing (DSP). For the required level of memory interaction, the parallel executing Address Calculation Unit (ACU) is often used to tune the architecture to the memory access characteristics of the application. The design of the ACU is performance critical. In today's typical design flow, this design task is somewhat driven by intuition as the transformation from application algorithm to architecture is complex and the exploration space is immense. Automatic utilities to aid the designer are essential; however, the key compilation techniques which map high-level language constructs onto addressing units have lagged far behind the emergence of these units. This paper presents a new retargetable approach and prototype tool for the analysis of array references and traversals for efficient use of ACUs. In addition to being an enhancement to existing compiler systems, the ArrSyn utility may be used as an aid to architecture exploration. A simple specification of the addressing resources and basic operations drives the available transformations and allows the designer to quickly evaluate the effects on speed and code size of his/her algorithm. Thus, the designer can tune the design of the ACU toward the application constraints. ArrSyn has been successfully used together with a C compiler developed for a VLIW architecture for an MPEG audio decoding application. The combination of these methods with the C compiler showed on average a 39% speedup and 29% code size reduction for a representative set of DSP benchmarks.     

Blocking in a system on a chip

With more and larger functions being implemented on a single piece of silicon, true systems on a chip are being created. At the physical level, this integration derives from progress in process technology. But from the circuit designers' viewpoint, tools and methods are less help than they might be. In effect, to construct a system on a chip means more than the integration of millions of transistors. A set of complicated and rapidly evolving technologies and standards for telecommunications, multimedia, and PCs must be mastered, too. Also, the software content of most electronic systems has been growing for several years and now often accounts for a major part of the final product and hence of the design effort. Since a system on a chip is a system, a design methodology for generating such complex ICs will frequently have to address the software as well as hardware needs. Further more, as the size and complexity of chips has grown, so too has the task of verification. Verifying the design of a chip containing a million gates of logic presents a formidable challenge of its own. The complexity of large designs calls for a shift in the design paradigm to one based on reusable, high-level building blocks. Currently, most functional blocks are created by hand and are seldom used again. Reusable blocks, though, are not enough. To deliver on the promise of more productivity and less time to market, designers need reinforcements-a methodology and tools with which to integrate the blocks efficiently, plus standards that support the creation of reusable blocks, their exchange, and their integration     

Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures

Integrated circuits in telecommunications and consumer electronics are rapidly evolving towards single chip solutions. New IC architectures are emerging, which combine instruction-set processor cores with customised hardware. This paper describes a high-level synthesis system for integration of real-time signal processing systems on such processor cores. The compiler supports a flexible architectural model. It can handle certain types of incompletely specified architectures, and offers capabilities for retargetable compilation and architectural exploration. Results for a realistic application from the domain of audio processing indicate the feasibility and power of the presented approach.     

Mining metadata for composability of IPs from SystemC IP library

Exploring the design space when constructing a system is vital to realize a well performing design. Design complexity has made building high-level system models to explore the design space an essential but time-consuming and tedious part of the system design. Reduction in design time and acceleration of design exploration can be provided through reusing IP-cores to construct system models. As a result, it is common to have high-level SoC design flow based on IP libraries promoting reuse. However, the success of these would be dependent on how introspection and reflection capabilities are provided as well as what are the interoperability standard defined. This leads to the important question of what kind of IP metadata must be available to allow CAD tools to effectively manipulate these designs as well as allow for a seamless integration and exchange design information between tools and design flows. In this article, we describe our tools and methodology, which allow introspection of SystemC designs, such that the extracted metadata enables IP composition. We discuss the issues related to extraction of metadata from IPs specified in SystemC and show how our methodology combines C++ and XML parsers and data structures to achieve the above.     

Building models of real-time systems from application software

We present a methodology for building timed models of real-time systems by adding time constraints to their application software. The applied constraints take into account execution times of atomic statements, the behavior of the system's external environment, and scheduling policies. The timed models of the application obtained in this manner can be analyzed by using time analysis techniques to check relevant real-time properties. We show an instance of the methodology developed in the TAXYS project for the modeling and analysis of real-time systems programmed in the Esterel language. This language has been extended to describe, by using pragmas, time constraints characterizing the execution platform and the external environment. An analyzable timed model of the real-time system is produced by composing instrumented C-code generated by the compiler. The latter has been re-engineered in order to take into account the pragmas. Finally, we report on applications of TAXYS to several nontrivial examples.     

Integrated multiscale modeling of the nervous system: predicting changes in hippocampal network activity by a positive AMPA receptor modulator

One of the fundamental characteristics of the brain is its hierarchical organization. Scales in both space and time that must be considered when integrating across hierarchies of the nervous system are sufficiently great as to have impeded the development of routine multilevel modeling methodologies. Complex molecular interactions at the level of receptors and channels regulate activity at the level of neurons; interactions between multiple populations of neurons ultimately give rise to complex neural systems function and behavior. This spatial complexity takes place in the context of a composite temporal integration of multiple, different events unfolding at the millisecond, second, minute, hour, and longer time scales. In this study, we present a multiscale modeling methodology that integrates synaptic models into single neuron, and multineuron, network models. We have applied this approach to the specific problem of how changes at the level of kinetic parameters of a receptor-channel model are translated into changes in the temporal firing pattern of a single neuron, and ultimately, changes in the spatiotemporal activity of a network of neurons. These results demonstrate how this powerful methodology can be applied to understand the effects of a given local process within multiple hierarchical levels of the nervous system.     

Efficient object-oriented integration and regression testing

This paper presents a model, a strategy and a methodology for planning integration and regression testing from an object-oriented model. It shows how to produce a model of structural system test dependencies which evolves with the refinement process of the object-oriented design. The model (test dependency graph) serves as a basis for ordering classes and methods to be tested for regression and integration purposes (minimization of test stubs). The mapping from unified modeling language to the defined model is detailed as well as the test methodology. While the complexity of optimal stub minimization is exponential with the size of the model, an algorithm is given that: computes a strategy for integration testing with a quadratic complexity in the worst case; and provides an efficient testing order for minimizing the number of stubs. Various integration strategies are compared with the optimized algorithm (a real-world case study illustrates this comparison). The results of the experiment seem to give nearly optimal stubs with a low cost despite the exponential complexity of getting optimal stubs. As being a part of a design-for-testability approach, the presented methodology also leads to the early repartition of testing resources during system integration for reducing integration duration     

Object-oriented domain specific compilers for programming FPGAs

Simplifying the programming models is paramount to the success of reconfigurable computing with field programmable gate arrays (FPGAs). This paper presents a methodology to combine true object-oriented design of the compiler/CAD tool with an object-oriented hardware design methodology in C++. The resulting system provides all the benefits of object-oriented design to the compiler/CAD tool designer and to the hardware designer/programmer. The two examples for domain-specific compilers presented are BSAT and StReAm. Each domain-specific compiler is targeted at a very specific application domain, such as applications that accelerate Boolean satisfiability problems with BSAT, and applications which lend themselves for implementation as a stream architecture with StReAm. The key benefit of the presented domain specific compilers is a reduction of design time by orders of magnitude while keeping the optimal performance of hand-designed circuits     

On the fully numerical evaluation of the linear-shape functiontimes the 3D Green's function on a plane triangle

A numerical technique is reported for the evaluation of improper integrals associated with the self-interaction terms arising in the application of linear (Rao-Wilton-Glisson) current basis functions, defined on planar triangular patches, to three-dimensional electromagnetic surface scattering problems. The two-dimensional numerical integration arising in more conventional approaches, which follow Graglia [1993], is replaced by a one-dimensional integration by means of a suitable change of the local coordinate system, and analytical expressions for the functions to be numerically integrated are derived. Numerical results obtained using Graglia's method, our alternative method, and a reliable reference solution are compared for accuracy and computational complexity. The alternative technique appears to be conceptually simpler than the conventional method, is easier to implement, and causes no degradation in accuracy; in fact, it seems to more efficiently achieve a slightly specified level of accuracy     

Telecommunication system architectures: Dealing with complexity

The changing environment of telecommunications service operators leads to an increasing customer orientation and an ever increasing complexity. The technical consequence of the increased customer orientation is visible in the higher interest in flexibility engineering. The increasing complexity is becoming the major problem in telecommunication systems of this decade. To deal with this complexity two fundamental capabilities are used: abstraction and structuring. In general, models can be identified on any level of abstraction, e.g. high-level system behaviour models, high-level system architectural models and low-level architectural models. When system complexity increases, more levels of abstraction will be necessary to deal with this complexity. Various methods exist to define models at different levels of abstraction. In this paper three modelling methods are discussed. It is demonstrated that abstraction is used in a similar way in these modelling methods. One particular method for abstraction is the use of the object-oriented paradigm, a powerful approach for modelling as well as for implementation. Additional structuring methods based on considerations with respect to the functionality, however, remain indispensable in order to keep complexity under control. Those methods, stratification and segregation, are specifically relevant in high level architectural models.     

Domain–Specific High–Level Modeling and Synthesis for ATM Switch Prototyping

ATM switch, the core technology of an ATM networking system, is one of the major products in Fujitsu telecommunication business. However, current gate–level design methodology can no longer satisfy its stringent time–to–market requirement. It becomes necessary to exploit high–level methodology to specify and synthesize the design at an abstraction level higher than logic gates. This paper presents our prototyping experience on domain–specific high–level modeling and synthesis for Fujitsu ATM switch design. We propose a high–level design methodology using VHDL, where ATM switch architectural features are considered during behavior modeling, and a high–level synthesis compiler, MEBS, is prototyped to synthesize the behavior model down to a gate–level implementation. Since the specific ATM switch architecture is incorporated into both modeling and synthesis phases, a high–quality design is efficiently derived. The synthesis results shows that given the design constraints, the proposed high–level design methodology can produce a gate–level implementation by MEBS with about 15 percent area reduction in shorter design cycle when compared with manual design.     

一种优化的神经网络树异常入侵检测方法

本文提出了一种基于优化神经网络树(ONNT)的异常检测方法,在提高异常检测精确率的同时,增强异常检测模型学习结果的可理解性、可解释性。ONNT是一种具有二叉树结构的混合学习模型,二叉树的节点分裂遵循信息增益率准则;其中间节点嵌入了结构简单的感知器神经网络,能够根据当前节点上给定的子样本集和教师信号,选择较小的特征子集构建相对简单的局部决策曲面。本文提出的异常检测方法包括两个方面的性能优化:1）通过优化神经网络树(NNT)的中间节点,降低局部决策曲面的复杂度,从而使中间节点能在可接受的计算代价内表示成低复杂度的布尔函数或规则集,为实现学习结果的可解释性提供基础;2）通过优化学习模型的整体结构,降低所有中间节点的规则析取式的前件复杂度,从而提高学习结果的可理解性。实验的数值结果表明,与基于NNT的异常检测方法相比,本文提出的方法能够以简单的中间节点和相对精简的整体结构提高检测结果的可解释性和可理解性;与其他同类方法相比,基于ONNT的异常检测方法具有较高的检测精确率,且在一定程度上给出了对异常检测具有重大影响的一些特征信息。      

High-level modeling and analysis of the traffic alert and collisionavoidance system (TCAS)

We demonstrate a high-level approach to modeling, analyzing, and verifying complex safety-critical systems through a case study on the traffic alert and collision avoidance system (TCAS); an avionics system that detects and resolves aircraft collision threats. Due to the complexity of the TCAS software and the hybrid nature of the closed-loop system, the traditional testing technique of exhaustive simulation does not constitute a viable verification approach. Moreover, the detailed specification of the system software employed to date as a means toward analysis and verification neither helps in intuitively understanding the behavior of the system nor enables the analysis of the closed-loop system behavior. We advocate defining high-level hybrid system models that capture the behavior not only of the software but also of the airplanes, sensors, pilots, etc. In particular, we show how the core components of TCAS can be captured by relatively simple hybrid I/O automata, which are amenable to format analysis. We then outline a methodology for establishing conditions under which TCAS guarantees sufficient separation in altitude for aircraft involved in collision threats. The contributions of the paper are the high-level models of the closed-loop TCAS system and the demonstration of the usefulness of high-level modeling, analysis, and verification techniques