Computer-aided design of VLSI circuits

With the rapid evolution of integrated circuit (IC) technology to larger and more complex circuits, new approaches are needed for the design and verification of these very-large-scale integrated (VLSI) circuits. A large number of design methods are currently in use. However, the evolution of these computer aids has occurred in an ad hoc manner. In most cases, computer programs have been written to solve specific problems as they have exist and no truly integrated computer-aided desisn (CAD) systems exist for the design of IC's. A structured approach both to circuit desisn and to circuit verification, as well as the development of integrated design systems, is necessary to produce cost-effective error-free VLSI circuits. This paper presents a review of the CAD techniques which have been used in the design of IC's, as well as a number of design methods to which the application of computer aids has proven most successful. The successful application of design-aids to VLSI circuits requites an evolution from these techniques and design methods.     

Relationship between wafer fracture reduction and controlling during the edge manufacturing process

Given the trend towards wafers of a larger diameter, microelectronics circuits are driven by modern IC manufacturing technology. Silicon wafer breakage has become a major concern of all semiconductor fabrication lines because silicon wafer is brittle and high stresses are induced in the manufacturing process. Additionally, the production cost is increasing. Even a breakage loss of a few per cent drives up device costs significantly if wafers are broken near completion, but wafer breakage even near the beginning of the process is significant.In this paper, we first point out the approach for the characterization of silicon wafer failure strength empolying a simple drop test, thereby providing a better understanding of the stress accumulated in wafer bulk before failure.This study also presents a brand new method using a charge coupled device (CCD) to capture the cross-section image of the wafer at the wafer edge; the data measured at the edge can be used to diagnose overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in wafer bulk before failure.This work presents an approach for characterizing silicon wafer failure strength using a simple drop test, to improve our understanding of the stress accumulated in wafer bulk before failure. However, this work will describe many of the improvements that have resulted in the virtual elimination of wafer breakage due to unknown reasons. According to an analysis based on the material mechanical theory for the bevel lengths (A1, A2), the edge length and the bevel angle (θ) are optimized to design the edge profile of the produced wafer, to prevent wafer breakage. Restated, when proper material and process control techniques are utilized, silicon wafer breakage should be prevented. This work is the first to demonstrate the importance of understanding wafer strength using a simple mechanical approach.     

A rule-based VLSI process flow validation system with macroscopicprocess simulation

As the integration scale of very large-scale integration (VLSI) circuits increases, it is becoming increasingly difficult to design long and complex process flows because there is a great amount of knowledge required in VLSI process technology. To assist in process-flow design, a rule-based validation system has been developed. This system checks designed process flows by using process knowledge related to contamination, cleaning methods, and the various constraints between the wafer structure and the process or equipment. It can point out error conditions that lead to such destructive results as contamination of the process equipment. The system applies process knowledge, expressed as if/then rules, to the process conditions and to macroscopic wafer structures derived from rule-based simulation. Due to the complexity of VLSI multilayered structures, information related to wafer structure is very important. This information can be obtained by rule-based simulation of such various macroscopic attributes of wafer structure as substance, contamination, and layer thickness. The validation system can precisely check various process flows and substantially improve the efficiency and quality of process-flow design     

Relationship between wafer edge design and its ultimate mechanical strength

Due to its brittle nature, high stress-induced in manufacturing process, silicon wafer breakage has become a major concern for all semiconductor fabrication line. Furthermore, the production cost had increased in advanced technology day by day. Even a some-percent breakage loss drives device costs up significantly if wafers are broken near completion. Consequently, wafer breakage even near the beginning of the process is significant. In short words, silicon wafer breakage has become a major concern for all semiconductor fabrication lines, and so high stresses are easily induced in its manufacture process. The production cost is increasing even breakage loss of a few percent significantly drives device costs up, if wafers are broken near completion. Even wafer breakage near the beginning of the process is significant.In this paper, we first point out the approach for the characterization of silicon wafer failure strength employing a simple drop test, thereby providing a better understanding of the stress accumulated in wafer bulk before failure.This study also presents a brand new method using a charge coupled device (CCD) to capture the cross-section image of the wafer at the wafer edge; the data measured at the edge can be used to diagnose overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in wafer bulk before failure.A physical model would also be proposed to explain the results. This model demonstrates that the fracture rate of wafers can be reduced by controlling the uniformity of the difference between the front and rear bevel lengths during the wafer manufacturing process.     

On the way to plastic computation

The development of post silicon technologies based on organic materials consolidates the possibility to realize new devices and applications with unusual properties: flexibility, lightweight, disposability. Both materials and processes play a fundamental role in this new electronic framework and have been improved continuously in the last decades. In this contribution, a new perspective will be drawn by considering a complete technology platform that lead printed organic electronics technology from the basic device and materials to a manufacturing process flow, design tools and market applications development. The final goal of the proposed approach is the manufacturing of organic circuits with sub-micron feature size at low fabrication costs with high flexibility and application versatility by using additive manufacturing processes. The identification of suitable material features and process steps and the implementation of dedicated CAD tools in a complete workflow are here reported. Moreover, the feasibility of the adopted technology is demonstrated by the design of both digital and analog circuits. Multilayered structure devices, like Organic Thin Film Transistor (OTFT), are used to design complex architectures like arithmetic logic units and nonlinear oscillators.     

A new quantum effect model for practical device simulation

An increase in the complexity of VLSI design, especially in process integration, is leading to increased demands for technology CAD (TCAD). The quantum mechanical (QM) effect becomes very important with an increase in the channel impurity concentration. Several models for the QM effect have been proposed. However, it has been reported that these models had some problems. In this paper, a new QM model for a conventional device simulator is proposed. Applications of this model to NMOS and PMOS including the buried-channel are examined     

一种220 GHz滤波器的设计

基于电感膜片矩形波导滤波器设计方法和加工流程,设计了一个220 GHz带通滤波器。滤波器采用玻璃片—硅片—陶瓷片结构,由硅片形成电感膜片结构,玻璃片、陶瓷片键合在硅片上形成闭合的谐振腔,采用集成电路的制作工艺,在加工前分析了工艺特性,优化了滤波器尺寸,避免工艺对滤波器关键尺寸的影响。采用信号源、功率计进行测试,测试结果表明,滤波器在220 GHz具有通带特性,带内损耗约为7 dB。     

一种适于快速OPC的精确光刻胶剖面仿真算法

光刻仿真工具是描述实际工艺的有效工具。利用光刻仿真工具，能够准确地描述由掩模制造工艺、光刻胶曝光、显影、蚀刻所引起的光学邻近效应和畸变所导致的关键尺寸的变化。利用了改进的空间图像仿真及可变光强阈值模型来获得准确的硅片图形。改进的空间图像的基本思想是，用空间图像与一个高斯滤波器进行卷积，从而使图像较原来变得模糊，以此来模拟光刻胶的实际扩散效应。描述了一种适用于快速光学邻近校正（OPC）的准确的光刻胶剖面仿真算法。     

基于神经网络方法的半导体生产工艺优化

以提高生产成品率为目标,利用神经网络的非线性和容错性,对半导体芯片生产过程进行了分析和优化,具体内容如下：（１）使用神经网络方法建立模型,确定生产线上工艺参数和成品率之间的映射关系,构造以工艺参数为输入,成品率为输出的多维函数曲面．（２）对上述多维函数曲面进行搜索,搜索成品率最高的最优点,以该最优点的工艺参数值为依据确定工艺参数的规范值．（３）对工艺参数规范进行优化,在实际生产工艺中反复实践,直至达到提高成品率的目的．生产实践证明,神经网络的分析结果是合理的．根据神经网络分析提出的优化建议,有效地提高了工     

Technology transfer between VLSI design and software engineering: CAD tools and design methodologies

Recent research on the explicit transfer of technology used in computer-aided design (CAD) tools and design methodologies is reported. First, several examples are given of applications of these technologies to software engineering. Then, three research projects are described which focused on applying software engineering principles to the VLSI design process. They are: a methodology, language, and assessment tool for multilevel mixed-mode VLSI designs; a research project that explored the potential for transfer of software design methodologies for managing VLSI design complexity; and a specification technique for "modules" in a VLSI design that localizes the impact of changes to the design. Next, a CAD tool and design methodology are described which consider the design of software and hardware together, and apply common techniques to both. Finally, some observations are made on the appropriateness of technology transfer between VLSI design and software engineering.     

Model for yield and manufacturing prediction on VLSI designs foradvanced technologies, mixed circuitry, and memories

A yield model has been developed and validated for use in optimizing VLSI floorplanning in next generation products. The model successfully predicts yields and costs on a variety of products in CMOS, bipolar, and BiCMOS process flows from low cost DIP's and QFP's to more complex PGAs and flip chip package solutions. This paper discusses how the model was developed for use in evaluating the viability of next generation VLSI solutions. The model takes into account variables such as layout sensitivity, circuit redundancy, and learning curves in wafer, assembly, and test processing in determining the total manufacturing cost     

A software tool for the design of high power PiN diodes based on the numerical study of the reverse characteristics

A physically based model of power PiN diodes was developed to simulate the reverse voltage behavior with purpose of design optimization for specific application. The model includes process simulation and 2D drift-diffusion simulation of the defined geometrical diode structure. The process simulation was adjusted to obtain the same doping profile measured on a known sample. Since bulk silicon and dopants used in high power device production are different from those used in VLSI, various analytical models of impurity diffusion phenomena were considered and parameters calibration was carried out within the range found in the literature to obtain the best fit with measurements. Impact ionization coefficients of the reverse biased diode model were tuned by comparison with measurements on a reference device and exploited to study the dependence of breakdown voltage vs. various technological parameters.A simulation campaign for many different diode structures was conducted.An ad hoc interpolation algorithm was developed and applied for using measurement and simulation results in quick design of diode structures for specific application.     

Mechanical strength of 300 mm diameter silicon wafers at high temperatures: modeling and simulation

Under gravitational and thermal constraints of IC process technology, 300 mm diameter silicon wafers can partly relax via slip dislocation generation and propagation, degrading the electrical characteristics of the leading edge device. We present a force balance model to describe the strain relaxation in large wafer diameter, which includes heat transfer effects and the criterion for yielding under a plane stress state. The material attributes, e.g. oxygen and its state of aggregation, are taken into account. While the plastic deformation of silicon wafers caused by thermal stresses at high temperatures can be controlled by process design, the control of plastic deformation due to gravitational forces may be accomplished by equipment design. This system approach allows calculation of wafer mechanics and ramp rate profiles for an arbitrary high-temperature process. The quantitative theory proposed here provides guidance for computer simulation to configure stable slip-free wafer process flow under mechanical and thermal loads. Applications include high speed simulations for use in ‘what if’ experiments or initial simulations of large scale experimental sequences. The simulator developed can also be used by IC manufacturers to determine optimum wafer throughput and cycle times in front-end device processes.     

Defect clustering viewed through generalized Poisson distribution

It is shown that generalized double Poisson distributions provide a good basis for yield models when moderate spatial heterogeneity exists between chips of larger sizes, or when defects are almost randomly distributed. The model includes the average number and size of clusters as its parameters. On being tested with simulated as well as actual wafer particle maps, the model gave a significance level >0.95 in most of the cases. This model is simple and facilitates direct implementation of multilevel or hierarchical redundancy in regular VLSI/WSI designs. The strength of the proposed model lies in its simplicity and its ability to provide a physical explanation of the clustering process through its parameters. The model reflects the effects of the competition which can occur among defects in a cluster during wafer processing. Comparisons of yield predictions by various models for wafer maps with different spatial properties are reported     

The impact of supercomputers on IC technology development and design

Very large scale integration (VLSI) has evolved at an enormous rate, progressing from hundreds of components on an integrated circuit (IC) in the 1960's to a million components on a chip in the foreseeable future. This paper reviews some of the computer-aided design (CAD) tools that are essential for VLSI technology development and circuit design and that also require large amounts of computer resources. Specifically, we describe programs for process simulation, device simulation, and circuit simulation. This paper also reviews the impact of high-performance computing facilities on the development and use of these programs at AT & T Bell Laboratories.     

MAC控制器IP硬核的设计与验证

采用布局布线工具Encounter对MAC控制器IP硬核进行版图设计,版图设计完成后通过编辑StreamOut.map文件中层数导出符合Virtusoo工具要求的GDS文件,并基于Virtuso环境采用Calibre工具对MAC控制器IP硬核进行物理验证,对设计规则检查和版图与原理图一致性检查中存在的违规提出具体解决办法.通过物理验证后的版图导出def格式文件采用Star-RCXT工具进行寄生参数抽取,得到内部互连网络的详细寄生参数值用PrimeTime工具做精确时序分析.最终成功实现满足时序和制造工艺要求的MAC控制器IP硬核,达到设计的目标和要求.     

VLSI reliability challenges: from device physics to wafer scalesystems

The philosophical and practical differences between Japanese and US IC industries in regard to VLSI reliability, as well as recent research topics and new analysis methods such as wafer scale testing, are discussed. It is suggested that a new approach to VLSI reliability is needed in response to the paradigm shift being brought about by simple scaling limitations, increased process complexity and application of VLSI to advanced systems. An example of this shift is the movement from simple failure analysis by sampling the output of a manufacturing line to the building-in-reliability approach. To introduce and expand on the building-in reliability approach in VLSIs, the authors discuss the required deeper physical understanding of such important processes as hot-carrier effects, dielectrics and metallization     

The role of VLSI in multimedia

The opportunity to develop multimedia applications based on compressed video is the result of progress in three areas: standards, networking, and VLSI. Current video coding standards and their underlying algorithms use a variety of techniques to isolate and remove redundancies in the image sequence. Some of these techniques place severe demands on the underlying VLSI technology. Manufacturers of VLSI codecs have chosen a number of different architectural approaches. The advantages and disadvantages of each are discussed in the context of various applications with examples taken from existing or soon to be announced products. The AT&T AVP4000 chip set is described in some detail. Major design challenges included CAD tools for simulation and verification, packaging and the control of power dissipation