高输出阻抗多功能电流模式双二阶滤波器

提出了一种基于多输出端差动差分电流传送器的多功能电流模式滤波器电路结构。该电路用三个多输出端差动差分电流传送器，五个或四个接地电阻和两个接地电容，同时实现了反相和，或同相带通和低通或带通和高通滤波响应特性。分析并模拟了所提出的滤波器的传递特性，PSPICE仿真结果表明，所提出的电路方案正确有效。电路具有灵敏度低，输出阻抗高，滤波器固有频率ωo和品质因数Q相互独立可调，多功能的优点，适于实现全集成连续时间滤波器。     

基于多输出端差动差分电流传送器跳耦结构滤波器

提出了一种新颖的多输出端差动差分电流传送器（ＭＤＤＣＣ）及其ＣＭＯＳ实现电路,用计算机模拟比较了ＭＤＤＣＣ和第二代电流传送器（ＣＣⅡ）的特性;以ＭＤＤＣＣ构成了全差分式连续时间电流模式跳耦结构低通滤波器,分析并模拟了所提出的滤波器的特性,仿真结果表明所提出的电路方案正确有效;ＭＤＤＣＣ电路兼有差动放大器（ＤＤＡ）和ＣＣⅡ两者的优点,适于实现全集成连续时间滤波器。     

基于MOCCⅡ和CCCⅡ的三输入单输出滤波器的设计

设计一种基于多输出电流传送器（MOCCⅡ）和电流控制传送器（CCCⅡ）的二阶电流模式多功能滤波器,其电路结构简单,通过选择不同的输入端口,可以实现低通、带通、高通的功能,无源元件全部接地,便于集成且与VLSI工艺兼容。所设计的电路具有很低的灵敏度,最后对该电路进行PSpice仿真分析,理论分析和计算机仿真结果相符,表明电路方案正确可行。     

基于CCCⅡ与OTA的三输入单输出多功能电流模式滤波器

提出了一种采用电流传送器CCCⅡ与OTA相结合构成的电流模式三输入单输出多功能滤波器.电路仅使用一个CCCⅡ器件、一个OTA器件、两个接地电容和一个接地电阻.合理选择电路的三个输入端中不同的输入信号组合,即可在输出端得到低通、高通、带通、带阻和全通五种二阶瘟波器功能.所提出的电路结构简单,中心频率可调范围大,无源元件全部接地,产生的电路具有很低的灵敏度.理论分析和PSpice计算机仿真表明所提出电路方案的正确性.     

采用改进电流传送器的二阶电流滤波器

本文基于ＫＨＮ电路结构，使用第二代改进电流传送器，提出了二阶滤波器的电流模式实现电路。该电路能实现低通、带通、高通、全通、带阻及陷波等种二阶滤波器函数。同时民路具有输入电流滤波器函数。另外该电路也便于集成实现。     

通用有源电流模式滤波器

提出了两种通用有源电流模式滤波器：１．用两个电流传送器（ＣＣＩＩ）实现的电流模式三介滤波器新电路,选择不同的输入信号组合即能获得低通、高通、带通、陷波和全通五种二阶滤波函数;２．由ＣＣＩＩ和多输出地运算放大器（ＯＴＡ）实现的单输入多输出滤波器新电路、所提电路结构简单、中心频率ω０和品质因数Ｑ独立可调、无源元件人武部接地,滤波器特性参数对的元件灵敏度低,理论分析和计算机仿真表明所提电路方案正确。     

电压模式通用双二阶滤波器的新实现

本文提出了采用第二代电流传送器CC Ⅱ+/-构成的电压模式三输入、单输出多功能通用双二阶滤波电路。此电路通过选择不同的输入信号,可输出端得到电压模式二阶低通、高通、带通、陷波和全通五种滤波功能。每种滤波功能的滤波器的固有角频率ωp和品质因素Qp可实现正交调节,所有滤波器都具有低的无源灵敏度,计算机仿真结果表明了通用滤波器电路的正确性和可行性。     

新颖的电压模式通用双二阶滤波器

提出了采用第二代电流传送器构成的电压模式三输入、单输出多功能通用双二阶滤波电路,该电路通过选择不同的输入信号,可在输出端得到电压模式二阶低通、高通、带通、陷波和全通五种滤波功能。每种滤波功能的滤波器的固有角频率ωｐ和品质因素Ｑｐ可实现正交调节,所有滤波器都具有低的无源和有源灵敏度。     

一种新颖的CMOS差动电压电流传送器及其应用

针对第二代电流传送器（ＣＣⅡ）的不足之处，提出了一种新颖的差动电压输入电流传送器（ＤＶＣＣ）。首先给出了ＤＶＣＣ的ＣＭＯＳ集成工艺实现方法，并分析了其工作原理。然后给出其具体应用实全儿ＰＳＰＩＣＥ的模拟结果，验证了实现和应用ＤＶＣＣ的可行性。     

一种新颖的基于CCCⅡ的多功能滤波器

提出了一种采用新的电流控制传送器(CCCII)积木块构成的电流模式单输入、多输出的多功能滤波器电路,它仅由4个CC器件和2个电容构成,选择电路3个输出端中的1个或它们的组合,即可实现5种基本的二阶滤波功能,给出了电路的PSPICE仿真结果,验证了理论分析的正确性。     

电流模式反激变换器中功率限制电路的设计

讨论电流模式反激变换器的工作原理与优点,重点分析反激变换器中的过功率保护模块的功能与实现方式。提出在过功率保护电路中利用斜坡电压取代传统的固定电压,以达到不同输入电压下的恒定功率限制。基于CMOS工艺设计了相应的斜坡电压产生电路,该电路结构简单,可广泛适用于各类反激开关电源控制电路。最后并对电路进行了仿真。     

一种新型的宽线性范围差分电压输入电流传输器及其应用

设计了一种带有共模检测电路的宽线性范围差分电压输入电流传输器(DVCCⅡ).所提出的电路具有动态的长尾电流的差分对,可获得较大的动态线性输入范围.所提出的电路可以得到精确跟随特性和宽线性输入范围,且比较已有电路具有低电压低功耗等特点.采用SMIC 0.18μm工艺,用Spectre对电路进行仿真,电源电压是1.8 V,...     

一种新型CMOS电流模带隙基准源的设计

设计了一种新型电流模带隙基准源电路和一个3bit的微调电路。该带隙基准源可以输出可调的基准电压和基准电流,避免了在应用中使用运算放大器进行基准电压放大和利用外接高精度电阻产生基准电流的缺点,同时该结构克服了传统电流模带隙基准源的系统失调、输出电压的下限限制以及电源抑制比低等问题。该带隙基准源采用0.5μm CMOS混合信号工艺进行实现,有效面积450μm×480μm;测试结果表明在3 V电源电压下消耗1.5mW功耗,电源抑制比在1 kHz下为72dB,当温度从-40～85°C变化时,基准电压的有效温度系数为30×10-6V/°C。该带隙基准电路成功应用在一款高速高分辨率模数转换器电路中。     

A new high-speed, high-resolution open-loop CMOS sample and hold

A new open loop, high resolution CMOS sample and hold (S/H) circuit is introduced in this article. This circuit is constructed based on a new method which leads to a great reduction in dependency of the storing charge of the holding capacitors to the charge injection of transistors. It is a combination of dummy switches and auxiliary capacitors in order to decrease the voltage spikes that are produced during the sampling mode. Due to the high linearity feature of our proposed design in comparison with previous works, it is reached to a great improvement in signal to noise and distortion ratio up to about 15 dB and it’s ENOB is equivalent with about 16 bits. Another advantages of our proposed design are it’s lower power dissipation and it’s high input voltage range. Also the optimum functionality of our proposed circuit does not damaged by the threshold voltage’s variations in different corners. As our proposed S/H circuit has been designed in open loop structure, it is suitable for high speed applications.     

A Novel Ultra Low Power High Performance Atto-Ampere CMOS Current Mirror with Enhanced Bandwidth

A novel CMOS atto-ampere current mirror （AACM） is proposed which reaches the minimum yet reported current range of 0.4 aA. Operation of this circuit is based on the source voltage modulation instead of the conventionally used gate voltage modulation which interestingly prevents usage of commonly required voltage shifting in those circuits. The proposed circuit has a simple structure prohibiting large chip area consumption which consumes extremely low power of 1.5 μW. It is thus the best choice for ultra low power low voltage （ULPLV） applications. By using a very simple frequency compensation technique, its bandwidth is widened to 15.8 kHz. Simulation results in SMIC （Semiconductor Manufacturing International Corporation） 0.18 μm CMOS technology with Hspice are presented to demonstrate the validation of the proposed current mirror.     

Design to suppress return-back leakage current of charge pump circuit in low-voltage CMOS process

A new charge pump circuit has been proposed to suppress the return-back leakage current without suffering the gate-oxide reliability problem in low-voltage CMOS process. The four-phase clocks were used to control the charge-transfer devices turning on and turning off alternately to suppress the return-back leakage current. A test chip has been implemented in a 65-nm CMOS process to verify the proposed charge pump circuit with four pumping stages. The measured output voltage is around 8.8 V with 1.8-V supply voltage to drive a capacitive output load, which is better than the conventional charge pump circuit with the same pumping stages. By reducing the return-back leakage current and without suffering gate-oxide overstress problem, the new proposed charge pump circuit is suitable for applications in low-voltage CMOS IC products.     

一种电压控制CMOS电调谐第二代电流传输器(ECCⅡ)

提出了一种电压跟随能力强、功耗低、调节范围大的CMOS电调谐第二代电流传输器(ECCⅡ),通过引入对称的CMOS电流舵电路,保证了电流传输精度,电流增益连续可调,调节因子-2≤K≤2,同时避免了电流镜的过多使用,减小了电流损耗.采用电压调控方式,增大了电流输入范围;将电流输入端和电流加减电路隔离,保证了精确的电压跟随能力.采用TSMC 0.35μm工艺参数,在±1.5V电源供电的条件下对电路进行了Hspice模拟,VY/VX,和IZ/IX的-3 dB带宽分别为83.5 MHz和136 MHz,功耗为1.7515 mW.该电路在可调谐连续时间电流模式滤波器的设计中有广泛的应用前景.     

A novel bulk-input low voltage and low power four quadrant analog multiplier in weak inversion

A new four quadrant voltage mode bulk input analog multiplier is presented .The proposed multiplier is designed to operate in weak inversion. Multiplication is done by driving the bulk terminals of the MOS devices which offers linear dynamic range of ±80 mV. The simulation shows, it has a linearity error of 5.6 %, THD of nearly 5 % and ?3 dB band width of 221 kHz. Total power consumption is very low i.e. 714 nW. The circuit operates at a supply voltage of 0.5 V and is designed using 180 nm CMOS technology. It is suitable for low power bioelectronics and neural applications.     

Novel high speed circuit structures for BiCMOS environment

Novel high speed BiCMOS circuits including ECL/CMOS, CMOS/ECL interface circuits and a BiCMOS sense amplifier are presented. A generic 0.8 μm complementary BiCMOS technology has been used in the circuit design. Circuit simulations show superior performance of the novel circuits over conventional designs. The time delays of the proposed ECL/CMOS interface circuits, the dynamic reference voltage CMOS/ECL interface circuit and the BiCMOS sense amplifier are improved by 20, 250, and 60%, respectively. All the proposed circuits maintain speed advantage until the supply voltage is scaled down to 3.3 V     

CMOS exponential function generator

A new CMOS exponential function generator is presented. The proposed circuit is compact, with low power and wide dynamic range. The proposed circuit has been fabricated in a 0.50 /spl mu/m CMOS process. Experimental results show that the output range of the proposed exponential function generator can be more than 15 dB with the linear error less than /spl plusmn/ 0.5 dB. The supply voltage is /spl plusmn/ 1.5 V and the power dissipation is less than 0.4 mW. Experimental results are given to demonstrate the proposed circuit.