A differential-input,differential-output current mode operational amplifier

A current operational amplifier with differential input and differential output is described. The amplifier is based on the parallel connection of a CCII+ current conveyor and a CCII? current conveyor followed by a differential output transconductance gain stage. The performance of the amplifier is analysed and experimental results obtained from an implementation using standard operational amplifiers and current mirrors realized using transistor arrays are presented and compared to the theoretical analysis. It is concluded that the static small signal open loop gain and the frequency response matches the performance of conventional voltage operational amplifiers. The input offset and bias errors and the common mode rejection are shown to be strongly dependent on the matching accuracy of the current mirrors used in the conveyors. The proposed configuration can easily be integrated into a monolithic amplifier in either CMOS or bipolar technology.     

A Low-Voltage Fully Differential Constant-Gm Rail-to-Rail CMOS Operational Amplifier

A low-voltage fully differential CMOS operational amplifier withconstant-g_mand rail-to-rail input and output stages ispresented. It is the fully differential version of a previously realizedsingle-ended operational amplifier where a novel circuit to ensure constanttransconductance has been implemented [1]. The input stage is a rail-to-railstructure formed by two symmetrical OTAs in parallel (the input transistorsare operating in weak inversion). The class-AB output stages have also afull voltage swing. A rail-to-rail input common mode feedback structureallows the output voltage control. Measurements in a 0.7 µ standardCMOS process with threshold voltages of about 0.7 V have been done. Theminimum experimental supply voltage is about 1.1 V. The circuit provides a60 dB low frequency voltage gain and about 1.5 MHz unity gain frequency fora total power consumption of about 0.72 mW at a 1.5 V supply voltage.     

微电容超声换能器的前端专用集成电路设计

针对微电容超声换能器(CMUT)微弱电流信号检测的要求,设计了一种用于CMUT的前端专用集成电路——运算放大器(OPA)电路。运算放大器电路采用两级放大结构,第一级采用全差分折叠-共源共栅结构,输出级采用AB类控制的轨到轨输出级,在运算放大器电路反相输入端和输出端通过一个反馈电阻实现CMUT电流信号到电压信号的转换。采用GlobalFoundries 0.18μm的标准CMOS工艺进行了仿真设计和流片,芯片尺寸为226μm×75μm。仿真结果表明,运算放大器的开环增益为62 dB,单位增益带宽为30 MHz,在3 MHz处的输入参考噪声电压为2.9μV/Hz^1/2,电路采用±3.3 V供电,静态功耗为11 mW。测试结果表明仿真与实测结果相符,该运算放大器电路能够实现CMUT微弱电流信号检测功能。     

一种基于BiFET工艺的高输入阻抗运算放大器

针对CMOS运算放大器存在的输入失调电压高、噪声性能差等问题,提出了一种基于双极结型场效应晶体管(BiFET)工艺的高输入阻抗运算放大器。采用P沟道JFET差分对作为输入级,实现了pA量级的极低输入偏置电流/失调电流和nV/Hz量级的极低输入噪声电压谱密度。采用双极晶体管构成的共集-共射增益级和互补推挽输出级,实现了100 dB的开环增益、10 V/μs的输出电压转换速率和10 MHz的带宽。该运算放大器适用于对微弱模拟信号的采集和放大。     

一种含理想运算放大器电路的讨论

为进一步明确含理想运算放大电路的有关概念和运算放大器的特性,本文从计算机仿真和理论分析两个方面,对一个含理想运算放大器电路的输入输出特性进行了模拟和推导.结果表明该电路在线性输入范围内是一电压跟随器,若超出线性输入范围,则输出波形严重失真;带反馈电路与开环电路相比较表现为线性输入范围扩大、电压增益减小,而这正是电路负反馈的特性.因此,不能简单的把接在运算放大器同相输入端的反馈视为正反馈.     

A THD-reduction high-efficiency audio amplifier using inverter-based OTAs with filter-output feedback

This paper presents an integrated low-voltage THD-reduction high-efficiency class-D audio amplifier using inverter-based operational transconductance amplifiers (OTAs). We propose a negative feedback loop which can compensate for external perturbations and improving output precision. The compensator increases the audio-frequency loop gain, and leads to a better rejection of audio-frequency disturbances. The use of inverter-based OTA and comparator provides low-voltage operation and low-power dissipation. The audio amplifier operates with a 1.5 V supply voltage with maximum power efficiency of 90%. The proposed class-D amplifier was implemented using a TSMC 0.18-μm 1P6M CMOS process, and the active chip area is 1.87 mm².     

Low power DDA-based instrumentation amplifier for neural recording applications in 65 nm CMOS

The low power instrumentation amplifier (IA) presented in this paper has been designed to be the front-end of an integrated neural recording system, in which common-mode rejection ratio (CMRR), input referred noise and power consumption are critical requirements. The proposed IA topology exploits a differential-difference amplifier (DDA) whose differential output current drives a fully differential, high-resistance, transimpedance stage, with an embedded common-mode feedback loop to increase the CMRR. This stage is followed by a differential-to-single-ended output amplifier. Low-power operation has been achieved by exploiting sub-threshold operation of MOS transistors and adopting a supply voltage of 1 V. Simulation results in a commercial 65 nm CMOS technology show a 1 Hz to 5 kHz bandwidth, a CMRR higher than 120 dB, an input referred noise of 8.1 μVrms and a power consumption of 1.12 μW.     

A 100-dB CMRR CMOS Operational Amplifier With Single-Supply Capability

A CMOS operational amplifier that has a common-mode rejection ratio (CMRR), a power-supply rejection ratio (PSRR), and gain above 100 dB for each of these parameters is described. This is achieved by combining a high output-impedance tail current source with a stable drain-source voltage of the input transistors. The common-mode input signal range includes the negative rail. This is obtained by controlling the bulk bias of the input and cascoding transistors. The amplifier consists of two gain stages connected via cascoded current mirrors. The gain is improved by using gain boost in the current mirrors, and by the suppression of impact ionization current in the output stage     

High-temperature characterisation and analysis of leakage-current-compensated,low-power bandgap temperature sensors

This paper presents a low-power, high-performance current-feedback instrumentation amplifier (CFIA) for portable bio-potential sensing applications. Noise analysis is performed to assign an optimized current for the input stage of the amplifier. Analysis on selecting nested chopping frequencies is performed, further reducing 1/f noise and the residual offset. Enhanced power efficiency is achieved by sharing cascode branches and using a Class-AB output stage. Through these methods, a good balance between noise performance and other parameters such as output ripples and power consumption of the ripple reduction feedback loop (RRFL) is achieved. The amplifier is developed using a 1-poly 6-metal 0.18 μm CMOS process. Three gain stages with a gain-boosting input stage provide a low-frequency, open-loop gain >250 dB. When configured to a closed-loop gain of 60 dB, the amplifier achieves a noise voltage density of 18 \({\text{nV}}/\sqrt {{\text{H}}z}\) and a 1/f noise corner of 3 Hz. With a current of 75 μA and a supply voltage of 3.3 V, a CMRR of 110 dB and a PSRR of 120 dB are achieved, with an average input offset of about 6.5 μV. The amplifier achieves a state-of-art noise efficiency factor of 4.2. Practical application of the CFIA is demonstrated with an in vivo electrocardiogram detection.     

基于最小电流选择的运算放大器设计

设计了一种工作电压为3V恒跨导满幅CMOS运算放大器,针对轨对轨输入级中存在的跨导不恒定和简单AB类输出级性能偏差这2个问题,提出了利用最小电流选择电路来稳定输入级的总跨导;浮动电流源控制的无截止前馈AB类输出级实现了运放的满幅输出,同时减小了交越失真。该电路通过HSpice进行仿真验证,在0～3V输入共模范围内,输入级跨导的变化小于3.3%,开环增益为93dB,单位增益带宽为8MHz,相位裕量为66°。     

电源自适应Rail-to-Rail CMOS运算放大器

基于CSMC 0.6 μm标准CMOS工艺,实现了一种电源自适应Rail-to-Rail CMOS运算放大器,其输入级从原理上变“被动地“适应低电压为“主动地“要求低电压.当外部电源电压在2.1V到3.2 V变化时,内部电源电压稳定在1.68 V,最大偏差为5.4%.这样,内部电源电压自适应地稳定在“相交条件“,实现了输入级的跨导Gm为常数:在整个共模(CM)电压变化范围内,输入级跨导的最大变化为9%.Rail-to-rail输出级用两个折叠网格和AB类反馈控制结构实现,使输出级的最低电源电压降到Vgs 2Vds,并使输出静态电流最小.     

一种适用于高速高精度流水线ADC的放大器

本文提出了一种新颖的放大器结构.它由两部分组成:前面为跨导放大器,后面则是由电阻反馈形成的跨阻放大器,两种放大器的组合构成了具有高输入阻抗、低输出阻抗的电压放大器.与普通放大器不同的是,在我们设计的工作条件下,它输出端的极点几乎不受负载电容的影响.用该放大器作为预放大级,驱动一单级主放大器所构成的两级运放在负载电容为4pf的情况下实现了超过1GHz的增益带宽积,瞬态分析的结果表明它可以在10ns内达到0.01%的精度(闭环增益为8),而功耗仅有25mW,远低于同性能其他结构的放大器,非常适合作为高速高精度流水线模数转换器中的首级余量放大器使用.     

一种用于水听器电压检测的模拟前端电路

提出了一种用于水听器电压检测的模拟前端电路,包括低噪声低失调斩波运算放大器,跨导电容(gm-C)低通滤波器,增益放大器三部分主体电路;低噪声低失调斩波运算放大器用于提取水听器前端传感器输出的微弱电压信号;gm-C低通滤波器用于滤除电压信号频率外的高频噪声和高次谐波;最后经过增益放大器放大至后级模数转换器的输入电压范围,输出数字码流;芯片采用台积电(TSMC)0.18μm单层多晶硅六层金属(1P6M)CMOS工艺实现。测试结果表明,在电源电压1.8 V,输入信号25 kHz和200 kHz时钟频率下,斩波运放输入等效失调电压小于110μV;整体电路输出信号动态范围达到80 dB,功耗5.1 mW,满足水听器的检测要求。     

二极管型非制冷红外探测器的前端电路设计

设计了一种二极管型非制冷红外探测器的前端电路,该电路采用Gm-C-OP积分放大器的结构,将探测器输出的微弱电压信号经跨导放大器(OTA)转化为电流信号,再经电容反馈跨阻放大器(CTIA)积分转化为电压信号输出。该OTA采用电流反馈型结构,可以获得比传统OTA更高的线性度和跨导值。输入采用差分结构,可以有效地消除环境温度及制造工艺对探测器输出信号的影响。电路采用0.35 m CMOS工艺进行设计并流片,5 V电源电压供电。Gm-C-OP积分放大器总面积0.012 6 mm2,当输入差分电压为0~5 mV时,测试结果表明:OTA跨导值与仿真结果保持一致,Gm-C-OP积分放大器可实现对动态输入差分信号到输出电压的线性转化,线性度达97%,输出范围大于2 V。     

1.2-V CMOS op-amp with a dynamically biased output stage

A very low-voltage operational amplifier in a standard CMOS process with a 0.75 V threshold voltage is presented. It uses a novel dynamically biased output stage based on the switched-capacitor approach. Thanks to this, drive performance is greatly improved and accurate current control is also achieved. The amplifier is capable of working with a power supply as low as 1.2 V while providing a -74 dB total harmonic distortion with a 700 mV peak-to-peak output voltage into a 500 Ω and 20 pF output load. The open-loop gain and the gain-bandwidth product are higher than 90 dB and 2.2 MHz, respectively     

A low-noise amplifier with automatic gain control and anticlipping control in CMOS technology

A CMOS low-noise amplifier (LNA) with two variable gain ranges of 6 and 9 dB is presented. Variable gain is realized by using linearized MOS resistive circuits (MRCs) as voltage-controlled resistors. One of these resistors is located in the feedback loop of a transresistance output stage and the other is in the bias current generator of the transconductance input stage. Using compatible lateral bipolar transistors (CLBTs) in the fully differential transconductance input stage, the circuit takes advantage of the linear dependence of transconductance on bias current. The equivalent noise is 14 nV/ square root Hz and free from 1/f noise in the voice band. The circuit was integrated in a 2- mu m CMOS process and has an active area of 0.8 mm/sup 2/.<>     

A 1.5-V high drive capability CMOS op-amp

A novel CMOS operational amplifier with a 1.5 V power supply is presented. It is based on a folded-mirror transconductance amplifier and a high-efficiency output stage. The amplifier achieves an open-loop gain and a gain-bandwidth product higher than 65 dB and 1 MHz, respectively. In addition, a 1 V peak-to-peak output voltage into a 500 Ω and 50 pF output load is provided with a total harmonic distortion of -77 dB. This performance was achieved using maximum aspect ratios of 120/1.2 and 360/1.2 for the NMOS and PMOS transistors, respectively, and a quiescent current as low as 60 μA for the driver transistors. The amplifier was implemented in a standard 1.2 μm CMOS process with threshold voltages around 0.8 V. It dissipates less than 300 μW     

一种适合VLSI库的Rail-to-Rail运算放大器

介绍了一种适于 VLSI库单元的轨到轨 (Rail-to-Rail)运算放大器。低电压、低功耗、输入输出动态幅度达到 Rail-to-Rail的运放模块是研究的核心。文章分析了该运放模块的输入、输出级 ,并分析了 cascodedMiller频率补偿技术。芯片采用新加坡特许半导体制造公司 0 .6μm N阱 CMOS工艺 ,芯片面积 0 .0 2 4mm2 。测试结果表明 :该运放模块在 3 V工作电压下直流增益 90 d B,共模输入范围 -0 .4～ 4V,输出动态范围 0～ 2 .9V,单位增益带宽 7MHz,相位裕量 70°,静态功耗仅有 0 .3 m W,特别适合作为 VLSI的库单元     

1-V rail-to-rail operational amplifiers in standard CMOS technology

The constraints on the design of CMOS operational amplifiers with rail-to-rail input range for extremely low supply voltage operation, are addressed. Two design approaches for amplifiers based on complementary input differential pairs and a single input pair, respectively, are presented. The first realizes a feedforward action to accommodate the common-mode (CM) component of the input signals to the amplifier input range. The second approach performs a negative feedback action over the input CM signal. Two operational amplifiers based on the proposed approaches have been designed for 1-V total supply operation, and fabricated in a standard 1.2-μm CMOS process. Experimental results are provided and the corresponding performances are discussed and compared     

一种电流跟踪补偿的输入输出全摆幅运算放大器

介绍了一种工作在2.5V电压下、具有全摆幅输入与输出功能的两级CMOS运算放大器。通过一种简单有效的电流跟踪电路实现了输入跨导恒定的要求，这样使得频率补偿变得容易实现；为了降低功耗，输入级工作在弱反型区：输出级采用带有前馈控制电路的AB类输出电路，实现了输出信号的轨至轨。电路具有结构简单、功耗低、面积小、性能高等优点。