The analysis of the electrical characteristics and interface state densities of Re/n-type Si Schottky barrier diodes at room temperature

The main electrical characteristics of current-voltage (I-V) and capacitance-voltage (C-V) measurements at room temperature of the Re/n-type Si Schottky barrier diodes prepared by pulsed laser deposition (PLD) method have been examined. The values of the basic electrical properties such as forward saturation current (I_o), ideality factors (n), barrier heights (Ф_bo), rectification ratio (RR) and series resistances (R_S) were obtained from I-V and C-V measurements using different calculation methods. At low voltages (V ≤ 0.3 V), the electrical conduction was formed to take place by thermionic emission, whereas at high voltages (V > 0.3 V), a space charge limited conduction mechanism was shown. Furthermore, the interface state densities (N_SS) as a function of energy distribution (E_SS- E_V) was obtained from the I-V data by taking into account the bias dependence of the effective barrier height (Φ_b) for the Re/n-type Si Schottky barrier diodes.     

An investigation of electrical and structural properties of Ni-germanosilicided Schottky diode

Ni-germanosilicided Schottky barrier diode has been fabricated by annealing the deposited Ni film on strained-Si and characterized electrically in the temperature range of 125 K–300 K. The chemical phases and morphology of the germanosilicided films were studied by using scanning electron microscopy (SEM), cross-sectional transmission electron microscopy (TEM) and energy dispersive spectroscopy (EDS). The Schottky barrier height (_b), ideality factor (n) and interface state density (D_it) have been determined from the current–voltage (I–V) and capacitance–voltage (C–V) characteristics. The current–voltage characteristics have also been simulated using SEMICAD device simulator to model the Schottky junction. An interfacial layer and a series resistance were included in the diode model to achieve a better agreement with the experimental data. It has been found that the barrier height values extracted from the I–V and C–V characteristics are different, indicating the existence of an in-homogeneous Schottky interface. Results are also compared with bulk-Si Schottky diode processed in the same run. The variation of electrical properties between the strained- and bulk-Si Schottky diodes has been attributed to the presence of out-diffused Ge at the interface.     

Effect of annealing temperature on the electrical characteristics of Platinum/4H-SiC Schottky barrier diodes

Pt/4H-SiC Schottky barrier diodes have been fabricated to investigate the effect of annealing on the electrical characteristics of the fabricated devices. The parameters such as barrier height, ideality factor and donor concentration were deduced from the current–voltage (I–V) and the capacitance–voltage (C–V) measurements at room temperature. Diodes showed non-ideal behaviour like high value of ideality factor and lower value of barrier height. A barrier height of 1.82?eV was obtained from C–V measurements and it was 1.07?eV when obtained from the I–V measurements with ideality factor 1.71 for as-deposited diodes at room temperature. The diodes, therefore, were annealed in the temperature range from 25°C to 400°C to observe the effect of annealing temperature on these parameters. Schottky barrier height and ideality factors were found to be temperature-dependent. After rapid thermal annealing upto 400°C, a barrier height of 1.59?eV from C–V measurements and the value of 1.40?eV from I–V measurements with ideality factor 1.12 were obtained. Barrier heights deduced from C–V measurements were consistently larger than those obtained from I–V measurements. To come to terms with this discrepancy, we re-examined our results by including the effect of ideality factor in the expression of the barrier height. This inclusion of ideality factor results in reasonably good agreement between the values of barrier height deduced by the above two methods. We believe that these improvements in the electrical parameters result from the improvement in the quality of interfacial layer.     

Determination of the absolute value of the semiconductor surface potential by the quasi-static capacitance-voltage characteristics of an MIS structure

A simultaneous analysis of the derivatives C_V′V_g of the experimental and ideal quasi-static capacitance-voltage characteristics (plotted as a function of the normalized differential capacitance of a metal-insulator-semiconductor (MIS) structure) allows identification of regions within the semiconductor band gap E_g, in which interface states are virtually aTSent and the relation between the surface potential ψ_S of the real semiconductor and the voltage V_g applied to the MIS structure may be readily ascertained. This allows an accurate enough determination of the additive constants ψ_S0(V_g0) necessary to calculate the dependence ψ_S(V_g) in the entire range of V_g by numerical integration of the experimental quasi-static C-V characteristic. The comparison of this dependence with the ideal one characterizes in detail the integral electronic properties of the semiconductor-insulator heterojunction: the E_g-averaged density of interface states, the qualitative pattern of their distribution over the band gap, and the flat-band voltage V_FB and its components caused by a charge fixed in the undergate insulator and a charge localized at boundary states. A high accuracy of the V_FB measurements allows detection of even a weak physical response of MIS structures to external factors or to variations in the heterojunction technology. Results of such an analysis for a typical SiO₂/Si interface of an n-Si-MOS (metal-oxide-semiconductor) structure are considered. The application of C_V′-C_V diagrams for analyzing the high-frequency C-V characteristics is considered.     

The forward bias current density–voltage–temperature (J–V–T) characteristics of Al–SiO2–pSi (MIS) Schottky diodes

Metal–insulator–semiconductor Schottky diodes were fabricated to investigate the tunnel effect and the dominant carrier transport mechanism by using current density–voltage (J–V) and capacitance–voltage (C–V) measurements in the temperature range of 295–370?K. The slope of the ln?J–V curves was almost constant value over the nearly four decades of current and the forward bias current density J is found to be proportional to J_o (T) exp(AV). The values of N_ss estimated from J–V and C–V measurements decreased with increasing temperature. The temperature dependence of the barrier heights obtained from forward bias J–V was found to be entirely different than that from the reverse bias C–V characteristics. All these behaviours confirmed that the prepared samples have a tunnel effect and the current transport mechanism in the temperature range of 295–370?K was predominated by a trap-assisted multi-step tunnelling, although the Si wafer has low doping concentration and the measurements were made at moderate temperature.     

Characterization by Internal Photoemission Spectroscopy of Single-Crystal CVD Diamond Schottky Barrier Diodes

Internal photoemission spectroscopy measurements have been performed to study the electrical characteristics of Schottky diodes on boron-doped single-crystalline chemical vapor deposited (SC-CVD) diamond. These measurements were compared with current–voltage (I–V) and current–temperature (I–T) measurements. Schottky contact barrier heights and ideality factors have been measured on Schottky contacts formed on four samples with Au, Ni, and Al contact metallizations. I–V and I–T measurements were performed in the temperature range from 300 K to 500 K. The internal photoemission method, which is less influenced by local variations in the Schottky barrier height than the other two methods, yielded the highest values of Schottky barrier heights to p-type material: Φ_B = 1.78 eV to 2.10 eV, depending on the choice of contact metal and sample boron concentration.     

Accurate surface potential determination in Schottky diodes by the use of a correlated current and capacitance voltage measurements.Application to n-InP

Based on current voltage(I-V_g) and capacitance voltage(C-V_g) measurements,a reliable procedure is proposed to determine the effective surface potential V_d(V_g) in Schottky diodes.In the framework of thermionic emission,our analysis includes both the effect of the series resistance and the ideality factor,even voltage dependent. This technique is applied to n-type indium phosphide(n-InP) Schottky diodes with and without an interfacial layer and allows us to provide an interpretation of the observed peak on the C-V_g measurements.The study clearly shows that the depletion width and the flat band barrier height deduced from C-V_g,which are important parameters directly related to the surface potential in the semiconductor,should be estimated within our approach to obtain more reliable information.     

Passivation of Surface and Interface States in AlGaN/GaN HEMT Structures by Annealing

The Ni/AlGaN interfaces in AlGaN/GaN Schottky diodes were investigated to explore the physical origin of post-annealing effects using electron beam induced current (EBIC), current–voltage (I–V) characteristics, and X-ray photoelectron spectroscopy (XPS). The EBIC images of the annealed diodes showed that the post-annealing process reduces electrically active states at the Schottky metal/AlGaN interfaces, leading to improvement of diode performance, for example a decrease in reverse leakage current and an increase in Schottky barrier heights. Pulsed I–V characteristics indicate the Fermi level is up-shifted after annealing, resulting in a larger sheet carrier density at the AlGaN/GaN interface. Unintentional oxidation of the free AlGaN surface during the post-annealing process, revealed by XPS analysis, may prevent electron trapping near the drain-side of the gate edges. We suggest that the post-annealing process under an optimized conditions can be an effective way of passivating AlGaN/GaN heterojunction field-effect transistors.     

Analysis of interface states and series resistance of MIS Schottky diodes using the current-voltage (I-V) characteristics

The purpose of this paper is to analyze interface states in Al/SiO₂/p-Si (MIS) Schottky diodes and determine the effect of SiO₂ surface preparation on the interface state energy distribution. The current-voltage (I-V) characteristics of MIS Schottky diodes were measured at room temperature. From the I-V characteristics of the MIS Schottky diode, ideality factor (n) and barrier height (Φ_B) values of 1.537 and 0.763 eV, respectively, were obtained from a forward bias I-V plot. In addition, the density of interface states (N_ss) as a function of (E_ss-E_v) was extracted from the forward bias I-V measurements by taking into account both the bias dependence of the effective barrier height (Φ_e), n and R_s for the MIS Schottky diode. The diode shows non-ideal I-V behaviour with ideality factor greater than unity. In addition, the values of series resistance (R_s) were determined using Cheung’s method. The I-V characteristics confirmed that the distribution of N_ss, R_s and interfacial insulator layer are important parameters that influence the electrical characteristics of MIS Schottky diodes.     

Electrical characteristics of Pd Schottky contacts on ZnO films

The electrical characteristics of Pd Schottky contacts on ZnO films have been investigated by current-voltage (I–V) and capacitance–voltage (C–V) measurements at different temperatures. ZnO films of two thicknesses (400 nm and 1000 nm) were grown by DC-magnetron sputtering on n-Si substrates. The basic structural, optical and electrical properties of these films are also reported. We compared the two Schottky diodes by means of characteristic parameters, such as rectification ratio, ideality factor (η), barrier height (Φ_b) and series resistance and obtained better results for the 1000 nm-ZnO Schottky diodes. We also discussed the dependence of I‐V characteristics on temperature and the two distinct linear regions observed at low temperatures are attributed to the existence of two different inhomogeneous barrier heights. From I–V plots in a log-log scale we found that the dominant current-transport mechanism at large forward bias is space-charge limited current (SCLC) controlled by the presence of traps within the ZnO bandgap. The existence of such traps (deep states or interface states) is demonstrated by frequency-dependent capacitance and deep-level transient spectroscopy (DLTS) measurements.