钟控传输门绝热逻辑电路和SRAM的设计

本文利用NMOS管的自举效应设计了一种新的采用二相无交叠功率时钟的绝热逻辑电路——钟控传输门绝热逻辑电路,实现对输出负载全绝热方式充放电.依此进一步设计了一种新型绝热SRAM,从而可以以全绝热方式有效恢复在字线、写位线、敏感放大线及地址译码器上的大开关电容的电荷.最后,在采用TSMC 0.25 μ m CMOS工艺器件参数情况下,对所设计的绝热SRAM进行HSPCIE模拟,结果表明,此SRAM逻辑功能正确,低功耗特性明显.     

三值钟控传输门绝热逻辑电路研究

通过分析开关一信号理论和绝热电路工作原理及结构,提出三值钟控传输门绝热逻辑(Ternary Clocked Transmission Gate Adiabatic Logic,TCTGAL)电路设计方案.该方案利用NMOS管自举效应和CMOS-1atch结构对输出负载进行充放电,并通过NMOS管栅漏并接对输出降压限幅;...     

绝热电路三要素理论及其应用

本文在研究多值电路三要素理论基础上提出绝热电路通用理论，即绝热电路三要素（信号、网络、负载）理论。应用此理论，设计了三种典型的绝热电路（逐级级联收缩结构、可逆逻辑结构和交叉存贮结构），验证了该理论的正确性；然后进一步依此理论设计了一种新颖的采用二相功率时钟的交叉存贮型绝热电路一钟控传输门绝热逻辑（Clocked Transmission Gate Adiabatic Logic，CTGAL）电路。最后用计算机验证了根据绝热电路三要素理论设计的CTGAL电路具有正确的逻辑功能和明显的低功耗特性。     

开关信号理论与绝热CMOS电路设计

重新定义了钟控信号的表示方法,发展了适用于绝热电路的开关级设计理论.设计了实现全部钟控信号的基本单元电路,这些电路包括单轨和双轨结构,并给出了它们的多种级联方式.所提出电路的功耗与其他绝热电路相当,并工作于二相正弦功率时钟,因此可降低时钟电路的设计难度.这些电路可分别应用于需要基0信号和基1信号的绝热电路设计中.与以往大部分绝热电路不同的是,应用所提出的电路结构可以实现在同一时钟相位有多级电路同时参加运算.这一特性可以有效减少实现复杂逻辑电路时的等待时间以及实现流水结构时所需插入的缓冲器数目.通过对基0信号2∶1数据选择器     

开关信号理论与绝热CMOS电路设计

重新定义了钟控信号的表示方法,发展了适用于绝热电路的开关级设计理论.设计了实现全部钟控信号的基本单元电路,这些电路包括单轨和双轨结构,并给出了它们的多种级联方式.所提出电路的功耗与其他绝热电路相当,并工作于二相正弦功率时钟,因此可降低时钟电路的设计难度.这些电路可分别应用于需要基0信号和基1信号的绝热电路设计中.与以往大部分绝热电路不同的是,应用所提出的电路结构可以实现在同一时钟相位有多级电路同时参加运算.这一特性可以有效减少实现复杂逻辑电路时的等待时间以及实现流水结构时所需插入的缓冲器数目.通过对基0信号2∶1数据选择器和基1信号全加器的设计及SPICE模拟,验证了所提出设计技术的有效性以及电路的低功耗特性.     

低功耗绝热SRAM

文章提出了一种新的绝热电路,并以该绝热电路为驱动,设计了一种低功耗绝热SRAM.由于所提出的绝热电路能以完全绝热的方式回收位线和字线上大开关电容的电荷,因此使该SRAM的功耗大大减小.我们采用0.25μm TSMC工艺,在时钟频率25～200MHz范围内对绝热SRAM进行了能耗和功能的HSPICE仿真,结果显示,与用传统的CMOS电路设计的SRAM相比,可节能80%左右.     

二进制译码器逻辑功能的Multisim仿真方案

介绍了用Multisim仿真软件分析二进制译码器工作过程的方法,即用Multisim仿真软件中字组产生器产生二进制译码器的使能控制信号和地址输入信号。字组产生器的字组内容反映二进制译码器输入端的不同输入情况,用Multisim中逻辑分析仪多踪同步显示二进制译码器的各个输入信号及输出信号波形,可直观描述二进制译码器的译码工作过程。该方法解决了二进制译码器的工作波形无法用电子实验仪器进行分析验证的问题。     

三值低功耗多米诺JKL触发器设计及应用

通过对三值触发器和绝热多米诺电路的研究,提出一种新颖低功耗多米诺JKL触发器开关级设计方案。该方案首先利用开关—信号理论,根据三值JKL触发器真值表,推导出三值绝热多米诺JKL触发器开关级结构式;然后利用三值JKL触发器实现三值正循环门电路和三值反循环门电路的设计;最后,经Spice软件模拟证明所设计的三值绝热多米诺JKL触发器逻辑功能正确,与常规三值多米诺JKL触发器相比,能耗节省约69%。     

一种新的大容量SRAM编译器设计

介绍了一种大容量的SRAM编译器设计技术。根据SRAM容量和结构,提出了新的建模方案,并建立更优化的时序和功耗模型。同时,根据大容量SRAM在面积和性能上的需求,选择不同的译码器和拼接结构,采用合适的IP核进行拼接,并从结构上实现。对512 kb和1 Mb的SRAM进行了流片测试,测试结果表明,该方案对于大容量的SRAM编译器设计是有效的。     

三值绝热多米诺加法器开关级设计

通过对绝热多米诺电路和加法器的研究,该文提出一种新颖低功耗三值加法器的开关级设计方案。该方案首先利用开关-信号理论,结合绝热多米诺电路结构特点,推导出三值加法器本位和电路与进位电路的开关级结构式,由此得到一位三值加法器单元电路;然后通过单元电路的级联得到四位三值绝热多米诺加法器;最后,利用Spice软件对所设计的电路进行模拟,结果显示所设计的四位三值绝热多米诺加法器具有正确的逻辑功能,与四位常规多米诺三值加法器相比,能耗节省约61%。     

Design of ternary clocked adiabatic static random access memory

Based on multi-valued logic,adiabatic circuits and the structure of ternary static random access memory (SRAM),a design scheme of a novel ternary clocked adiabatic SRAM is presented.The scheme adopts bootstrapped NMOS transistors,and an address decoder,a storage cell and a sense amplifier are charged and discharged in the adiabatic way,so the charges stored in the large switch capacitance of word lines,bit lines and the address decoder can be effectively restored to achieve energy recovery during reading and writing of ternary signals.The PSPICE simulation results indicate that the ternary clocked adiabatic SRAM has a correct logic function and low power consumption.Compared with ternary conventional SRAM,the average power consumption of the ternary adiabatic SRAM saves up to 68%in the same conditions.     

Design of a DTCTGAL circuit and its application

By research on the switch-signal theory for multiple-valued logic circuits, the theory of three essential elements and the principle of adiabatic circuits, a design scheme for a double power clock ternary clocked transmission gate adiabatic logic (DTCTGAL) circuit is presented. The energy injection and recovery can be conducted by the bootstrapped NMOSFET, which makes the circuit maintain the characteristics of energy recovery as well as multiple-valued input and output. An XOR/XNOR circuit based on DTCTGAL is also presented using this design scheme. Finally, using the parameters of a TSMC 0.25 μm CMOS device, PSPICE simulation results indicate that the proposed circuits have correct logic and significant low power characteristics.     

nMOS reversible energy recovery logic for ultra-low-energyapplications

We propose a new fully reversible adiabatic logic, nMOS reversible energy recovery logic (nRERL), which uses nMOS transistors only and a simpler 6-phase clocked power. Its area overhead and energy consumption are smaller, compared with the other fully adiabatic logics. We employed bootstrapped nMOS switches to simplify the nRERL circuits. With the simulation results for a full adder, we confirmed that the nRERL circuit consumed substantially less energy than the other adiabatic logic circuits at low-speed operation. We evaluated a test chip implemented with 0.8-μm CMOS technology, which included a chain of nRERL inverters integrated with a clocked power generator. The nRERL inverter chain of 2400 stages consumed the minimum energy at V_dd=3.5 V at 55 kHz, where the adiabatic and leakage losses are about equal, which is only 4.50% of the dissipated energy of its corresponding CMOS circuit at V_dd=0.9 V. In conclusion, nRERL is more suitable than the other adiabatic logic circuits for the applications that do not require high performance but low energy consumption     

A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates

A 1.5-ns address access time, 256-kb BiCMOS SRAM has been developed. To attain this ultra-high-speed access time, an emitter-coupled logic (ECL) word driver is used to access 6-T CMOS memory cells, eliminating the ECL-MOS level-shifter time delay. The RAM uses a low-power active pull down ECL decoder. The chip contains 11-K, 60-ps ECL circuit gates. It provides variable RAM configurations and general logic functions. RAM power consumption is 18 W; chip power consumption is 35 W. The chip is fabricated by using a 0.5-μm BiCMOS process. The memory cell size is 58 μm² and the chip size is 11×11 mm     

A 16-bit carry-lookahead adder using reversible energy recoverylogic for ultra-low-energy systems

In this paper, we describe an energy-efficient carry-lookahead adder using reversible energy recovery logic (RERL), which is a new dual-rail reversible adiabatic logic. We also describe an eight-phase, clocked power generator that requires an off-chip inductor. For the energy-efficient design of reversible logic, we explain how to control the overhead of reversibility with a self-energy-recovery circuit. A test chip was implemented with a 0.8 μm CMOS technology, which included two 16-bit carry-lookahead adders to allow fair comparison: an RERL one and a static CMOS one. Experimental results showed that the RERL adder had substantial advantages in energy consumption over the static CMOS one at low operating frequencies. We also confirmed that we could minimize the energy consumption in the RERL circuit by reducing the operating frequency until adiabatic and leakage losses were equal     

1-V 100-MHz embedded SRAM techniques for battery-operatedMTCMOS/SIMOX ASICs

Multithreshold-voltage CMOS (MTCMOS) has a great advantage of lowering physical threshold voltages without increasing the power dissipation due to large subthreshold leakage currents. This paper presents the embedded SRAM techniques for high-speed low-power MTCMOS/SIMOX application-specified integrated circuits (ASICs) that are operated with a single battery cell of around 1 V. In order to increase SRAM operating frequency, a pseudo-two stage pipeline architecture is proposed. The address decoder using a pass-transistor-type NAND gate and a segmented power switch presents a short clocked wordline selection time. The large bitline delay in read operations is greatly shortened with a new memory cell using extra low-V_th nMOSs. The small readout signal from memory cells is detected with a high-speed MTCMOS sense amplifier, in which a pMOS bitline selector is merged. The wasted power dissipation in writing data is reduced to zero with a self-timed writing action. A 8 K-words×16-bits SRAM test chip, fabricated with a 0.35-μm MTCMOS/SIMOX process (shortened effective channel length of 0.17 μm is available), has demonstrated a 100-MHz operation under the worst power-supply condition of 1 V. At a typical 1.2 V, the power dissipation during the standby time is 0.2-μW and that of a 100-MHz operation with a checkerboard test pattern is 14 mW for single fan-in loads     

On the Test and Mitigation of Malfunctions in Low-Power SRAMs

In low-power SRAMs, power gating mechanisms are commonly used to reduce static power consumption. When the SRAM is not accessed for a long period, such mechanisms allow shutting off one or more memory blocks (core-cell array, address decoder, I/O logic, etc.), thus reducing leakage currents. In order to guarantee static power reduction in low-power SRAMs, reliable operation of power gating mechanisms must be ensured by adequate test techniques. In this paper, we first present a detailed analysis based on electrical simulations to identify faulty behaviors caused by realistic defects that may affect power gating mechanisms embedded in low-power SRAMs. Based on this analysis, we present an efficient test solution targeting detection of observed faulty behaviors. As a final contribution, we propose novel techniques to mitigate the impact of studied defects, once detected by test methods, therefore providing significant yield improvement.     

准静态单相能量回收逻辑

提出了一种新的准静态单相能量回收逻辑,其不同于以往的能量回收逻辑,真正实现了单相功率时钟,且不需要任何额外的辅助控制时钟,不但降低了能耗,更大大简化了时钟树的设计.该逻辑还可以达到两相能量回收逻辑所具有的速度.设计了一个8位对数超前进位加法器,并分别用传统的静态CMOS逻辑、钟控CMOS绝热逻辑(典型的单相能量回收逻辑)和准静态单相能量回收逻辑实现.采用128组随机产生的输入测试向量的仿真结果表明:输入频率为10MHz时,准静态能量回收逻辑的能耗仅仅是传统静态CMOS逻辑的45%;当输入频率大于2MHz时,可以获得比时钟控CMOS绝热逻辑更低的能耗.     

准静态单相能量回收逻辑

提出了一种新的准静态单相能量回收逻辑,其不同于以往的能量回收逻辑,真正实现了单相功率时钟,且不需要任何额外的辅助控制时钟,不但降低了能耗,更大大简化了时钟树的设计.该逻辑还可以达到两相能量回收逻辑所具有的速度.设计了一个8位对数超前进位加法器,并分别用传统的静态CMOS逻辑、钟控CMOS绝热逻辑(典型的单相能量回收逻辑)和准静态单相能量回收逻辑实现.采用128组随机产生的输入测试向量的仿真结果表明:输入频率为10MHz时,准静态能量回收逻辑的能耗仅仅是传统静态CMOS逻辑的45%;当输入频率大于2MHz时,可以获得比时钟控CMOS绝热逻辑更低的能耗.