一种零中频通用射频前端的设计及实现

摘要：本文采用零中频结构针对800～2400MHz工作频段设计了一种通用射频前端,该射频前端在一款高性能解调器的基础上,加入宽带低噪声放大器、程控射频AGC电路、电调谐预选滤波器等电路,从而实现灵敏度优于-100dBm/5MHz,动态范围大于100dB的设计指标要求。     

采用RF2607的WLAN自动增益控制设计

介绍了宽动态变化范围的新型可变增益放大器RF2607的特性、功能,给出了利用RF2607设计无线局域网(WLAN)通信中自动增益控制部分的实用电路.     

一种用于软件无线电的接收机射频前端电路设计与实现

设计了一种用于软件无线电的射频前端电路,该电路可工作于短波、超短波频段（3～89MHz）。电路将天线接收的信号经过前端滤波、AGC、放大处理后,将输出信号稳定到2V,直接送给下级进行A/D采样及基带处理。设计的核心是宽带AGC电路,采用了一种级联VGA的形式,较大地提高了AGC电路的动态范围和线性范围。经过硬件实测,该接收电路灵敏度能够达到-90dBm,动态范围为70dB,并且具有线性度高、噪声系数小等特点。     

应用于S波段AESA的射频收发前端设计

采用0．18μm Si RFCMOS工艺设计了应用于s波段AESA的高集成度射频收发前端芯片。系统由发射与接收前端组成,包括低噪声放大器、混频器、可变增益放大器、驱动放大器和带隙基准电路。后仿真结果表明,在3．3V电源电压下,发射前端工作电流为85mA,输出ldB压缩点为5．0dBm,射频输出在2～3．5GHz频带内电压增益为6．3～9．2dB,噪声系数小于14．5dB;接收前端工作电流为50mA,输入1dB压缩点为-5．6dBm,射频输入在2～3．5GHz频带内电压增益为12—14．5dB,噪声系数小于11dB;所有端口电压驻波比均小于1．8：芯片面积1．8×2．6mm0。     

2.4GHz带片上非平衡变压器射频前端的设计与优化

本文介绍了一种工作在2.4GHz频段的低功耗、低噪声、高线性射频接收机前端电路,该接收前端电路使用新型的带三种增益模式的LNA,并提出一种新的片上非平衡变压器优化技术。前端电路采用了直接变频结构,使用片上非平衡变压器实现低噪声放大器与下变频混频器之间的单端-差分转换,优化设计以提高前端电路的噪声性能。本文使用锗硅0.35um BiCMOS工艺,所采用的技术同样适用于CMOS工艺。前端电路总的最大转换增益为36dB;在高增益模式下的双边带噪声系数为3.8dB;低增益模式下,输入三阶交调点位12.5dBm。为了获得最大的输入动态范围,低噪声放大器采用三种可调增益模式,低增益模式使用by-pass结构,大大提高了大信号输入下接收前端的线性度。下变频混频器在输出端使用可调R-C tank,滤除带外高频杂波。混频器输出使用射极跟随器作为输出极驱动片外50ohm负载。该接收前端在2.85-V电源供电下,功耗为33mW,芯片面积为0.66mm2。     

射频前端技术和应用

在这篇文章里我们讨论了很多针对移动、无线和消费类射频前端应用的高等射频前端的系统与电路设计问题。在对应用趋势分析后，我们会讨论连接不同系统解决方案的技术选择。     

基于无源混频器的多频段TD—SCDMA射频接收器前端设计

文章以0．13μmRFCMOS工艺实现了直接下变频结构的多频段TD-SCDMA射频接收器前端,首先从TD-SCDMA系统要求和电路结构入手,分析了各电路模块的设计,包括高频低噪声放大器、无源混频器、运算放大器和本振驱动,最后给出了射频接收器前端的测试结果。     

一种用于接收机的低功耗自动增益控制环路

This paper proposes a new structure to lower the power consumption of a variable gain amplifier (VGA) and keep the linearity of the VGA unchanged. The structure is used in a high rate amplitude-shift keying (ASK) based IF-stage. It includes an automatic gain control (AGC) loop and ASK demodulator. The AGC mainly consists of six-stage VGAs. The IF-stage is realized in 0.18 μ m CMOS technology. The measurement results show that the power consumption of the whole system is very low. The system consumes 730 μ A while operating at 1.8 V. The minimum ASK signal the system could detect is 0.7 mV (peak to peak amplitude).     

应用于TD-LTE接收机射频前端的一种AGC电路

基于可变增益放大器AD8367,结合线性检波器AD8361和误差放大器AD820,为TD-LTE接收机射频前端设计了一个自动增益控制(AGC)电路,实物测试显示该AGC电路能在输入信号频率为240MHz,输入信号功率为-40dBm到-10dBm时,输出信号功率能稳定在0dBm处,分析了该AGC电路噪声对接收机整体噪声的影响,满足系统指标的要求。设计思维简洁,电路结构简单,可以方便地调节输出电平值,确保接收机正常工作。     

56 Gbit/s PAM4 CMOS光接收机前端电路设计

基于65 nm CMOS工艺设计了一种56 Gbit/s PAM4光接收机前端放大电路.前级为差分形式的跨阻放大器,采用共栅前馈型结构降低输入阻抗,并在输入端串联电感,有效提高了跨阻放大器的带宽和灵敏度.后级放大器采用具有线性增益控制的多级级联可变增益放大器,实现对输出摆幅的自动控制.输出缓冲器采用源极退化技术来拓展带...     

An RF front-end with an automatic gain control technique for a U/V band CMMB receiver

This paper presents a fully integrated RF front-end with an automatic gain control(AGC) scheme and a digitally controlled radio frequency varied gain amplifier(RFVGA) for a U/V band China Mobile Multimedia Broadcasting(CMMB) direct conversion receiver.The RFVGA provides a gain range of 50 dB with a 1.6 dB step. The adopted AGC strategy could improve immunity to adjacent channel signal,which is of importance for CMMB application.The front-end,composed of a low noise amplifier(LNA),an RFVGA,a mixer and AGC,achieves an input referred 3rd order intercept point(IIP3) of 4.9 dBm with the LNA in low gain mode and the RFVGA in medium gain mode,and a less than 4 dB double side band noise figure with both the LNA and the RFVGA in high gain mode.The proposed RF front-end is fabricated in a 0.35μm SiGe BiCMOS technology and consumes 25.6 mA from a 3.0 V power supply.     

一种ISM 2.4GHz的低功耗低中频射频接收机前端

本文描述了一种工作在2.4GHz ISM频段的低功耗、低中频射频接收机前端电路,使用TSMC 0.13um CMOS工艺。整个前端包括一个低噪声放大器以及两次变频下变换混频器。低噪声放大器通过在输入级引入额外的栅-源电容实现了低功耗与低噪声的设计;在下变换混频器设计中,分别使用一个单平衡射频混频器以及两个双平衡低中频混频器实现两次变频下变换技术;射频混频器输入晶体管源极串联电感-电容谐振网络以及低噪声放大器输出级的电感-电容谐振网络总共实现了30dB的镜像抑制率。整个前端占用芯片面积约0.42mm2,在1.2V的供电电压下,仅耗功率4.5mW,实现了4dB的噪声系数,在高增益模式下,获得-22dBm的三阶交调线性度,整个链路电压增益为37dB。     

用于315/433MHz超再生接收机的射频前端关键技术

采用0.5μm CMOS工艺实现了用于315/433MHz超再生无线接收机的射频前端电路,包括射频放大器和超再生振荡器。文中提出了一种改进型有源电感,提高了射频放大器中谐振回路的品质因数。阐述了振荡器的自偏置效应以及振荡器输出信号幅度和电流源的关系,在此基础上实现了适用于包络检波的差分结构超再生振荡器。测试结果显示,电源电压范围为2.5V~5V,电流小于2.5mA,系统接收灵敏度优于-90dBm。     

Design and optimization of a 2.4 GHz RF front-end with an on-chip balun

A 2.4 GHz low-power,low-noise and highly linear receiver front-end with a low noise amplifier(LNA) and balun optimization is presented.Direct conversion architecture is employed for this front-end.The on-chip balun is designed for single-to-differential conversion between the LNA and the down-conversion mixer,and is optimized for the best noise performance of the front-end.The circuit is implemented with 0.35μm SiGe BiCMOS technology.The front-end has three gain steps for maximization of the input dynamic range.The overall maximum gain is about 36 dB.The double-sideband noise figure is 3.8 dB in high gain mode and the input referred third-order intercept point is 12.5 dBm in low gain mode.The down-conversion mixer has a tunable parallel R-C load at the output and an emitter follower is used as the output stage for testing purposes.The total front-end dissipation is 33 mW under a 2.85 V supply and occupies a 0.66 mm~2 die size.     

差分式低电压高增益电流模式集成射频接收机前端

本文提出了一种用于802.11 b 无线局域网的差分式低电压该增益电流模式射频前端集成电路。该电路包含一个差分式跨导低噪声放大器和一个差分式电流模式下混频器。单边跨导低噪声放大器仅含一个MOS晶体管和2个电感、2个电容构成。放大器中的栅-源并联电容Cx1 和 Cx2 不仅能减小栅-源寄生电容对谐振频率和输入匹配阻抗的的影响,而且能使得栅电感的取值变小。电流模式混频器由开关电流镜构成。调节开关电流镜晶体管之间沟道尺寸比值可以增加混频器的增益,从而增大射频接收机前端的功率增益。该射频前端电路工作在1V的电源电压下。使用chartered 0.18μm CMOS工艺进行了流片。 对芯片进行测试得到该射频前端的功率增益为17.48 dB, 输入三阶交调截点 (IIP3) 为 -7.02 dBm. 后仿真表示该芯片的噪声系数为4.5 dB,功耗仅为 14mW。     

A differential low-voltage high gain current-mode integrated RF receiver front-end

A differential low-voltage high gain current-mode integrated RF front end for an 802.11b WLAN is proposed.It contains a differential transconductance low noise amplifier（G_m-LNA） and a differential current-mode 0 down converted mixer.The single terminal of the G_m-LNA contains just one MOS transistor,two capacitors and two inductors.The gate-source shunt capacitors,C_x1 and C_x2,can not only reduce the effects of gate-source C_gs on resonance frequency and input-matching impedance,but they also enable the gate inductance L_g1,2 to be selected at a very small value.The current-mode mixer is composed of four switched current mirrors.Adjusting the ratio of the drain channel sizes of the switched current mirrors can increase the gain of the mixer and accordingly increase the gain of RF receiver front-end.The RF front-end operates under 1 V supply voltage.The receiver RFIC was fabricated using a chartered 0.18μm CMOS process.The integrated RF receiver front-end has a measured power conversion gain of 17.48 dB and an input referred third-order intercept point（IIP3） of-7.02 dBm.The total noise figure is 4.5 dB and the power is only 14 mW by post-simulations.     

用于U波段移动数字电视的宽带大动态范围高线性度射频前端

A wideband large dynamic range and high linearity U-band RF front-end for mobile DTV is introduced,and includes a noise-cancelling low-noise amplifier(LNA),an RF programmable gain amplifier(RFPGA) and a current communicating passive mixer.The noise/distortion cancelling structure and RC post-distortion compensation are employed to improve the linearity of the LNA.An RFPGA with five stages provides large dynamic range and fine gain resolution.A simple resistor voltage network in the passive mixer decreases the gate bias voltage of the mixing transistor,and optimum linearity and symmetrical mixing is obtained at the same time.The RF front-end is implemented in a 0.25 μm CMOS process.Tests show that it achieves an ⅡP3(third-order intercept point) of –17 dBm,a conversion gain of 39 dB,and a noise figure of 5.8 dB.The RFPGA achieves a dynamic range of –36.2 to 23.5 dB with a resolution of 0.32 dB.