用于GaAs射频集成电路的不同厚度氧化铝MIM 电容的研究

本文研究了不同厚度的氧化铝对MIM电容直流和射频特性的影响。在1MHz下,对于20nm氧化铝MIM电容,其拥有3850 pF/mm₂的高电容密度和可接受的681 ppm/V₂的VCC-α电压系数。1MHz时突出的74 ppm/V₂VCC-α电压系数,8.2GHz谐振频率以及2GHz时41的Q值可以从100nm氧化铝MIM电容获得。采用GaAs工艺以及原子层淀积制造的高性能ALD氧化铝MIM电容很有可能成为GaAs射频集成电路很有前景的候选器件。     

Microstructure and dielectric response of SrTiO3/NdGaO3 interdigitated capacitors

Epitaxial strontium titanate (SrTiO₃ or STO) thin films were prepared by an off-axis pulsed laser deposition technique on neodymium gallate (NdGaO₃ or NGO) substrates held at temperature of 820 °C. This technique allows different film growth rates in a deposition. Coplanar capacitors were fabricated and dielectric responses were measured at 1 MHz and at 2 GHz, and from 300 K to 4 K. The electric field tunability of the dielectric constant and loss tangent were taken with a range of electric field. The structure and morphology of the films were analyzed using high-resolution X-ray diffractometry and atomic force microscopy, respectively. The results showed that the films are crystalline with (1 0 0) orientation and the grains are columnar. Increased in-plane grain size and reduced surface to volume ratio were found to play a major role in improved performance of the film coplanar capacitors. The film with the growth rate of approximate 40 Å/min showed the highest change in the dielectric constant with an electric field of 4 V/μm. The film also showed the largest in-plane grain size of about 3000 Å.     

Wideband frequency and in situ characterization of ultra thin ZrO2 and HfO2 films for integrated MIM capacitors

High-κ dielectrics are promising candidates to increase capacitor integration densities but their properties depend on manufacturing process and frequency because relaxation and resonance mechanisms occur. Complementary characterization protocols are needed to analyze high-κ insulator behaviour from DC to microwave frequencies. The extraction of Plasma Enhanced Atomic Layer Deposition HfO₂ and ZrO₂ complex permittivity was performed up to 5 GHz using dedicated test vehicles allowing an in situ characterization as a function of dielectric thickness. The measurement procedure was thus validated, highlighting the potentiality of these two dielectrics to cover a wide range of frequencies.     

First investigation of metal–insulator–metal (MIM) capacitor using Pr2O3 dielectrics

Metal–insulator–metal (MIM) capacitors with Pr₂O₃ as high-k material have been investigated for the first time. We varied the thickness of the Pr₂O₃ layers as well as the bottom electrode material. The layers are characterised using X-ray photoelectron spectroscopy (XPS), X-ray diffraction (XRD), transmission electron microscopy (TEM) and secondary ion mass spectroscopy (SIMS). Preliminary information on the interaction of water with the films was obtained from XPS and ab initio pseudopotential calculations. The electrical characterisation shows that Pr₂O₃ MIM capacitors can provide higher capacitance densities than Si₃N₄ MIM capacitors while still maintaining comparable voltage coefficients of capacitance. The Pr₂O₃ dielectric material seems to be suitable for use in silicon RF applications.     

Analysis of reliability characteristics of high capacitance density MIM capacitors with SiO2-HfO2-SiO2 dielectrics

In this paper, reliability as well as electrical properties of high capacitance density metal-insulator-metal (MIM) capacitor with hafnium-based dielectric is analyzed in depth. The fabricated MIM capacitor exhibits not only high capacitance density but also low voltage coefficient of capacitance (VCC) and low temperature coefficient of capacitance (TCC). It also has a low leakage current level of about ∼1 nA/cm² at room temperature and 1 V. However, it is shown that voltage linearity has a different dependence on the polarity of applied bias as temperature increases maybe due to the bulk traps between the metal electrode and high-k dielectric interface. In addition, the effect of charge trapping and de-trapping on the voltage linearity is analyzed under constant voltage stress.     

Precise determination of metal effective work function and fixed oxide charge in MOS capacitors with high-κ dielectric

Effective metal work function, Φ_m,eff, and oxide charge, Q_ox, were determined on MOS capacitors with slanted high-κ dielectric. Φ_m,eff and Q_ox were extracted using flat-band voltage shift versus equivalent oxide thickness data, both deduced from the capacitance–voltage measurements. Slanted HfSiO_x dielectric (initial thickness was 9 nm) was prepared by gradual etching in HF-based solution. As a metal electrode, thin Ru-films were deposited by MOCVD-derived technique—Atomic Vapor Deposition^® on the slanted HfSiO_x as well as SiO₂ dielectrics. The Φ_m,eff of Ru was found to be 4.74 and 4.81 eV for Ru/HfSiO_x and Ru/SiO₂ gate stacks, respectively. Ultraviolet photoelectron spectroscopy yields the work function of 4.62 eV in agreement with the capacitance–voltage data. We also studied the I–V characteristics of the Ru/HfSiO_x/Si MOS capacitors. The barrier height was found to be constant within the HfSiO_x bulk.     

In0.53Ga0.47As表面氮化和硫钝化对其Al/Al2O3/InGaAs MOS电容特性的影响

本文通过对比频散特性和滞回特性,计算界面态密度D_it和有效边界缺陷密度ΔN_bt,分析界面缺陷和漏电流等方法,系统的研究了In_0.53Ga_0.47As表面氮化和硫钝化对其Al/Al₂O₃/InGaAs结构MOS电容特性的影响。实验结果表明,这两种方法都能够在InGaAs表明形成一层界面钝化层。相比较于未处理的样品,经过氮气等离子体处理的样品表现出较好的界面特性,得到了最小的积累区频散、滞回电压,以及良好的I-V性能。经过(NH₄)₂S_x处理的样品则获得了最小的平带电压区频散以及最低的界面态密度Dit=2.6E11cm_-2eV_-1.     

Nanoscale analysis of YBa2Cu3O7−x/La0.67Ca0.33MnO3 interfaces

The structure of interfaces in superconducting/ferromagnetic YBa₂Cu₃O_7−x/La_0.67Ca_0.33MnO₃ superlattices has been analyzed by scanning transmission electron microscopy and high spatial resolution electron energy loss spectroscopy. Individual layers are flat over long lateral distances. The interfaces are coherent, free of defects, exhibiting no roughness, and are located at the BaO plane of the superconductor. Concerning chemical disorder, EELS measurements show the absence of measurable chemical interdiffusion within experimental error bars.     

Epitaxy of BaTiO3 thin film on Si(0 0 1) using a SrTiO3 buffer layer for non-volatile memory application

In this study we report the epitaxial growth of BaTiO₃ films on Si(0 0 1) substrate buffered by 5 nm-thick SrTiO₃ layer using both MBE and PLD techniques. The BaTiO₃ films demonstrate single crystalline, (0 0 1)-oriented texture and atomically flat surface on SrTiO₃/Si template. The electrical characterizations of the BaTiO₃ films using MFIS structures show that samples grown by MBE with limited oxygen pressure during the growth exhibit typical dielectric behavior despite post deposition annealing process employed. A ferroelectric BaTiO₃ layer is obtained using PLD method, which permits much higher oxygen pressure. The C-V curve shows a memory window of 0.75 V which thus enable BaTiO₃ possibly being applied to the non-volatile memory application.     

Performance analysis of 20 nm gate-length In0.2Al0.8N/GaN HEMT with Cu-gate having a remarkable high ION/IOFF ratio

Abstract： We propose a new structure of InxAll-xN/GaN high electron mobility transistor （HEMT） with gate length of 20 nm. The threshold voltage of this HEMT is achieved as -0.472 V. In this device the InA1N barrier layer is intentionally n-doped to boost the ION/IOFF ratio. The InAlN layer acts as donor barrier layer for this HEMT which exhibits an ION = 10-4.3 A and a very low IOFF = 10-14.4 A resulting in an ION/IoFF ratio of 1010.1. We compared our obtained results with the conventional InAlN/GaN HEMT device having undoped barrier and found that the proposed device has almost l0s times better ION/IOFF ratio. Further, the mobility analysis in GaN channel of this proposed HEMT structure along with DC analysis, C-V and conductance characteristics by using small-signal analysis are also presented in this paper. Moreover, the shifts in threshold voltage by DIBL effect and gate leakage current in the proposed HEMT are also discussed. InAlN was chosen as the most preferred barrier layer as a replacement of AlGaN for its excellent thermal conductivity and very good scalability.     

High temperature transport kinetics in heteroepitaxial LaFeO3 thin films

Heteroepitaxial LaFeO₃(1 1 0) thin films with a thickness of 150 nm were grown on LaAlO₃(0 0 1) by reactive sputtering in an inverted cylindrical magnetron geometry. Equilibrium conductivity was measured as a function of partial pressure of oxygen at T=1000 °C, and logσ plotted vs. logP(O₂) showed a minimum in conductivity for P(O₂)=10⁻¹¹ atm and a linear response between 10⁻¹⁰ and 1 atm. This linear response makes thin films of LaFeO₃ a promising material for oxygen sensor applications. We have also measured the time response of the film conductivity upon an abrupt change in the partial pressure of ambient oxygen from 10⁻² to 10⁻³ atm, which was determined at 60 s for T=700 °C and <3.5 s at T=1000 °C.     

High temperature characterization of high-κ dielectrics on SiC

We have fabricated thin catalytic metal–insulator–silicon carbide based structure with palladium (Pd) gates using TiO₂ as the dielectric. The temperature stability of the capacitor is of critical importance for use in the fabrication of electronics for deployment in extreme environments. We have evaluated the response to temperatures in excess of 450 °C in air and observed that the characteristics are stable. Results of high temperature characterization are presented here with extraction of interface state density up to 650 °C. The results show that at temperatures below 400 °C the capacitors are stable, with a density of interface traps of approximately 6×10¹¹ cm² eV⁻¹. Above this temperature the C–V and G–V characteristics show the influence of a second set of traps, with a density around 1×10¹³ cm² eV⁻¹, which is close to that observed for slow states near the conduction band edge. The study of breakdown field as a function of temperature shows two distinct regions, below 300 °C where the breakdown voltage has a strong temperature dependence and above 300, where it is weaker. We hypothesize that the oxide layer dominates the breakdown voltage at low temperature and the TiO₂ layer above 300 °C. These results at high temperatures confirms the suitability of the Pd/TiO₂/SiO₂/SiC capacitor structure for stable operation in high temperature environments.     

微波法制备高活性H1-xSr2Nb3-xMoxO10 (x = 0, 0.05, 0.1, 0.15 and 0.2) 光催化剂

通过微波辅助法制备出高活性H1-xSr2Nb3-xMoxO10光催化材料,制备过程和时间均被大大缩短。采用X射线粉末衍射（XRD）、扫描电镜（SEM）、紫外-可见吸收吸收光谱（UV-Vis DRS）等表征其材料性能。考察了催化材料在40W汞灯辐照下催化降解甲基橙的催化性能。实验结果表明,MoO3的掺入量为15%（摩尔分数）时,材料的光催化性能最优。     

Fabrication of Ge-MOS capacitors with high quality interface by ultra-thin SiO2/GeO2 bi-layer passivation combined with the subsequent SiO2-depositions using magnetron sputtering

Ge-MOS capacitors were fabricated by a novel method of ultra-thin SiO₂/GeO₂ bi-layer passivation (BLP) for Ge surface combined with the subsequent SiO₂-depositions using magnetron sputtering. For the Ge-MOS capacitors fabricated by BLP with O₂, to decrease oxygen content in the subsequent SiO₂ deposition is helpful for improving interface quality. By optimizing process parameters of the Ge surface thermal cleaning, the BLP, and the subsequent SiO₂ deposition, interface states density of 4 × 10¹¹ cm⁻² eV⁻¹ at around mid-gap was achieved, which is approximately three times smaller than that of non-passavited Ge-MOS capacitors. On the contrary, for the Ge-MOS capacitors fabricated by BLP without O₂, interface quality could be improved by an increase in oxygen contents during the subsequent SiO₂ deposition, but the interface quality was worse compared with BLP with O₂.     

高峰谷电流比的高掺杂发射区In0.53Ga0.47As/AlAs共振隧穿二极管

利用空气桥工艺设计和制作了高掺杂发射区In0.53Ga0.47As/AlAs共振隧穿二极管（RTD）。在室温下,器件的峰谷电流比大于40,峰值电流密度为24kA/cm2。建立了RTD器件等效电路模型,并从直流和微波测试结果中提取出器件参数。高峰谷电流比的RTD器件具有非常小的电容,有利于在微波/太赫兹领域中的应用。     

Etch damage evaluation on (Bi4−xLax)Ti3O12 thin films during the etch process using inductively coupled plasma sources

The etching mechanism of (Bi_4−xLa_x)Ti₃O₁₂ (BLT) thin films in Ar/Cl₂ inductively coupled plasma (ICP) and plasma-induced damages at the etched surfaces were investigated as a function of gas-mixing ratios. The maximum etch rate of BLT thin films was 50.8 nm/min of 80% Ar/20% Cl₂. From various experimental data, amorphous phases on the etched surface existed on both chemically and physically etched films, but the amorphous phase was thicker after the 80% Ar/20% Cl₂ process. Moreover, crystalline “breaking” appeared during the etching in Cl₂-containing plasma. Also the remnant polarization and fatigue resistances decreased more for the 80% Ar/20% Cl₂ etch than for pure Ar plasma etch.     

Investigation of high-K gate stacks with epitaxial Gd2O3 and FUSI NiSi metal gates down to CET=0.86 nm

Novel gate stacks with epitaxial gadolinium oxide (Gd₂O₃) high-k dielectrics and fully silicided (FUSI) nickel silicide (NiSi) gate electrodes are investigated. Ultra-low leakage current densities down to 10^–7 A cm^–2 are observed at a capacitance equivalent oxide thickness of CET=1.8 nm. The influence of a titanium nitride (TiN) capping layer during silicidation is studied. Furthermore, films with an ultra-thin CET of 0.86 nm at a Gd₂O₃ thickness of 3.1 nm yield current densities down to 0.5 A cm⁻² at V_g=+1 V. The extracted dielectric constant for these gate stacks ranges from k=13 to 14. These results emphasize the potential of NiSi/Gd₂O₃ gate stacks for future material-based scaling of CMOS technology.     

一种具有高能量分辨率Al2O3钝化结区的PIN探测器

提出了一种Al₂O₃钝化结区的PIN探测器,与传统PIN探测器不同的是,在器件正面的pn结和背面的高低结处沉积了10 nm厚的Al₂O₃薄膜。经TCAD仿真结果表明,该探测器具有更低的漏电流和保护环处的电子电流密度,能对高能粒子射线入射产生良好的响应。设计了两种探测器的制备步骤并制备了器件,通过薄膜少子寿命的表征、器件的暗态I-V测试和²⁴¹Am元素能谱测试对其进行了评估。测试结果表明,与传统的PIN探测器相比,Al₂O₃钝化结区的PIN探测器的少子寿命提升至1 061μs,漏电流降低至5 nA,能量分辨率提升至521 eV,表现出更好的探测性能。     

High-field mobility metal-gate/high-κ Ge n-MOSFETs with small equivalent-oxide-thickness

We fabricated high performance gate-last TaN/La₂O₃/SiO₂ on Ge n-MOSFET. Small equivalent-oxide-thickness (EOT) of 1.9-nm and high-field mobility of 258 cm²/V s at 0.75 MV/cm were obtained, which were attributed to the thin SiO₂-like barrier layer and low process temperature to prevent interfacial reaction during post-deposition annealing (PDA).     

Interaction of α radiation with iron-doped n-type silicon

Deep-level transient spectroscopy (DLTS) measurements were carried out on low-doped n-silicon before and after irradiation with 5.48 MeV α particles at room temperature with a fluence of 10¹⁰ α particles/cm². The DLTS measurements on the samples identified three electron levels E₁, E₂ and E₃ before irradiation. The deep-levels characteristic studies include emission rate signatures, activation energies, defect concentrations and capture cross sections. It was found that all pre-existing defects decreased their amplitudes during irradiation. The decrease in activation energy of level E₃ and noticeable suppression of level E₁ was also observed after irradiation. It was clearly seen that the composite peak E₃ (combination of E₂ and E₃) was successfully resolved after irradiating with α particles. α-irradiation is seen to lead a significant suppression of the iron interstitial defect, and without causing any change in its room temperature annealing characteristics.