Minimized constrains for lateral profiling of hot-carrier-induced oxide charge and interface traps in MOSFETs

For better understanding the hot-carrier-induced reliability problems, a charge-pumping technique has been developed to profile the Q/sub ot/ and N/sub it/ directly from the experimental results. However, the key neutralization condition is acquired by trial and error, which takes much time and effort. Therefore, a technique of two-step neutralization is proposed to find out the appropriate neutralization condition in this work. This two-step neutralization combined with the error-reduction method is shown to carry out the profiling more quickly and precisely.     

A new technique for measuring lateral distribution of oxide chargeand interface traps near MOSFET junctions

A technique to measure the lateral distribution of both interface traps and trapped oxide charge near the source-drain junctions in MOSFETs is presented. Its basic principle is described. This technique derives from the charge-pumping method, is easy to implement, and allows ready separation of the interface-trap and oxide charge components. Examples are shown for hot-carrier stressed MOS transistors     

FORWARD GATED—DIODE METHOD FOR DIRECTLY MEASURING STRESS—INDUCED INTERFACE TRAPS IN NMOSFET／SOI

Forward gated-diode Recombination-Generation(R-G) current method is applied to an NMOSFET/SOI to measure the stress-induced interface traps in this letter.This easy but accurate experimental method can directly give stress-induced average interface traps for characterizing the device‘s hot carrier characteristics.For the tested device, an expected power law relationship of Δnit-t^0.787 between pure stress-induced interface traps and accumulated stressing time is obtained.     

FORWARD GATED—DIODE METHOD FOR EXTRACTING HOT—CARRIER—STRESS0INDUCED BACK INTERFACE TRAPS IN SOI／NMOSFETs

The forward gated-diode R-G current method for extracting the hot-carrier-stress-induced back interface traps in SOI/NMOSFET devices has been demonstrated in this letter. This easy and accurate experimental method directly gives the induced interface trap density from the measured R-G current peak of the gated-diode architecture. An expected power law relationship between the induced back interface trap density and the accumulated stress time has been obtained.     

Light emission from interface traps and bulk defects in SiC MOSFETs

Images and spectra of light emission have been observed in 4H and 6HSiC n-type MOSFETs originating from electron-hole recombination at interface traps and from the bulk under the channel. Low mobility and high interface trap density impedes the flow of electrons into the channel. Its time evolution was imaged. It is slower in 4H than in 6H MOSFETs due to the lower channel mobility and higher interface trap density in the former. Emission images reveal triangular shaped 3C inclusions and these defects were found to alter the formation of the inversion layer.     

Analysis of slow traps centres in submicron MOSFETs by random telegraph signal technique

In this paper, we present a comprehensive study of slow single traps, situated inside the gate oxide of small area (W×L=0.5×0.1 μm²) metal–oxide–semiconductor (MOS) transistors. The gate oxide of the analyzed transistors, which have been used for memory-cell applications, is composed of two SiO₂ layers—a deposited high-temperature oxide (HTO) and the thermal oxide. The interface between the two gate oxides is shown to play a significant role in the channel conduction: we observed that the presence of individual traps situated inside the gate oxide, at some angstroms from the interface with the channel, is inducing discrete variations in the drain current. Using random telegraph signal (RTS) analysis, for various temperatures and gate bias, we have determined the characteristics of these single traps: the energy position within the silicon bandgap, capture cross section and the position within the gate oxide.     

Electron mobility in ULSI MOSFETs: effect of interface traps andoxide nitridation

We provide a comprehensive set of electron mobility measurements at 300 K and 77 K on standard and N₂O-nitrided MOSFETs, with channel doping in the range 3.8×10¹⁷-1.25×10¹⁸ cm^-3. In such heavily-doped devices, the Fermi level always lies very close to the conduction band edge, where interface traps reach the highest density and the shortest lifetimes. We show that these traps contribute to the gate-channel capacitance, leading to a systematic overestimate of the channel charge. This effect has the largest impact precisely in the roll-off region of the mobility curves, which has been the subject of recent theoretical investigations     

Spatial uniformity of interface trap distribution in MOSFETs

The uniformity of the spatial distribution of (fast) interface traps N_it in small MOS devices was determined using charge pumping on MOSFETs with varying lengths and widths. The number of traps was found to be linearly proportional to both length and width as expected for a macroscopically uniform distribution. No evidence was found for an anomalous N_it distribution at the edges of the source/drain regions; however, the data suggest that there is a higher density of traps along the edges of LOCOS (local oxidation of silicon) field oxides     

Simulation of flicker noise in gate-all-around Silicon Nanowire MOSFETs including interface traps

This paper presents a systematic investigation of flicker noise in Gate-all-around Silicon Nanowire MOSFET. The 1/f noise is simulated in the presence and absence of interface traps. Moreover the device is simulated under various distributions (Exponential, Gaussian, Uniform) of noise source. Nonuniformity in the interface of the oxide/semiconductor region as gave rise to increase the threshold voltage, there by increasing the leakage current. The effect of interface traps on different distribution has been explored in detail. The noise spectral density variations for various traps shows significant increase in flicker noise up to a magnitude of under 6 “dB” for weak signals. The simulated results matches with the calibrated experimental data.     

Forward gated-diode measurement of filled traps in high-fieldstressed thin oxides

The forward gated-diode monitoring technique can find its potential applications in assessing the filled traps in MOSFET thin oxides, which are subjected to high-field stressing and then followed by a hot-electrons filling scheme. Our measurement of the gate voltage shift associated with the forward current peak produces a power law relation between the filled trap density and the electron stress fluence, indeed in close agreement with that obtained by MOSFET threshold voltage shift     

Spatial distribution of interface traps in DeMOS transistors

The spatial distribution of interface traps in a p-type drain extended MOS transistor is experimentally determined by the analysis of variable base-level charge pumping spectra. The evolution of the interface trap distribution can be monitored as a function of the hot-carrier stress time. A double peaked interface trap density distribution, located in the spacer oxide, is extracted. The interface trap density in the poly overlapped drift region is constant as a function of stress time. No channel degradation is observed.     

Lateral distribution of hot-carrier-induced interface traps inMOSFETs

The spatial profiles of hot-carrier-induced interface traps in MOSFETs with abrupt arsenic junctions and oxide thickness of 10-38 nm are determined using charge pumping both in the conventional manner and with a modified constant-field approach. For the thinnest oxides the damage is highly localized in a very sharp peak that is located inside the drain at the point of maximum lateral electric field. In thicker oxides, the damage peak is broader and is shifted toward the edge of the drain junction. Two-dimensional device simulations using the measured profiles are in qualitative agreement with measured I-V characteristics after degradation. However, the magnitude of the predicted degradation is underestimated, suggesting that significant electron trapping occurs also     

Effect of oxide–semiconductor interface traps on low-temperature operation of MOSFETs

Operation of n-channel MOSFET was studied at low temperatures. It has been shown that the charge state of shallow traps in the Si/SiO₂ interface is responsible for the hysteresis of transistor drain characteristics in the prekink region. Thermally activated emptying of these traps leads to the sharp decrease of the current in the subthreshold mode of transistor operation.     

Application of forward gated-diode R–G current method in extracting F–N stress-induced interface traps in SOI NMOSFETs

Application of the forward gated-diode recombination–generation (R–G) current method in extracting the F–N stress-induced interface traps in SOI NMOSFET devices has been demonstrated in this letter. This easy and accurate experimental method can directly give F–N stress-induced interface trap density from the measured R–G current peak of the gated-diode architecture. An expected power law relationship between the induced interface trap density and the accumulated stress time has been obtained. For the different stress time and the bias voltage, the stress experiments demonstrate the induced interface traps increase in a similar power law factor, 0.4, revealing the same generation mechanism of the interface traps.     

A field-effect electron mobility model for SiC MOSFETs including high density of traps at the interface

Besides its favorable physical properties, high performant MOSFETs (metal-oxide-semiconductor field-effect transistors) fabrication in silicon carbide (SiC) remains an open issue due to their low channel mobility values. The effect of charge trapping and the scattering at interface states have been invoked as the main reasons for mobility reduction in SiC thermal oxidized MOS gated devices. In this paper, we propose a compact electron mobility model based on the well-established Lombardi mobility model to reproduce the mobility degradation commonly observed in these SiC devices. Using 2D electrical simulations along with the proposed model and taking into account interface traps Coulomb scattering, the experimental field-effect mobility of 4H-SiC MOSFET devices has been fitted with a good agreement.     

Effects of high field generation of charge trapping in the oxideand interface traps on MOS capacitors and MOSFETs

Oxide charge trapping and interface state generation phenomena under the various high-field stress conditions have been investigated using capacitors fabricated on both p-and n-type substrates, and p- and n-channel MOSFETs. It was found that prediction based on MOSFET devices yielded shorter lifetimes than predictions based on capacitors     

A novel experimental technique for the lateral profiling of oxideand interface state charges in hot-hole degraded n-MOSFETs

A new experimental technique, based on gate-to-drain capacitance C _gd^s and charge pumping (CP) current, is proposed for the lateral profiting of oxide and interface state charges in the LDD region of the n-MOSFETs. The device is injected with hot holes, which are subsequently removed by a low-level channel hot-electron stress. The degree of neutralization is monitored by C_gd^s until complete annihilation of trapped holes is realized. This allows the effects of oxide and interface state charges on CP characteristics to be clearly distinguished, and the spatial profiles of the two charges to be separately determined     

Profiling of stress induced interface states in short channel MOSFETs using a composite charge pumping technique

The charge pumping phenomenon is studied and the limits of validity of different experimental alternatives are analysed, taking into consideration emission processes and short channel effects. As a result, a composite charge pumping technique, which can accurately give the energy distribution of interface state densities in short channel MOSFETs, is proposed. The experiment is based on the successive variation of the gate voltage pulse parameters (top and bottom levels, rise and fall times) at room and low temperatures. This method is then applied to study aging effects due to channel hot electron injection. The comparison of the experimental energy profile determined before and after electrical stress shows a global increase of interface states, which is more pronounced near the conduction band edge.     

On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress

A common framework for interface-trap (N/sub IT/) generation involving broken /spl equiv/Si-H and /spl equiv/Si-O bonds is developed for negative bias temperature instability (NBTI), Fowler-Nordheim (FN), and hot-carrier injection (HCI) stress. Holes (from inversion layer for pMOSFET NBTI, from channel due to impact ionization, and from gate poly due to anode-hole injection or valence-band hole tunneling for nMOSFET HCI) break /spl equiv/Si-H bonds, whose time evolution is governed by either one-dimensional (NBTI or FN) or two-dimensional (HCI) reaction-diffusion models. Hot holes break /spl equiv/Si-O bonds during both FN and HCI stress. Power-law time exponent of N/sub IT/ during stress and recovery of N/sub IT/ after stress are governed by relative contribution of broken /spl equiv/Si-H and /spl equiv/Si-O bonds (determined by cold- and hot-hole densities) and have important implications for lifetime prediction under NBTI, FN, and HCI stress conditions.     

Determination of the energy distribution of interface traps in MIS systems using non-steady-state techniques

Experimental techniques are described for determining the energy distribution of interface traps at the semiconductor-insulator interface of MIS devices. The device used here was an MNOS capacitor in which the semiconductor was n-type. The first technique which is described is that of measuring the thermally stimulated currents. The method consists of biasing the capacitor into the accumulation mode at a low temperature thereby filling the traps at the semiconductor oxide interface. The device is then biased into the deep-depletion mode in which state the traps remain filled because the temperature is too low to allow the electrons to be thermally excited out of the traps. The temperature of the device is then raised at a uniform rate, and the current associated with the release of electrons from the trap is monitored. The shape of the I?T characteristic is a direct image of the interface trap distribution is a broad peak with a maximum at 0·35 eV below the bottom of the conduction band, and of height approximately 6 × 10¹³ cm^?2eV^?1. The experiments were carried out at two heating rates (0·1°K/sec and 0·01°K/sec), and the trap densities so obtained were identical.The second method consists of biasing the device into the accumulation mode at a fixed temperature thereby filling the traps at the silicon-silicon oxide interface. It is then short-circuited and the non-steady state transient current associated with the release of electrons from the interface traps is monitored. The energy distribution of the interface traps in the upper half of the forbidden gap is shown to be readily obtained from the transient currents, and is found to be identical to that obtained using the thermal technique.