SOINMOSFET沟道热载流子的应力损伤

研究了沟道热载流子应力所引起的SOI NMOSFET的损伤,发现在中栅压应力（Vg≈Vd/2）和高栅压应力（Vg≈Vd）条件下,器件损伤表面出单一的幂律规律;而在低栅压应力（Vgs≈Vth)下,多特性的退化规律便会表现出来。同时,应力漏电压的升高、应力时间的延续都会导致退化特性的改变。这使预测SOI器件的寿命变得非常困难。     

沟道热载流子导致的SOI NMOSFET's的退化特性

研究了沟道热载流子效应引起的SOI NMOSFET's的退化.在中栅压应力(Vg≈Vd/2)条件下,器件退化表现出单一的幂律规律;而在低栅压应力(Vgs≈Vth)下,由于寄生双极晶体管(PBT)效应的影响,多特性的退化规律便会表现出来,漏电压的升高、应力时间的延续都会导致器件退化特性的改变.对不同应力条件下的退化特性进行了详细的理论分析,对SOI NMOSFET'S器件退化机理提出了新见解.     

沟道热载流子导致的SOI NMOSFET's的退化特性

研究了沟道热载流子效应引起的SOI NMOSFET's的退化.在中栅压应力(Vg≈Vd/2)条件下,器件退化表现出单一的幂律规律;而在低栅压应力(Vgs≈Vth)下,由于寄生双极晶体管(PBT)效应的影响,多特性的退化规律便会表现出来,漏电压的升高、应力时间的延续都会导致器件退化特性的改变.对不同应力条件下的退化特性进行了详细的理论分析,对SOI NMOSFET'S器件退化机理提出了新见解.     

HALO结构pMOSFETs在V_g=V_d/2应力模式下应力相关的热载流子退化

研究了超薄栅(2 .5 nm )短沟HAL O- p MOSFETs在Vg=Vd/ 2应力模式下不同应力电压时热载流子退化特性.随着应力电压的变化,器件的退化特性也发生了改变.在加速应力下寿命外推方法会导致过高地估计器件寿命.在高场应力下器件退化是由空穴注入或者电子与空穴复合引起的,随着应力电压的下降器件退化主要是由电子注入引起的.最后,给出了两种退化机制的临界电压并在实验中得到验证     

HALO结构pMOSFETs在Vg=Vd/2应力模式下应力相关的热载流子退化

研究了超薄栅(2.5nm)短沟HALO-pMOSFETs在Vg=Vd/2应力模式下不同应力电压时热载流子退化特性.随着应力电压的变化,器件的退化特性也发生了改变.在加速应力下寿命外推方法会导致过高地估计器件寿命.在高场应力下器件退化是由空穴注入或者电子与空穴复合引起的,随着应力电压的下降器件退化主要是由电子注入引起的.最后,给出了两种退化机制的临界电压并在实验中得到验证.     

SOI NLIGBT热载流子效应研究

SOI NLIGBT中热载流子效应分别通过直流电压的应力测试、TCAD仿真和电荷泵测试三种方法进行了研究。其中,不同直流电压应力条件下测得的衬底电流Isub和导通电阻Ron用来评估因热载流子效应引起的器件退化程度。为了进行理论分析,对器件内部的电场强度和碰撞离化率也进行了仿真。测试得到的电荷泵电流直接验证了器件表面的损伤程度。最后讨论了SOI LIGBT在不同栅压条件下的退化机制。     

深亚微米PD和FD SOI MOS器件热载流子损伤的研究

研究了深亚微米PD和FD SOI MOS器件遭受热截流子效应(HCE)后引起的器件参数退化的主要差异及其特点，提出了相应的物理机制，以解释这种特性。测量了在不同应力条件下最大线性区跨导退化和闽值电压漂移，研究了应力Vg对HCE退化的影响，并分别预测了这两种器件的寿命，提出了10年寿命的0．3μm沟长的PD和FD SOI MOS器件所能承受的最大漏偏压。     

低压5V pMOS器件在不同栅偏置应力下的热载流子注入退化机理研究

研究了低压pMOS器件热载流子注入HCI（hot-carrier injection）退化机理,分析了不同的栅压应力下漏极饱和电流（Idsat）退化出现不同退化趋势的原因。结合实测数据并以实际样品为模型进行了器件仿真,研究表明,快界面态会影响pMOS器件迁移率,导致Idsat的降低;而电子注入会降低pMOS器件阈值电压（Vth）,导致Idsat的上升。当栅压为-7.5V时,界面态的产生是导致退化的主要因素,在栅压为-2.4V的应力条件下,电子注入在热载流子退化中占主导作用。     

F-N应力下SOI n-MOSFETs性能退化与栅控二极管产生-复合（G-R）电流的对应关系

本文验证了F-N应力导致的SOI n- MOSFET器件性能退化与栅控二极管的产生-复合（G-R）电流的对应关系。F-N应力导致的界面态增加会导致SOI-MOSFET结构的栅控二极管的产生-复合（G-R）电流增大,以及MOSFET饱和漏端电流,亚阈斜率等器件特性退化。通过一系列的SOI-MOSFET栅控二极管和直流特性测试,实验观察到饱和漏端电流的线性退化和阈值电压的线性增加,亚阈摆幅的类线性上升以及相应的跨导退化。理论和实验证明栅控二极管是一种很有效的监控SOI-MOSFET退化的方法。     

深亚微米SOI MOSFET低压热载流子效应研究

当器件尺寸进入深亚微米后，SOI MOS集成电路中的N沟和P沟器件的热载流子效应引起的器件退化已不能忽视。通过分别测量这两种器件的跨导、阈值电压等参数的退化与应力条件的关系，分析了这两种器件的退化规律，对这两种器件的热载流子退化机制提出了合理的解释。并模拟了在最坏应力条件下，最大线性区跨导Gmmax退化与漏偏压应力Vd的关系，说明不同沟长的器件在它们的最大漏偏压以下时，能使Gmmax的退化小于10％。     

Temperature dependence of hot-carrier degradation in silicon-on-insulator dynamic threshold voltage MOS transistors

The authors analyze the influence of temperature on hot-carrier degradation of silicon-on-insulator (SOI) dynamic threshold voltage MOS (DTMOS) devices. Both low and high stress gate voltages are used. The temperature dependence of the hot-carrier effects in DTMOS devices is compared with those in SOI partially depleted (PD) MOSFETs. Possible physical mechanisms to explain the obtained results are suggested. This work shows that even if the stress gate voltage is low, the degradation of DTMOS devices stressed at high temperature could be significant.     

部分耗尽SOI MOSFETs中沟道的非对称掺杂效应

利用二维模拟软件对部分耗尽SoI器件中的非对称掺杂沟道效应进行了模拟.详细地研究了该结构器件的电学性能,如输出特性,击穿特性.通过本文模拟发现部分耗尽SOI非对称掺杂沟道相比传统的部分耗尽SOI,能抑制浮体效应,改善器件的击穿特性.同时跟已有的全耗尽SOI非对称掺杂器件相比,部分耗尽器件性能随参数变化,在工业应用上具有可预见性和可操作性.因为全耗尽器件具有非常薄的硅膜,而这将引起如前栅极跟背栅极的耦合效应和热电子退化等寄生效应.     

部分耗尽SOI MOSFETs中沟道的非对称掺杂效应

利用二维模拟软件对部分耗尽SoI器件中的非对称掺杂沟道效应进行了模拟.详细地研究了该结构器件的电学性能,如输出特性,击穿特性.通过本文模拟发现部分耗尽SOI非对称掺杂沟道相比传统的部分耗尽SOI,能抑制浮体效应,改善器件的击穿特性.同时跟已有的全耗尽SOI非对称掺杂器件相比,部分耗尽器件性能随参数变化,在工业应用上具有可预见性和可操作性.因为全耗尽器件具有非常薄的硅膜,而这将引起如前栅极跟背栅极的耦合效应和热电子退化等寄生效应.     

Back gate effects on threshold voltage sensitivity to SOI thicknessin fully-depleted SOI MOSFETs

The dependence of threshold voltage on silicon-on-insulator (SOI) thickness is studied on fully-depleted SOI MOSFETs, and, for this purpose, back-gate oxide thickness and back gate voltage are varied. When the back gate oxide is thinner than the critical thickness dependent on the back gate voltage, the threshold voltage has a minimum in cases where the SOI film thickness is decreased, because of capacitive coupling between the SOI layer and the back gate. This fact suggests that threshold voltage fluctuations due to SOI thickness variations are reduced by controlling the back gate voltage and thinning the back gate oxide     

Analysis of temperature-induced saturation threshold voltage degradation in deep-submicrometer ultrathin SOI MOSFETs

This paper presents a systematic study of the temperature lowering influence on the saturation threshold voltage degradation in ultrathin deep-submicrometer fully depleted silicon-on-insulator (SOI) MOSFETs. It is observed that the difference between the threshold voltage obtained with low and high drain bias, increases at lower temperatures for nMOSFETs, whereas it is weakly temperature-dependent for pMOSFETs. Experimental results and two-dimensional numerical simulations are used to support the analysis. The influence of applied back gate bias on threshold voltage variation is also studied. It is demonstrated that the higher doping level into the body region provided by the halo ion implantation associated to the floating-body increases both the multiplication factor and the parasitic bipolar gain as the temperature is lowered contributing to the threshold voltage degradation. The absence of halo implantation efficiently improves this degradation. The use of double gate structure, even with high body doping level, suppress the saturation threshold voltage degradation in cryogenic operation.     

超深亚微米部分耗尽SOI NMOSFET关态应力下前栅和背栅晶体管损伤研究

The hot-carrier effect charactenstic in a deep submicron partially depleted SOI NMOSFET is investigated. Obvious hot-carrier degradation is observed under off-state stress.The hot-carrier damage is supposed to be induced by the parasitic bipolar effects of a float SOI device.The back channel also suffers degradation from the hot carrier in the drain depletion region as well as the front channel.At low gate voltage,there is a hump in the sub-threshold curve of the back gate transistor,and it does not shift in the same way as the main transistor under stress.While under the same condition,there is a more severe hot-carrier effect with a shorter channel transistor. The reasons for those phenomena are discussed in detail.     

High-performance embedded SOI DRAM architecture for the low-powersupply

This paper presents the high-performance DRAM array and logic architecture for a sub-1.2-V embedded silicon-on-insulator (SOI) DRAM. The degradation of the transistor performance caused by boosted wordline voltage level is distinctly apparent in the low voltage range. In our proposed stressless SOI DRAM array, the applied electric field to the gate oxide of the memory-cell transistor can he relaxed. The crucial problem that the gate oxide of the embedded-DRAM process must be thicker than that of the logic process can be solved. As a result, the performance degradation of the logic transistor can be avoided without forming the gate oxides of the memory-cell array and the logic circuits individually. In addition, the data retention characteristics can be improved. Secondly, we propose the body-bias-controlled SOI-circuit architecture which enhances the performance of the logic circuit at sub-1.2-V power supply voltage, Experimental results verify that the proposed circuit architecture has the potential to reduce the gate-delay time up to 30% compared to the conventional one. This proposed architecture could provide high performance in the low-voltage embedded SOI DRAM     

Successive charging/discharging of gate oxides in SOI MOSFET's bysequential hot-electron stressing of front/back channel

Hot-hole injection into the opposite channel of silicon-on-insulator (SOI) MOSFETs under hot-electron stress is reported. Sequential front/back-channel hot-electron stressing results in successive hot-electron/-hole injection, causing the threshold voltage to increase and decrease accordingly. This ability to inject hot holes into the opposite gate oxide can be used as an additional tool for studying the degradation mechanisms. Furthermore, it can be explored for possible use in designing SOI flash memory cells with back-channel-based erasing schemes     

Hot carrier induced degradation in mesa-isolated n-channel SOIMOSFETs operating in a Bi-MOS mode

A thorough investigation of hot carrier effects is made in mesa-isolated SOI nMOSFETs operating in the Bi-MOS mode (abbreviated as Bi-nMOSFETs). As a result of its unique hybrid operation mechanism, significant reduction of hot carrier induced maximum transconductance degradation and threshold voltage shift in the Bi-nMOSFET is observed in comparison with that in the conventional SOI nMOSFETs. Device lifetime of SOI Bi-nMOSFETs and conventional SOI nMOSFETs was roughly estimated for comparison. In view of the analysis of the degradation mechanism, the devices were stressed under different conditions. The post-stress body current and stress body current in Bi-nMOSFETs as a function of the stress time and stress drain voltage were evaluated as further proofs of the aging reasons. The hot electron injection is found to be the dominant degradation process in the SOI Bi-nMOSFETs. Compared with SOI nMOSFETs, SOI Bi-nMOSFETs show better immunity to the parasitic bipolar transistor action due to the body contact. In addition, the positive body bias can result in lowered hot hole injection into the gate oxide due to the provision of the generated hole leakage path, and thus decreased interface traps     

Analytical threshold voltage model for short channeln+-p+ double-gate SOI MOSFETs

Solving a two-dimensional (2-D) Poisson equation in the channel region, we have developed models for short channel n⁺-p⁺ double-gate SOI MOSFETs, and showed how to design a device with a decreased gate length, suppressing short channel threshold voltage shift ΔVth and subthreshold swing (S-swing) degradation. According to our model, we can design a 0.05 μm L_G device of which threshold voltage is 0.2 V, ΔVth is 25 mV, and S-swing is 65 mV/decade with a 3-nm-thick gate oxide and 12-nm-thick SOI