新型亚50纳米硅栅制作技术

提出并演示了一新型的低成本亚 5 0纳米多晶硅栅制作技术 .该技术的特点是它与光刻分辨率无关 ,即不需要高分辨率光刻技术 .纳米尺度的栅掩膜图案是由台阶侧壁图形的转移所形成 .实验结果表明 ,该技术制成的硅栅的栅长由形成侧壁图形的薄膜之厚度所决定 ,大致为该厚度的 75 %— 85 % .SEM照片显示硅栅的剖面为倒梯形结构 .与其它结构 (如矩形或正梯形 )相比 ,该结构有利于减少栅电阻 .     

用于纳米器件的电子束与光学混合光刻技术

成功开发出了一种可用于纳米结构及器件制作的电子束与光学光刻的混合光刻工艺。通过两步光刻工艺,在栅结构层上采用大小图形数据分离的方法,使用光学光刻形成大尺寸栅引出电极结构,利用电子束直写形成纳米尺寸栅结构,并通过图形转移工艺解决两次光刻定义的栅结构的叠加问题。此混合光刻工艺技术可以解决纳米电子束直写光刻技术效率较低的问题,同时避免了电子束进行大面积、高密度图形曝光时产生严重邻近效应影响的问题。这项工艺技术已经应用于先进MOS器件的研发,并且成功制备出具有良好电学特性、最小栅长为26 nm的器件。     

纳米压印制作半导体激光器的分布反馈光栅

分布反馈(DFB)光栅的制作是半导体激光器芯片的关键工艺,通过纳米压印技术在InP基片表面涂覆的光刻胶上压印出DFB光栅图形,并分别通过湿法腐蚀和干法刻蚀技术将光栅图形转移到InP基片上。所制作的DFB光栅周期为240nm(对应于1 550nm波长的DFB激光器),光栅中间具有λ/4相移结构。采用纳米压印技术制作的DFB光栅相对于通常双光束干涉法制作的光栅具有更好的均匀性以及更低的线条粗糙度,而且解决了双光束干涉法无法制作非均匀光栅的技术难题。相对于电子束直写光刻法,采用纳米压印技术制作DFB光栅具有快速与低成本的优势。采用纳米压印技术在InP基片上成功制作具有相移结构的DFB光栅,为进一步进行低成本高性能的半导体激光器芯片的制作奠定了良好基础。     

基于光刻版的无留膜紫外纳米压印技术研究

针对纳米压印光刻技术中压印脱模后的留膜去除问题,提出了一种基于光刻版的无留膜紫外纳米压印技术.采用传统的光刻版作为紫外压印模版,由于模版上铬层的遮蔽作用.使得铬层下面的光刻胶不被曝光,从而可以轻易地被去除.实验结果表明,该技术综合了压印与光刻各自的优点,可以获得无留膜厚度的压印图形,省去了压印后的留膜刻蚀工艺.从而避免了由于留膜厚度不均匀所带来的过刻蚀或欠刻蚀的问题.     

3333l/mmX射线全镂空自支撑透射光栅的制备与测试

针对我国对高线密度X射线镂空透射光栅在空间环境探测和激光等离子体诊断方面的需求,将电子束光刻和X射线光刻技术相结合,制备出3333l/mmX射线全镂空透射光栅,栅线宽度接近150nm,周期300nm,栅线厚度为500nm,有效光栅面积达到60%。首先利用电子束光刻和微电镀技术在镂空聚酰亚胺薄膜底衬上制备X射线母光栅掩模,然后利用X射线光刻和微电镀技术实现了光栅图形的复制品,之后采用紫外光刻和微电镀技术制作加强筋结构,最后通过腐蚀体硅和等离子体刻蚀聚酰亚胺完成镂空透射光栅的制作。在国家同步辐射实验室光谱辐射和计量实验站上对此光栅在5～23nm波段进行了衍射效率标定。标定结果表明所制备的光栅栅线平滑,占空比合理,侧壁陡直,不同光栅之间一致性好,完全可以满足应用需求。     

微光刻与微/纳米加工技术

介绍了微电子技术的关键工艺技术——微光刻与微/纳米加工技术,回顾了中国制版光刻与微/纳米加工技术的发展历程与现状,讨论了微光刻与微/纳米加工技术面临的挑战与需要解决的关键技术问题,并介绍了光学光刻分辨率增强技术、下一代光刻技术、可制造性设计技术、纳米结构图形加工技术与纳米CMOS器件研究等问题。近年来,中国科学院微电子研究所通过光学光刻系统的分辨率增强技术(RET),实现亚波长纳米结构图形的制造,并通过应用光学光刻系统和电子束光刻系统之间的匹配与混合光刻技术及纳米结构图形加工技术成功研制了20～50nm CMOS器件和100nm HEMT器件。     

利用RELACS辅助技术制作"T"型栅

利用RELACS化学收缩辅助技术制作了i线三层胶结构的"T"型栅。首先利用水溶性的化学收缩试剂RELACS,涂在曝光完成的光刻图形上,然后借由混合烘焙让光刻胶中的光酸分子因受热而产生扩散运动并进入到RELACS试剂内,催化RELACS试剂,让RELACS试剂中的高分子与交链分子产生交链反应,使得光刻胶表面形成新的一层不溶于水的交链层而达到光刻图形收缩的目的。此方法增加了细栅光刻的宽容度,降低了细栅光刻制作的难度,极易将0.5μm的栅条收缩到0.3μm,甚至更小,不但有效地减小了栅长,而且提高了细栅光刻的成品率。RELACS技术可以应用于不同光刻胶类型的"T"型栅制作中。     

高线密度X射线双光栅的研制

研究了采用高分辨率的100 kV电子束光刻和光学光刻系统相结合制作高线密度X射线双光栅的工艺技术,并且分析了电子束邻近效应校正技术在高线密度光栅制备中的应用。首先,利用电子束曝光和纳米电镀技术在同一衬底上制备两种不同线密度光栅图形;然后,利用光学光刻在2 000 lp/mm光栅上制备了自支撑加强筋结构。通过此技术制备的X射线双光栅成功集成了高线密度5 000 lp/mm透射光栅和2 000 lp/mm自支撑透射光栅,其栅线宽度分别为100和250 nm,金吸收体厚度达到400 nm。     

紫外纳米压印技术的图形转移层工艺研究

研究了紫外纳米压印技术的图形转移层工艺,通过改变膜厚进行压印对比实验,将转速控制在3000～4000r/min,成功地得到了50nm光栅结构的高保真图形,复型精度可以达到93.75%。同时阐明,纳米压印技术由于具有超高分辨率、低成本、高产量等显著特点,将成为下一代光刻技术(NGL)的主要候选者之一。     

高分辨率SiNx纳米压印模板的快速制备工艺

纳米压印技术是近年来国际新兴的纳米光刻技术,具有高分辨率、高效率和低成本等优点。本文结合电子束光刻技术和干法刻蚀技术开发了简洁的纳米压印SiNx光栅模板制造工艺。为提高工艺效率,引进高灵敏度的化学放大胶NEB-22胶（负性胶）作为电子光刻胶,用电子束光刻技术在NEB-22上刻出光栅图形,再利用其作为掩膜,经反应离子刻蚀后,将光栅图形转移到氮化硅上,得到所需模板。文中详细研究了NEB-22胶的电子束光刻特性及其干法刻蚀特性,指出了它作为电子束光刻胶的优点及它相对于铬掩膜而言作为干法刻蚀掩膜的不足。     

A robust spacer gate process for deca-nanometer high-frequency MOSFETs

This paper, presents a robust spacer technology for definition of deca-nanometer gate length MOSFETs. Conformal deposition, selective anisotropic dry-etching and selective removal of sacrificial layers enabled patterning of an oxide hard mask with deca-nanometer lines combined with structures defined with I-line lithography on a wafer. The spacer gate technology produces negligible topographies on the hard mask and no residual particles could be detected on the wafer. The line-width roughness of 40 nm poly-Si gate lines was 4 nm and the conductance of 200 μm long lines exhibited a standard deviation of 6% across a wafer. nMOSFETs with 45 nm gate length exhibited controlled short-channel effects and the average maximum transconductance in saturation was 449 μS/μm with a standard deviation of 3.7% across a wafer. The devices exhibited a cut-off frequency above 100 GHz at a drain current of 315 μA/μm. The physical and electrical results show that the employed spacer gate technology is robust and can define deca-nanometer nMOSFETs with high yield and good uniformity.     

A novel self-aligned T-shaped gate process for deep submicron SiMOSFET's fabrication

T-shaped gate electrode is highly desired for high-speed FET fabrication since it can significantly reduce the gate resistance. In this study, we propose and demonstrate a self-aligned method of forming T-shaped gate which is suitable for ULSI Si-MOSFET's fabrication. This method employs CMP planarization, BOE selective etching and poly-Si sidewall spacer techniques to form the T-shaped poly-Si gate structure. Ti and Co silicidation were also incorporated to demonstrate the effectiveness of this process. Our experimental results indicate that the proposed process not only reduces the parasitic gate resistance, but also improves the thermal stability of the gate structure     

Laser thermal processing of amorphous silicon gates to reduce poly-depletion in CMOS devices

One major challenge in advanced CMOS technology is to have adequate dopant activation at the polycrystalline silicon (poly-Si) gate/gate oxide interface to minimize the poly-Si depletion effect. In this paper, laser thermal processing (LTP) was employed to fabricate single or dual-layer poly-Si-gated MOS capacitors with ultrathin gate oxides. Capacitance-voltage data show that the carrier concentration at the poly-Si gate/gate oxide interface increases substantially when the devices are subjected to LTP prior to a rapid thermal anneal (RTA). Thus, LTP readily reduces the poly-depletion thickness in MOS devices. For p/sup +/-gated capacitors, this is achieved with boron penetration that is equivalent to the control sample with 1000/spl deg/C, 5 s RTA (without LTP). In addition, results from secondary ion mass spectrometry indicate that the concentration of dopants near the critical gate/gate oxide interface increases significantly after a post-LTP anneal, in good agreement with the electrical data. Time-dependent dielectric breakdown studies show that the gate oxide reliability is not degraded even after LTP at high fluences.     

Characterizing Fluorine-Ion Implant Effects on Poly-Si Thin-Film Transistors With ${hbox{Pr}}_{2}{hbox{O}}_{3}$ Gate Dielectric

The fluorine ion implantation applied to the polycrystalline silicon thin-film transistors (poly-Si TFTs) with high-k Pr₂O₃ as gate dielectric is investigated for the first time. Using the Pr₂O₃ gate dielectric can obtain a high gate capacitance density and thin equivalent-oxide thickness, exhibiting a greatly enhancement in the driving capability of TFT device. Introducing fluorine ions into the poly-Si film by fluorine ion implantation technique can effectively passivate the trap states in the poly-Si film and at the Pr₂O₃/poly-Si interface to improve the device electrical properties. The Pr₂O₃ TFTs fabricated on fluorine-implanted poly-Si film exhibit significantly improved electrical performances, including lower threshold voltage, steeper subthreshold swing, higher field-effect mobility, lower off-state leakage current, and higher on/off current ratio, as compared with the control poly-Si Pr₂O₃ TFTs. Also, the incorporation of fluorine ions also improves the reliability of poly-Si Pr₂O₃ TFTs against hot-carrier stressing, which is attributed to the formation of stronger Si-F bonds. Furthermore, superior threshold-voltage rolloff characteristic is also demonstrated in the fluorine-implanted poly-Si Pr₂O₃ TFTs. Therefore, the proposed scheme is a promising technology for high-performance and high-reliability solid-phase crystallized poly-Si TFT.     

A Novel Multiple-Gate Polycrystalline Silicon Nanowire Transistor Featuring an Inverse-T Gate

A novel multiple-gate field-effect transistor with poly-Si nanowire (NW) channels is proposed and fabricated using a simple process flow. In the proposed structure, poly-Si NW channels are formed with sidewall spacer etching technique, and are surrounded by an inverse-T gate and a top gate. When the two gates are connected together to drive the NW channels, dramatic performance enhancement as compared with the cases of single-gate operation is observed. Moreover, subthreshold swing as low as 103 mV/dec at $hbox{Vd} = hbox{2} hbox{V}$ is recorded. Function of using the top gate bias to modulate the threshold voltage of device operation driven by the inverse-T gate biases is also investigated in this letter.      

Fabrication of self-aligned 90-nm fully depleted SOI CMOS SLOTFETs

We have developed a novel sub-100-nm fully depleted silicon-on-insulator (SOI) CMOS fabrication process, in which conventional 248-nm optical lithography and nitride spacer technology are used to define slots in a sacrificial layer (SLOTFET process). This process features a locally thinned SOI channel with raised source-drain regions, and a low-resistance T-shaped poly-Si gate; Both n- and p-channel MOSFETs with 90-nm gate length have been demonstrated. At a 0.5 V bias voltage, ring-oscillator propagation delay of less than 50 ps per stage has been measured     

Depletion layer of gate poly-Si

The depletion effects of gate poly-Si are investigated in detail taking into consideration the fact that many-body effects due to carrier-carrier and carrier-ion interactions are different at the surface than in a bulk of the gate poly-Si. All calculations are self-consistently performed including an incomplete ionization of activated impurities in an iterative manner. As a result, it is found that the surface part of these interactions affects the equivalent oxide thickness determined by the capacitance-voltage fitting, and that the bulk part affects the determination of flat band potential. It is also found that the surface of the gate poly-Si is incompletely depleted, and the depletion layer is then wider than calculated when assuming the complete depletion (N/sub S//N/sub D/). The width of the incomplete depletion layer is studied in detail for the first time.     

The etchback approach: Enlarged process window for MuGFET gate etching

We present a new method to enlarge the process window for gate patterning on a surface with high topography. We have compared two approaches for the patterning of a poly-Si gate with oxide hard mask (HM) as used in multi-gate field effect transistors. In the first approach, referred to as ‘direct deposition’, a poly-Si layer of 60 nm is deposited on the substrate, whereas in the second, and new approach 200 nm poly-Si is deposited and anisotropically etched back to 60 nm. All subsequent process steps (i.e. HM deposition, lithography and gate etch) are identical. From ellipsometric thickness measurements, we conclude that for the etchback case the poly-Si film has a larger within-wafer-non-uniformity due to the deposition of a thicker film. On the other hand, top down and cross-section SEM after gate etch show that for the etchback approach there is a larger process window with respect to avoiding micro-masking by the oxide HM at topography steps. We demonstrate that less over-etch is needed during the HM opening step to achieve residue free patterning of the poly-Si film. For a poly-Si thickness of 100 nm, we were able to obtain a residue free gate etch process for both the direct deposition and the etchback approach. Electrical evaluation shows that device performance is not compromised when using the etchback approach.     

A 30 V Self-Aligned Metal/Poly-Si Replacement Gate Planar DMOS for DC/DC Converters

In this letter, a novel self-aligned metal/poly-Si gate planar double-diffused MOS (DMOS) is proposed and demonstrated for high-switching-speed and high-efficiency dc/dc converter applications. The self-aligned metal/poly-Si gate is realized by a replacement gate technology. The fabricated metal/poly-Si gate planar DMOS has a breakdown voltage of 36 V and a threshold voltage of 2.1 V. The gate sheet resistance of the metal/poly-Si gate is around 0.2 Omega/square, which is 50 times lower than that of the polysilicon gate. The low sheet resistance reduces the switching time as well as the power loss of the device during switching. For a device with a drain current of 69 A/cm², the turn-on and turn-off times are reduced from 29 to 25 ns and from 36 to 31 ns, respectively. The turn-on and turn-off switching energy losses are reduced by 22% and 15%, respectively