精确预计SiBJT微波功率器件峰值结温的方法

三维全热程热电一体地模拟了 Si BJT微波功率器件 .热场计算包括从芯片的有源区经芯片 -粘接层 -基片 -粘接层 -底座直到固定于 70℃的安装台面的整个散热过程 .在处理热电正反馈时把有源区的 6 0个基本单元 (子胞 )当成 6 0个并联子胞晶体管进行建模 ,子胞模型包括子胞晶体管本身、基区横向扩展电阻、发射区横向扩展电阻 .热电一体分析除了涉及 Vbe随温度变化外 ,还有子胞发射极有效面积随子胞发射极电流上升而下降的效应 (以下称面积效应 ) .与对有源区各点直接进行分析相比 ,子胞建模不仅大大简化了计算 ,而且摸拟结果与器件结构、版图结构、工艺参     

射频功率HBT热稳定性的一种新表征方法

从热电反馈网络角度出发,在考虑到晶体管发射极电流随温度的变化、发射结价带不连续性（△Ev）、重掺杂禁带变窄（△Eg）及基极和发射极加入镇流电阻（RB和RE）等情况下,首次较全面地给出了功率晶体管热稳定因子S表达式。用该表达式可以很方便、明了地对功率双极晶体管进行热稳定性分析。分析了镇流电阻对射频功率晶体管安全工作区以及S的影响。结果表明,功率异质结双极晶体管（HBT）热稳定性优于同质结双极晶体管（BJT）,适当选取RB和RE可使S=0,使由器件本身产生的耗散功率而引起的自加热效应被完全补偿,器件特性得以保持,不因自热而产生漂移,这是同质结器件所无法实现的。     

基区重掺杂对SiGe HBT热学性能的影响

相对于同质结晶体管,异质结双极晶体管(HBT)由于异质结的存在,电流增益不再主要由发射区和基区掺杂浓度比来决定,因此可以通过增加基区掺杂浓度来降低基区电阻,提高频率响应,降低噪声系数,但基区掺杂浓度对器件热特性影响的研究却很少。以多指SiGeHBT的热电反馈模型为基础,利用自洽迭代法分析了基区重掺杂对器件集电极电流密度和发射极指温度的影响。通过研究发现,随着基区浓度的增加,SiGe HBT将发生禁带宽度变窄,基区反向注入发射区的空穴电流增大;同时,基区少子俄歇复合增强,这些都将减小集电极电流密度,降低发射极指温度,从而抑制发射极指热电正反馈,提高器件的热稳定性。     

多晶硅发射极微波功率管的三维热电耦合模型

文章结合双层多晶硅发射极双极型微波功率管器件结构,采用步内建模法,首次建立了三维热电耦合模型,并进行了直流稳态模拟.模拟结果表明,新的三维热电耦合模型可准确预测功率管结温的均匀状况.与单子胞器件CI相比,多子胞器件C2的中心区域结温变化平缓,结温温度约为390K,比单子胞器件C1的结温温度下降约10K.此外,低热传导率...     

基于有源镇流改善射频功率管的热稳定性

提出一种基于有源电路的基极镇流方案,用以解决射频功率晶体管的电流集中和热稳定性问题.采用传感器检测非均匀结温分布,后级相邻触发电路触发功率器件子单元基极和发射极之间的镇流MOS管,通过分流来缓解电流集中,进而完成器件子单元的过温保护.模拟结果表明,该方案可以有效地实现对功率器件的保护,与传统的无源镇流电阻方法相比,改进后的器件具有更优良的增益特性.单个有源镇流电路仅消耗功率6.5 mW,占用面积为2 530 μm2.     

二维非等温的分布晶体管模型

本文提出了一个考虑了晶体管热电反馈效应的分布晶体管直流模型,称之为“二维非等温的分布晶体管模型”. 本模型考虑了基区高注入效应、Kirk效应以及由内基区电阻、发射极金属化电极薄层电阻所引起的电流横向及纵向集边效应,并计入了晶体管内温度分布的不均匀性对上述诸效应的影响. 借助计算机,利用下降法求解了描述本模型热电特性的非线性方程组,计算结果给出了晶体管发射区内温度、电流的二维分布数值,从而得到了晶体管热电反馈效应的定量描述,且理论结果与实验吻合良好. 利用本模型可进行功率晶体管的计算机辅助设计,预测功率晶体管的安全工作区并指导器件的可靠性设计.     

1.44~1.68GHz 220W硅微波脉冲功率晶体管

南京电子器件研究所近期研制成功1.44～1.68GHz 220 W硅微波脉冲功率晶体管.该器件在1.44～1.68 GHz频带内,脉宽200 μs,占空比10%和40V工作电压下,全带内脉冲输出功率大于220 W,功率增益大于7.1 dB,效率大于45%.该器件采用高效梳条状结构,单元间距6μm,发射极和基极线宽1.9μm,金属条间距1.6μm.每个器件由6个面积为1 600μm×800 μm功率芯片组成,每个功率芯片含有2个大功率子胞.整个器件包含12个大功率子胞、20个内匹配电容和200多条连接金丝.     

芯片粘接工艺对MEMS性能影响的单元库法模型

芯片粘接工艺引起的器件-封装热失配会对MEMS器件的可靠性和性能产生显著影响.常用FEM模拟在分析此类问题时比较费时且缺乏明确的理论意义.文中基于单元库法思路提出了该类问题的理论建模方法,并依此举例分析了芯片粘接工艺中各可变参数对双端固支梁pull-in电压的影响,其结论与Ansys模拟结果一致.该方法简单准确,对MEMS的封装-器件协同设计将有着实际的意义.     

芯片粘接工艺对MEMS性能影响的单元库法模型

芯片粘接工艺引起的器件-封装热失配会对MEMS器件的可靠性和性能产生显著影响.常用FEM模拟在分析此类问题时比较费时且缺乏明确的理论意义.文中基于单元库法思路提出了该类问题的理论建模方法,并依此举例分析了芯片粘接工艺中各可变参数对双端固支梁pull-in电压的影响,其结论与Ansys模拟结果一致.该方法简单准确,对MEMS的封装-器件协同设计将有着实际的意义.     

掺砷多晶硅发射极RCA晶体管

研究了掺砷多晶硅发射极RCA晶体管的工艺实验技术.以先进多晶硅发射极器件制备工艺为基础,在淀积发射极多晶硅之前,用RCA氧化的方法制备了一层超薄氧化层,并采用氮气快速热退火的方法处理RCA氧化层,制备出可用于低温超高速双极集成电路的掺砷多晶硅发射极RCA晶体管.晶体管的电流增益在-55-+125℃温度范围内的变化率小于15%,而且速度快,发射区尺寸为4×10μm2的RCA晶体管其特征频率可达3.3GHz.     

Thermal stability analysis of AlGaAs/GaAs heterojunction bipolartransistors with multiple emitter fingers

A numerical electro-thermal model was developed for AlGaAs/GaAs heterojunction bipolar transistors (HBT's) to describe the base current, current gain and output power dependence on junction temperature. The model is applied to microwave HBT devices with multi-emitter fingers. The calculated results of the common-emitter, current-voltage characteristics in the linear active region show a “current crush” effect due to inherent nonuniform junction temperature, current density and current gain distribution in the device. The formation of highly localized high temperature regions, i.e., hot spots, occur when the device is operating beyond the current-crush point. This thermally induced current instability imposes an upper limit on the power capability of HBT's. The dependence of this effect on various factors is discussed. These factors include the intrinsic parameters such as the base current ideality factor, the “apparent” valence band discontinuity, and the temperature coefficient of the emitter-base turn-on voltage, as well as the extrinsic factors such as the emitter contact specific resistance, the substrate thermal conductivity and the heat source layout     

Simulated turn-off of 4H-SiC gate turn-off thyristors with gateelectrodes on the p-base or the n-base

Turn-off simulations of a 4H-SiC GTO thyristor structure having a gated p-base and p-type substrate are compared with that having a gated n-base and n-type substrate. Two gate drive circuits are considered, one with a voltage source and resistor between the gate and adjacent emitter region, and the other with a voltage source and resistor between the gate and farthest emitter region. The gated n-base thyristor's substrate current increases atypically before the device turns off. Also, the gated n-base structure turns off when the gate circuit is connected directly to the emitter region furthest from the gate region, but the gated p-base structure does not. Furthermore, turn-off gain is lower for the gated n-base structure due to mobility differences as demonstrated by current-voltage (I-V) and current versus time (I-t) curves     

不受温度影响的电流源

为了改进电流源电路的温度特性,提出了一种对温度不敏感的高精度电流源的实现方案。与现有的电路相比．本电路并没有改变原来的主电路结构．而仅仅在参考电流源中增加了一个小电阻。它在零下50℃到150℃的大范围内的温度效应被限制在1％-2％。该电阻在芯片上是利用闲置区域布线的,因此并不会增加集成电路的制造成本。另外．该电阻是连接在恒流源中,不会增加芯片的功耗。     

From chip to inverter: Electro-thermal modeling and design for paralleled power devices in high power application

Power loss and thermal stress of semiconductor components are closely related to the reliability of high power inverter. In addition to the inverter electrical parameters, the size of semiconductor is also an important factor in inverter electro-thermal performance. In this paper, an electro-thermal model correlated with chip area and chip paralleled number is built to calculate the power switch loss and junction temperature. Then, the relationship between chips size and inverter loss/thermal behaviors can be established by this model, enabling more flexible in chip design to optimize the inverter efficiency and thermal loading. Finally, the inverter electro-thermal design procedure is established to properly select the chip area and number in a power switch. As a case study, the optimal chip paralleled structure in the high power inverter is estimated and the results are compared under varying inverter output frequency. By selecting the chip area and number in the target region, junction temperature can maintain in the limited range.     

Study of novel techniques for reducing self-heating effects in SOI power LDMOS

Self-heating effects in silicon-on-insulator (SOI) power devices have become a serious problem when the active silicon layer thickness is reduced and buried oxide thickness is increased. Hence, if the temperature of the active region rises, the device electrical characteristics can be seriously modified in steady state and transient modes. In order to alleviate the self heating, two novel techniques which lead to a better heat flow from active silicon layer to silicon substrate through the buried oxide layer in SOI power devices are proposed. No significant changes on device electrical characteristics are expected with the inclusion of the novel techniques. The electro-thermal performance of lateral power devices including the proposed techniques is also presented.     

GaAs/AlGaAs power heterobipolar transistor fabricated on silicon substrate

A GaAs/AlGaAs power HBT was fabricated on a silicon substrate, where the thermal conductance is reduced by a factor of 2.8 compared with that on bulk GaAs. Due to the newly developed monolithically grown ballast resistor in the emitter region, the experimentally fabricated device has shown the highest collector current of over 2.5 A for a device with an active device area of 0.14 mm/sup 2/.<>     

Thermal switchback in high ftepitaxial transistors

To investigate the reasons for second breakdown¹- or thermal switchback--and then to extend the safe operating area of power transistors, the behavior of an array of twenty small devices, mounted in parallel on a common heat sink, first without, then with an emitter series resistance, was evaluated. The first configuration suffers from β changes occurring at relatively low currents, an abrupt decrease of the base-to-emitter voltage, and failure to dissipate power. The configuration with emitter resistance shows a very tight collector-current base-current distribution, and normal base-to-emitter voltage characteristic. The same effect was obtained on a single large area device by employing a distributed thin-film resistor in series with the emitter. The uniform current distribution and the better thermal spreading of the heavily inter-digitated epitaxial device compensate for the small increase in saturation voltages due to the emitter resistance. Improved operating current levels and safe operating area are results observed on relatively small chip sizes.     

微电子芯片热电冷却系统的传热特性

针对微电子芯片热管理技术的现状和传统冷却技术的不足,建立微电子芯片热电冷却装置及其性能测试系统,采用热阻分析模型对传热过程进行研究.结果表明:在热电冷却过程中,帕尔帖效应占主导作用,TEC(热电冷却系统)自身热阻θ2随工作电流I的增大而降低.当芯片功率为20 W时,芯片与TEC冷面的界面热阻θ1在I为2.1 A时取得最...     

热处理对TaN薄膜电性能的影响

采用直流磁控溅射法在Al2O3陶瓷基片上制备了TaN薄膜,研究了热处理温度和时间对TaN薄膜的方阻(R□)及电阻温度系数(TCR)的影响。研究发现,在热处理时间为2h的条件下,热处理温度在200℃到600℃变化时,R□从12?/□增加到24?/□,TCR从15×10-6/℃下降到-80×10-6/℃;在热处理温度为300℃的条件下,热处理时间对R□及TCR影响较小,随着热处理时间的增长,R□及TCR略有变化。     

薄膜转移工艺制备的128×128规模高架桥式电阻阵

采用新的薄膜转移工艺,成功制备了128×128规模的高架桥式电阻阵。电阻阵的单元尺寸为50μm×50μm,占空比50%。初步测试了该高架桥电阻阵的两个基本指标,微桥的热时间常数和最高等效黑体温度,并对该电阻阵进行了成像实验。采用电学法测试单个微桥的时间常数τ约为4.5 ms,可在100Hz下工作。将整个面阵点亮,在8~12μm波段最高等效黑体温度达到250℃,推测在3~5μm波段最高等效黑体温度超过300±20℃。将整个器件全部点亮并驱动到最高温度时,器件的最大功率为30 W。该电阻阵可成功实现驱动显示成像。测试结果表明该高架桥式电阻阵初步满足红外景象产生器的要求。