槽栅MOS控制的晶闸管

报道了一种新结构的功率栅控晶闸管 ,称其为槽栅 MOS控制的晶闸管 (TMCT) .在该器件结构中 ,采用 U-MOS控制晶闸管的开启和关闭 .结构中不存在任何的寄生器件 ,因此 ,消除了在其它结构的栅控晶闸管中由寄生晶体管引起的各种问题 ,所以 TMCT会有优良的电特性 .实验结果表明 ,多元胞 TMCT (6 0 0 V,有源区面积0 .2 m m2 )的开态压降在 30 0 A / cm2 时为 1.2 5 V,最大可控电流在栅压为 - 2 0 V和电感负载下达到了 2 96 A/ cm2 .     

屏蔽栅结构射频功率VDMOSFET研制

在台栅垂直双扩散金属-氧化物-半导体场效应晶体管(VDMOSFET)的结构基础上,利用常规硅工艺技术,研制出了一种具有屏蔽栅结构的射频功率VDMOSFET器件,在多晶硅栅电极与漏极漂移区之间的氧化层中间加入了多晶硅屏蔽层,大幅度降低了器件的栅漏电容Cgd。研制出的屏蔽栅结构VDMOSFET器件的总栅宽为6 cm、漏源击穿电压为57 V、漏极电流为4.3 A、阈值电压为3.0 V、跨导为1.2 S,与结构尺寸相同、直流参数相近的台栅结构VDMOSFET器件相比,屏蔽栅结构VDMOSFET器件的栅漏电容降低了72%以上,器件在175 MHz、12 V的工作条件下,连续波输出功率为8.4 W、漏极效率为70%、功率增益为10 dB。     

双栅酞菁铜有机薄膜晶体管

有机薄膜晶体管以其成本低、柔性好、易加工等优点越来越受到人们的青睐,目前已广泛应用于低端器件。为了获得更实际的应用,OTFTs的性能还需进一步的提高和改善。文章中以酞菁铜(CuPc)为有机半导体材料,制备了双栅结构的有机薄膜晶体管,其阈值电压为-4.5V,场效应迁移率0.025cm2/V.s,开关电流比Ion/Ioff达到9.8×103,与单栅有机薄膜晶体管相比,双栅器件在更低的操作电压下获得了更大的输出电流,场效应迁移率更高,而且通过对两个栅压的调节,对导电沟道实现了更好的控制,器件性能有了较大的提高。     

全丝印后栅CNT-FED仿真及器件研究

模拟并制作了一种基于丝网印刷技术的后栅结构碳纳米管场发射显示器。采用有限元分析软件ANSYS对器件进行了电场模拟,优化了阴极宽度、阴极厚度、阴极间隙、介质层厚度等结构参数。取最优参数制作了像素为30×30,发光面积为54mm×54mm的单色显示屏。在阳压为1500V、栅压为300V时,器件发射电流密度达到5μA/cm2。该器件制作成本低,稳定性和均匀性良好,可矩阵寻址实现字符显示。     

新型双异质结双平面掺杂功率PHEMT

设计并制作了双异质结双平面掺杂的Al0 .2 4 Ga0 .76 As/ In0 .2 2 Ga0 .78As/ Al0 .2 4 Ga0 .76 As功率PHEMT器件,采用双选择腐蚀栅槽结构,有效提高了PHEMT器件的输出电流和击穿电压.对于1μm栅长的器件,最大输出电流为5 0 0 m A/ mm ,跨导为2 75 m S/ m m,阈值电压为- 1 .4 V,最大栅漏反向击穿电压达到了33V .研究结果表明,在栅源间距一定时,栅漏间距对于器件的输出电流、跨导和击穿电压有很大关系,是设计功率PHEMT的关键之一.     

PDSOI体源连接环形栅nMOS特性研究

提出了一种基于部分耗尽绝缘体上硅的体源连接环形栅nMOS器件,并讨论了相应的工艺技术和工作机理。采用体源连接环形栅器件结构,有效地抑制了浮体环形栅器件中存在的浮体效应和寄生双极晶体管效应,使器件性能得到很大的提高。消除了浮体环形栅器件的反常亚阈值斜率和Kink效应,DIBL从120.7mV/V降低到3.45mV/V,关态击穿电压从4.8V提高到12.1V。最后指出,体源连接环形栅器件非常适合于抗辐照加固等应用领域。     

1OOV高压pMOS器件研制

研制出适用于100V高压集成电路的厚栅氧高压pMOS器件.在器件设计过程中利用TCAD软件对器件结构及性能进行了模拟和优化,开发出与0.8μm n阱标准CMOS工艺兼容的高压工艺流程,并试制成功.实验结果表明,该器件关态击穿电压为-158V,栅压-100V时饱和驱动电流达17mA(W/L=100μm/2μm),可以在100V高压下安全工作.     

具有136 GHz的0.18μm GaAs Metamorphic HEMT器件

应用电子束直写技术成功制作了栅长0.18μm的高性能In0.52Al0.48As/In0.53Ga0.47As MHEMT.从工艺角度,结合器件的小信号等效电路的理论分析,优化了器件结构,特别是T形栅结构.从而减小了器件寄生参数,达到了较好的器件性能.最终制作的In0.52Al0.48As/In0.53Ga0.47As MHEMT饱和电流达到275 mA/mm,夹断电压-0.8 V,在Uga为-0.15 V时的最大非本征跨导gm为650 mS/mm,截止频率ft达到136 GHz,最大振荡频率fmax大于120 GHz.     

100V高压pMOS器件研制

研制出适用于100V高压集成电路的厚栅氧高压pMOS器件. 在器件设计过程中利用TCAD软件对器件结构及性能进行了模拟和优化，开发出与0.8μm n阱标准CMOS工艺兼容的高压工艺流程，并试制成功. 实验结果表明，该器件关态击穿电压为-158V，栅压-100V时饱和驱动电流达17mA (W/L=100μm/2μm) ，可以在100V高压下安全工作.     

3300V逆导型IGBT器件仿真

基于现有仿真平台,设计一款3 300V/50A逆导型绝缘栅双极晶体管器件(逆导型IGBT或RC-IGBT),元胞采用场截止型平面栅结构,元胞设计中采用载流子增强技术(EP),元胞注入采用自对准工艺,背面P型集电极采用透明集电极技术,降低IGBT工作模式下的饱和压降。采用二维数值仿真研究了器件结构及结构参数对器件性能的影响,通过结构参数拉偏,折衷优化IGBT与内集成二极管的性能参数,仿真得到的3 300V/50A逆导型IGBT器件饱和压降为3.4V,二极管导通压降为2.3V,阈值电压为5.6V,击穿电压为4 480V,与相同电压等级的分立IGBT器件和二极管性能相当。     

Zero-voltage-zero-current switching in high-output-voltagefull-bridge PWM converters using the interwinding capacitance

A novel zero-voltage and zero-current-switching (ZVZCS) full-bridge (FB) pulsewidth-modulated (PWM) power converter is proposed. The new converter uses the interwinding capacitance and a small primary-side inductor to achieve a zero-current-zero-voltage turn off and a zero-current turn on of the passive-to-active leg transistors. The turn off of the active-to-passive leg transistors is with zero voltage, and the turn on is with zero voltage and zero current across them. The ringing caused by the parasitic interwinding capacitance and by the reverse recovery of the rectifiers is reduced. The new converter is attractive for high-output-voltage applications (600-1000 V), where the interwinding capacitance is sufficiently dominant. In addition, switches such as insulated gate bipolar transistors (IGBTs) and MCTs can be used at higher frequencies which is particularly desirable for high-power application (above 2 kW). The experimental results obtained from an IGBT-based 62.5-kHz DC/DC power converter with a rated output voltage of 600 V and a nominal power of 1.2 kW are presented     

Analysis of transit times and minority carrier mobility in n-p-n 4H-SiC bipolar junction transistors

An analysis of the transit times and minority carrier mobility in n-p-n 4H-SiC RF bipolar junction transistors is presented. These parameters were extracted from small signal RF measurements on 4H-SiC RF transistors with three different base thicknesses: 100, 140, and 200 nm. The study shows that the room temperature minority carrier electron mobility is 215 cm/sup 2//V/spl middot/s for a base Al doping of N/sub B/=4/spl times/10/sup 18/ cm/sup -3/. The analysis reveals that the collector charging time /spl tau//sub C/ and the parasitic charging time /spl tau//sub P/ from the capacitance between metal pads and the underlying collector region have a significant effect on the transistors RF performance. The calculated RF gain is in good agreement with the measured results.     

Engineering density of semiconductor-dielectric interface states to modulate threshold voltage in OFETs

Threshold-voltage control is critical to the further development of pentacene organic field-effect transistors (OFETs). In this paper, we demonstrate that the threshold voltage can be tuned through chemical treatment of the gate dielectric layer. We show that oxygen plasma treatment of an organic polymer gate dielectric, parylene, introduces traps at the semiconductor-dielectric interface that strongly affect the OFET performance. Atomic force microscopy, optical microscopy using crossed-polarizers, and current-voltage and capacitance-voltage characterization were performed on treated and untreated devices. A model is presented to account for the effects of trap-introduced charges, both 1) fixed charges (2.0/spl times/10/sup -6/ C/cm/sup 2/) that shift the threshold voltage from -17 to +116 V and 2) mobile charges (1.1/spl times/10/sup -6/ C/cm/sup 2/) that increase the parasitic bulk conductivity. This technique offers a potential method of tuning threshold voltage at the process level.     

Vertical scaling of 0.25-/spl mu/m emitter InP/InGaAs single heterojunction bipolar transistors with f/sub T/ of 452 GHz

Vertical scaling of the epitaxial structure has allowed submicron InP/InGaAs-based single heterojunction bipolar transistors (SHBTs) to achieve record high-frequency performance. The 0.25/spl times/16 /spl mu/m/sup 2/ transistors, featuring a 25-nm base and a 100-nm collector, display current gain cut-off frequencies f/sub T/ of 452 GHz. The devices operate at current densities above 1000 kA/cm/sup 2/ and have BV/sub CEO/ breakdowns of 2.1 V. A detailed analysis of device radio frequency (RF) parameters, and delay components with respect to scaling of the collector thickness is presented.     

A Monolithically Integrated 12V/5V Switch-Capacitor DC-DC Converter

Motivated by the battery-operated applications that demand compact,lightweight andefficient DC-DC converters,many kinds of converter circuits have been published.Amongthem,resonantconverters and the soft-switching convertershave greatl...     

A 50 dB variable gain amplifier using parasitic bipolar transistorsin CMOS

A variable-gain amplifier (VGA) with a gain range of 50 dB has been implemented in a standard 3 μm CMOS process using parasitic lateral and vertical bipolar transistors to form the core of the circuit. The bipolar transistors had been characterized extensively. The VGA has a bandwidth larger than 3 MHz over the whole gain range and operates on a single 5 V power supply. The active area is about 0.8×0.9 mm²     

Electrical characteristics of 8-/spl Aring/ EOT HfO/sub 2//TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown junctions

The authors demonstrate high-performing n-channel transistors with a HfO/sub 2//TaN gate stack and a low thermal-budget process using solid-phase epitaxial regrowth of the source and drain junctions. The thinnest devices have an equivalent oxide thickness (EOT) of 8 /spl Aring/, a leakage current of 1.5 A/cm/sup 2/ at V/sub G/=1 V, a peak mobility of 190 cm/sup 2//V/spl middot/s, and a drive-current of 815 /spl mu/A//spl mu/m at an off-state current of 0.1 /spl mu/A//spl mu/m for V/sub DD/=1.2 V. Identical gate stacks processed with a 1000-/spl deg/C spike anneal have a higher peak mobility at 275 cm/sup 2//V/spl middot/s, but a 5-/spl Aring/ higher EOT and a reduced drive current at 610 /spl mu/A//spl mu/m. The observed performance improvement for the low thermal-budget devices is shown to be mostly related to the lower EOT. The time-to-breakdown measurements indicate a maximum operating voltage of 1.6 V (1.2 V at 125 /spl deg/C) for a ten-year lifetime, whereas positive-bias temperature-instability measurements indicate a sufficient lifetime for operating voltages below 0.75 V.     

Study of trapping phenomenon in 4H-SiC MESFETs: dependence on substrate purity

This work demonstrates that the "purity", meaning the low density of electron traps in a semi-insulating (SI) SiC substrate, can be crucial for the electrical characteristics of 4H-SiC MESFETs. Structures realized on two types of SI substrates have been investigated. The first kind is vanadium doped substrates grown by the classical Physical Vapor Transport (PVT) sublimation technique. The second kind are extremely low vanadium content SI substrates grown by the high temperature CVD (HTCVD) technique. For all the transistors, I/sub d/-V/sub ds/ measurements have been performed as a function of temperature. Different parasitic effects have been observed on the static output characteristics in the case of PVT substrates. Frequency dispersion measurements of the transconductance and drain-source output conductance, have next been realized. The results give clear evidence of the presence of deep traps in the transistors realized on PVT substrates. Those traps have an activation energy of 1.05 eV and a capture cross section between 10/sup -18/ cm/sup -2/ and 10/sup -19/ cm/sup -2/. They are most probably related to vanadium. The correlation between the presence of these traps and the parasitic effects on the output characteristics is discussed and the trap localization in the structure is established. In the case of HTCVD very low vanadium substrates, no parasitic effect have been observed and the presence of traps was not detected by the different characterization techniques.     

A novel high-performance asymmetric hetero-doped S/D high-voltage MOSFET

A novel high-voltage MOSFET structure, using a simple yet effective concept of an asymmetric hetero-doped source/drain (S/D) is proposed. The asymmetric hetero-doped S/D reduces the on-state resistance of the transistor due to the high doping used for device drain drift, provides excellent ruggedness for parasitic NPN turned-on due to a minimized n/sup +/ source spacer, and also raises the device breakdown voltage due to charge compensation in the composite drain drift region. Therefore, the asymmetric hetero-doped S/D structure allows the high voltage MOSFET to have a high current handling capability with a small device size. This in turn causes the R (sp, on) to be low, leading to high performance for the power device when used in a power integrated circuit. Measured results show that a 24-V breakdown voltage new device with a low-cost two-layer metal (Al) back-end achieves very low R (sp, on) of 0.166 m/spl Omega//spl middot/cm/sup 2/. Furthermore, the new device with a 65-V high-side capability achieves good isolation performance even when switching S/D to -20 V and also gets a cutoff frequency of 13 GHz at a gate voltage of 5.5 V.