4H-SiC混合 PN/ Schottky二极管的研制

报道了 4H- Si C混合 PN / Schottky二极管的设计、制备和特性 .该器件用镍作为肖特基接触金属 ,使用了结终端扩展 (JTE)技术 .在肖特基接触下的 n型漂移区采用多能量注入的方法形成 P区而组成面对面的 PN结 ,这些 PN结将肖特基接触屏蔽在高场之外 ,离子注入的退化是在 15 0 0℃下进行了 30 min.器件可耐压 6 0 0 V,在 6 0 0 V时的最小反向漏电流为 1× 10 - 3A/ cm2 . 10 0 0μm的大器件在正向电压为 3V时电流密度为 2 0 0 A/ cm2 ,而 30 0μm的小尺寸器件在正向电压为 3.5 V电流密度可达 10 0 0 A/ cm2     

3300 V-10 A SiC肖特基二极管北大核心CSCD

利用一次离子注入同时形成有源区和结终端结构,实现3 300 V 4H-SiC肖特基二极管。器件的正向电压为1.7 V时,电流达到10.3 A,相应电流密度为100 A/cm2,比导通电阻为7.77 mΩ·cm2。在3 300 V反向偏置电压下反向漏电流为226μA。测试同一晶圆上的pn二极管显示,设计的场限环结终端击穿电压可以达到4 000 V,达到仿真结果的95%。分析发现肖特基二极管的漏电流主要由肖特基接触的热场电子发射产生,有源区的肖特基接触线宽直接影响器件的正向电流密度和反向漏电流。设计合适的肖特基接触宽度是实现高性能器件的关键。     

3300 V-10 A SiC肖特基二极管

利用一次离子注入同时形成有源区和结终端结构,实现3 300 V 4H-SiC肖特基二极管。器件的正向电压为1.7 V时,电流达到10.3 A,相应电流密度为100 A/cm2,比导通电阻为7.77 mΩ·cm2。在3 300 V反向偏置电压下反向漏电流为226μA。测试同一晶圆上的pn二极管显示,设计的场限环结终端击穿电压可以达到4 000 V,达到仿真结果的95%。分析发现肖特基二极管的漏电流主要由肖特基接触的热场电子发射产生,有源区的肖特基接触线宽直接影响器件的正向电流密度和反向漏电流。设计合适的肖特基接触宽度是实现高性能器件的关键。     

2700V4H-SiC结势垒肖特基二极管

在76.2 mm 4H-SiC晶圆上采用厚外延技术和器件制作工艺研制的结势垒肖特基二极管(JBS).在室温下,器件反向耐压达到2700 V.正向开启电压为0.8V,在VF=2V时正向电流密度122 A/cm2,比导通电阻Ron=8.8 mΩ·cm2.得到肖特基接触势垒qφв=1.24 eV,理想因子n=1.     

4500V碳化硅肖特基二极管研究

设计了一种阻断电压4 500V的碳化硅(SiC)结势垒肖特基(JBS)二极管。采用有限元仿真的方法对器件的外延掺杂浓度和厚度以及终端保护效率进行了优化。器件采用50μm厚、掺杂浓度为1.2×1015cm-3的N型低掺杂区。终端保护结构采用保护环结构。正向电压4V下导通电流密度为80A/cm2。     

碳化硅混合PiN/Schottky二极管的二维模拟

利用模拟软件MEDICI对碳化硅混合PiN/Schottky二极管(MPS)的输运机理及伏安特性进行了模拟.输运机理的模拟结果表明MPS的工作原理是正向肖特基起主要作用,而反向时PN结使漏电流大大减小.伏安特性的模拟结果表明MPS的正向压降小,电流密度大,在2V正向偏压下达10-5A/μm,反向漏电流小,击穿电压高(2000V左右),可以通过改变肖特基和PN结的面积比来调整MPS的性能,与硅MPS、碳化硅PN结以及碳化硅肖特基二极管相比具有明显的优势,是理想的功率整流器.     

碳化硅混合PiN/Schottky二极管的二维模拟

利用模拟软件MEDICI对碳化硅混合PiN/Schottky二极管(MPS)的输运机理及伏安特性进行了模拟.输运机理的模拟结果表明MPS的工作原理是正向肖特基起主要作用,而反向时PN结使漏电流大大减小.伏安特性的模拟结果表明MPS的正向压降小,电流密度大,在2V正向偏压下达10-5A/μm,反向漏电流小,击穿电压高(2000V左右),可以通过改变肖特基和PN结的面积比来调整MPS的性能,与硅MPS、碳化硅PN结以及碳化硅肖特基二极管相比具有明显的优势,是理想的功率整流器.     

3300V碳化硅肖特基二极管及混合功率模块研制

基于数值仿真结果,采用结势垒肖特基(JBS)结构和多重场限环终端结构实现了3 300 V/50 A 4H-SiC肖特基二极管(SBD),所用4H-SiC外延材料厚度为35 μm、n型掺杂浓度为2× 1015cm-3.二极管芯片面积为49 mm2,正向电压2.2V下电流达到50 A,比导通电阻13.7 mΩ· cm2;反偏条件下器件的雪崩击穿电压为4 600 V.基于这种3 300 V/50 A 4H-SiC肖特基二极管,研制出3 300 V/600 A混合功率模块,该模块包含24只3 300 V/50 A Si IGBT与12只3 300 V/50 A 4H-SiC肖特基二极管,SiC肖特基二极管为模块的续流二极管.模块的动态测试结果为:反向恢复峰值电流为33.75 A,反向恢复电荷为0.807 μC,反向恢复时间为41 ns.与传统的Si基IGBT模块相比,该混合功率模块显著降低了器件开关过程中的能量损耗.     

高电流密度金刚石肖特基势垒二极管研究

报道了一种具有高正向电流密度和高反向击穿场强的垂直型金刚石肖特基势垒二极管器件。采用微波等离子体化学气相沉积(MPCVD)技术在高掺p~+单晶金刚石衬底上外延了一层275 nm厚的低掺p~-金刚石漂移层,并通过在样品背面和正面分别制备欧姆和肖特基接触电极完成了器件的研制。欧姆接触比接触电阻率低至1.73×10~(-5)Ω·cm~2,肖特基接触理想因子1.87,势垒高度1.08 eV。器件在正向-10 V电压时的电流密度达到了22 000 A/cm~2,比导通电阻0.45 mΩ·cm~2,整流比1×10~(10)以上。器件反向击穿电压110 V,击穿场强达到了4 MV/cm。     

高性能SiC整流二极管研究

在n型4H-SiC单晶导电衬底上制备了具有MPS(merged p-i-n Schottky diode)结构和JTE(junction termination extension)结构的肖特基势垒二极管。通过高温离子注入及相应的退火工艺,进行了区域性p型掺杂,形成了高真空电子束蒸发Ni/Pt/Au复合金属制备肖特基接触,衬底溅射Ti W/Au并合金做欧姆接触,采用场板和JTE技术减小高压电场集边效应。该器件具有良好的正向整流特性和较高的反向击穿电压。反向击穿电压可以达到1300V,开启电压约为0.7V,理想因子为1.15,肖特基势垒高度为0.93eV,正向电压3.0V时,电流密度可以达到700A/cm2。     

Design, fabrication, and characterization of low forward drop, low leakage, 1-kV 4H-SiC JBS rectifiers

The 1-kV 4H-SiC planar junction barrier Schottky (JBS) rectifiers were designed, fabricated, and characterized. Different p+ implantation dosages and activation anneal methods were used to determine an optimum baseline process. Using the optimized process, the forward drop of our JBS rectifiers is <1.5 V while the reverse leakage current density is <1/spl times/10/sup -5/ A/cm/sup -2/. Blocking voltage>1 kV was achieved using a single-zone junction termination extension termination. It was shown experimentally that 4-/spl mu/m p-type implantation window spacing gives an optimum tradeoff between forward drop voltage and leakage current density for these rectifiers, yielding a specific on-resistance of 3 m/spl Omega//spl middot/cm/sup 2/.     

3 A/40 V新型肖特基势垒二极管的设计与研制

为提高传统肖特基二极管的击穿电压,减小了器件的漏电流,提高芯片利用率,文中设计研制了适合于裸片封装的新型肖特基势垒二极管(SBD)。利用Silvaco Tcad软件模拟,在器件之间采用PN结隔离,器件周围设计了离子注入形成的保护环,实现了在浓度和厚度分别为7.5×1012 cm-3和5 μm的外延层上,制作出了反向击穿电压45 V和正向导通压降0.45 V的3 A/45 V肖特基二极管,实验和仿真结果基本吻合。此外,还开发了改进SBD结构、提高其电特性的工艺流程。     

GaN and AlGaN high-voltage rectifiers grown by metal-organic chemical-vapor deposition

In this paper, we report the study of the electrical characteristics of GaN and AlGaN vertical p-i-n junctions and Schottky rectifiers grown on both sapphire and SiC substrates by metal-organic chemical-vapor deposition. For GaN p-i-n rectifiers grown on SiC with a relatively thin “i” region of 2 μm, a breakdown voltage over 400 V, and forward voltage as low as 4.5 V at 100 A/cm² are exhibited for a 60-μm-diameter device. A GaN Schottky diode with a 2-μm-thick undoped layer exhibits a blocking voltage in excess of ∼230 V at a reverse-leakage current density below 1 mA/cm², and a forward-voltage drop of 3.5 V at a current density of 100 A/cm². It has been found that with the same device structure and process approach, the leakage current of a device grown on a SiC substrate is much lower than a device grown on a sapphire substrate. The use of Mg ion implantation for p-guard rings as planar-edge terminations in mesageometry GaN Schottky rectifiers has also been studied.     

Fabrication of self-aligned graded junction termination extensions with applications to 4H-SiC P-N diodes

The properties of SiC make this wide band-gap semiconductor a promising material for high power devices. This potential is demonstrated in various devices, such as p-n diodes, Schottky diodes, bipolar junction transistors, thyristors, etc., all of which require adequate and affordable termination techniques to reduce leakage current and increase breakdown voltage in order to maximize power-handling capabilities. In this paper, we describe a technique for fabricating a graded junction termination extension (GJTE) that is effective and self-aligned, a feature that simplifies the implantation process during fabrication and, therefore, has the potential to reduce production costs. Implanted anode p-n diodes fabricated using this technique on 10-μm thick n⁻ epitaxial layer had a maximum breakdown voltage of 1830 V. This was comparable to the ideal parallel-plane breakdown of 1900 V predicted by numerical simulation.     

A high-speed ITO-InAlAs-InGaAs Schottky-barrier photodetector

A high-speed and high-sensitivity vertical indium-tin-oxide-InAlAs-InGaAs Schottky barrier photodetector has been designed, fabricated, and characterized. The devices had dark current densities as low as 8.87/spl times/10/sup -5/ A/cm/sup -2/ at an applied bias of 5 V. The responsivity for all the devices tested ranged from 0.55-0.60 A/W at a wavelength of 1.31 /spl mu/m, and 0.563-0.583 A/W at 1.55 /spl mu/m. The 15-/spl mu/m diameter devices exhibited a -3 dB bandwidth of 19 and 25 GHz at a wavelength of 1.55 /spl mu/m and an applied bias of 5 and 10 V, respectively. These are the best values of responsivity and bandwidth for a vertical InGaAs-based Schottky-barrier photodetector reported to date.     

高能Si~+注入Sl-GaAs形成n型埋层

本文报导0.6～5MeV高能Si~+离子注入LEC半绝缘GaAs的快速退火效果,在950℃温度下退火5秒得到最佳电特性.采用多能量叠加注入已制备出平均深度在1.2μm,厚约1.7μm的n~+深埋层,载流子浓度为3～5×10~(17)cm~(-3).在近表面单晶层上作成了性能良好的肖特基接触,其势垒高度约为0.7V.     

采用场板和B+离子注入边缘终端技术的Ti/4H-SiC肖特基势垒二极管

采用自主外延的4H-SiC外延片,利用PECVD生长的SiO2做场板介质,B+离子注入边缘终端技术,制造了Ti/4H-SiC肖特基势垒二极管.测试结果表明,Ti/4H-SiC肖特基势垒二极管的理想因子n=1.08,势垒高度(ψe)=1.05eV,串联电阻为6.77mΩ·cm2,正向电压为4V时,电流密度达到430A/cm2.反向击穿电压大于1.1kV,室温下,反向电压为1.1kV时,反向漏电流为5.96×10-3 A/cm2.     

Design of edge termination for GaN power Schottky diodes

The GaN Schottky diodes capable of operating in the 300–700-V range with low turn-on voltage (0.7 V) and forward conduction currents of at least 10 A at 1.4 V (with corresponding forward current density of 500 A/cm²) are attractive for applications ranging from power distribution in electric/hybrid electric vehicles to power management in spacecraft and geothermal, deep-well drilling telemetry. A key requirement is the need for edge-termination design to prevent premature breakdown because of field crowding at the edge of the depletion region. We describe the simulation of structures incorporating various kinds of edge termination, including dielectric overlap and ion-implanted guard rings. Dielectric overlap using 5-μm termination of 0.1–0.2-μm-thick SiO₂ increases the breakdown voltage of quasi-vertical diodes with 3-μm GaN epi thickness by a factor of ∼2.7. The use of even one p-type guard ring produces about the same benefit as the optimized dielectric overlap termination.     

Demonstration of the first 10-kV 4H-SiC Schottky barrier diodes

This letter reports the demonstration of the first 4H-SiC Schottky barrier diode (SBD) blocking over 10 kV based on 115-/spl mu/m n-type epilayers doped to 5.6 /spl times/ 10/sup 14/ cm/sup -3/ through the use of a multistep junction termination extension. The blocking voltage substantially surpasses the former 4H-SiC SBD record of 4.9 kV. A current density of 48 A/cm/sup 2/ is achieved with a forward voltage drop of 6 V. The Schottky barrier height, ideality factor, and electron mobility for this very thick epilayer are reported. The SBD's specific-on resistance is also reported.