基于模块电路结构的BP神经网络及共应用研究

本文采用一种简化的ＢＰ（Ｂａｃｋ Ｐｒｏｐａｇａｔｉｏｎ）神经网络硬件模块实现方法。该方法利用全电流模式电路组成神经元模块，再用若干模块构成简化的ＢＰ神经网络。所提出的模块结构网络系统具有在线学习和在线权值存储能力，且可应用于实现偏、解码和二维图像识别，文中提供了ＰＳＰＩＣＥ和高级语言计算机仿真结果。     

浅析BP神经网络基本模型的C语言实现

BP神经网络已经成为应用最为广泛的神经网络模型之一。而人工神经网络是对人脑真正神经工作的简化生物模型。为了加深对神经网络的理解,利用推导公式来详细分析其最后的输出值和误差。这里旨在阐述用C语言实现BP神经网络基本模型,在BP神经网络的初始化函数中采用了归一化处理的方法,另外就是对神经元的权重初始化;而BP神经网络训练函数是整个BP神经网络形成的引擎,驱动着样本训练过程的执行。     

基于FPGA的人工神经网络系统的实现方孩

为了改变人工神经网络的研究仅仅局限于算法.只是在通用的串行或并行计算机上模拟实现的现状,针对函数逼近问题,将BP神经网络的结构分为3个模块,采用VHDL语言完成对各个模块的硬件描述,并使用Alters公司的QuartusII 6.1综合软件进仿真和调试,然后在CycloneII系列FPGA上实现了能够进行片上学习并完成函数逼近的BP神经网络系统.测试结果证明,该系统能够很好地完成在线学习,并能满足一般系统应用的速度和精度的要求,验证了该方法的有效性.     

BP神经网络PID的气动位置控制系统的研究

本文提出了一种将常规PID控制与BP神经网络相结合的自适应PID控制器,该控制器运用神经网络和BP算法实现了对PID参数的在线调整,利用变步长法和引入动量项来改进BP神经网络学习算法,有效减小了学习过程的振荡趋势,改善了收敛性,避免了学习过程陷入某些局部最小值,并将其用于在线调整气动位置伺服控制系统的PID参数,实现具有最佳组合的PID控制。MATLAB仿真表明,本文控制算法的静态特性、动态品质良好,鲁棒性强。     

基于BP神经网络的机械臂轨迹控制研究

针对六自由度机械臂耦合性强、时变、非线性等性能,基于拉格朗日动力学建模方法,文章采用BP神经网络逼近模型,实现高精度轨迹跟踪。该方法根据六自由度机械臂本体采集的数据进行黑箱辨识建模解耦,建模过程采用BP神经网络逼近,提升建模精度、简化建模过程。针对解耦后的系统,还需建立PID闭环控制器进一步实现轨迹跟踪控制。仿真及实验结果表明,基于BP神经网络的PID控制器能够改善系统的鲁棒性和稳定性,并有效抑制抖动。     

基于PID-BPNN的矿用铅酸蓄电池SOC在线估计

针对矿山避难硐室安全供电系统中铅酸蓄电池内化成过程中检测是否已经达到满电荷量,且在组装铅酸蓄电池时需要考虑电池均衡问题都需要进行准确估算SOC的问题,提出基于BP神经网络的PID控制通过修正反馈误差来实现铅酸蓄电池SOC在线估计。采用实验的方法获取数据,选取与电池SOC相关的因子作为BP神经网络的输入参数,最终准确在线预测蓄电池SOC值。仿真结果表明,基于BP神经网络的PID控制的铅酸蓄电池SOC估计的精度大大提高,同时为电池管理系统提供一个新的估计方法。     

基于RBF神经网络的加速度传感器动态补偿研究

提出一种应用径向基函数(RBF)神经网络进行加速度传感器动态性能补偿方法.介绍动态补偿原理以及算法,并将其与BP神经网络法和系统辨识法进行比较.该方法利用加速度传感器的动态标定数据,采用RBF神经网络搜索和优化补偿模型参数.结果表明,这种补偿模型误差小,比用系统辨识法有良好的鲁棒性、能实现在线软补偿,比用BP神经网络有更快的训练速度.     

基于BP神经网络的大规模电路模块级故障快速诊断方法

根据大规模电路故障诊断网络撕裂法和交叉撕裂搜索方法,采用基于误差反向传播算法的多层前向神经网络(BP神经网络)记载多次撕裂信息,提出了一种新型基于BP神经网络的大规模电路模块级快速诊断方法。该方法能快速有效地并行处理定位故障模块,具有测前工作量小,实时诊断性强等优点。     

一种基于BP神经网络算法PID控制器的研究与仿真

文中将BP神经网络的原理应用于参数辨识过程,结合传统的PID控制算法,形成一种改进型BP神经网络PID控制算法。该算法利用BP神经网络建立系统参数模型,能够跟踪被控对象的变化,取得较高的辨识精度。针对BP神经网络对权系初始值敏感的缺点,优化BP神经网络的初始权系数。通过BP算法修正BP网络自身权系数,实现PID参数的在线调整。仿真结果显示了该算法收敛速度快、精度高、鲁棒性强、稳定性好,表明了该算法的可行性与有效性。     

基于微粒群改进BP算法的非线性方程PID参数整定研究

文章从微粒群算法和BP神经网络基本原理出发,研究了将其用于PID控制的可行性,实现参数的在线自整定。仿真结果表明。基于微粒群优化BP神经网络的非线性PID参数自整定取得了良好的控制效果。     

一种可扩展BP在片学习神经网络芯片

基于0.6μm标准CMOS工艺,设计并实现了一种可扩展BP在片学习神经网络芯片.该芯片包含8个神经元和64个突触.提出了一种新颖的可扩展拓扑结构,使得利用该芯片构成完整的神经网络系统时,不需附加额外的神经元误差计算芯片;将L个芯片层叠起来就可以得到一个L层的神经网络.该芯片采用模拟电路,利用电容进行电荷存储,在片学习本身可用于权重刷新以保证权重值的正确性.奇偶校验实验证明了该神经网络芯片具有在片学习的能力.     

一种学习速率自适应的可编程片上学习BP神经网络电路系统的设计

设计了一种学习速率自适应的可编程片上学习BP神经网络电路系统.整个系统由前向网络、误差反传网络两部分组成.提出了一种新型的可编程S型函数及其导数的发生器电路.它不仅产生S型函数,完成非线性I－V转换;还利用前向差分法,产生S型函数的导数.这两种函数不仅与理想函数的拟合程度很好,而且易实现对阈值和增益因子的编程.为提高BP神经网络片上学习的收敛速度,还提出了学习速率自适应电路.本文采用标准1.2μm CMOS工艺的模型参数,对整个系统进行了sin(x)函数拟合等模拟实验,验证了该片上学习BP神经网络的优越性能.     

Circuit Design of On-Chip BP Learning Neural Network with Programmable Neuron Characteristics

A circuit system of on chip BP(Back-Propagation) learning neural network with pro grammable neurons has been designed,which comprises a feedforward network,an error backpropagation network and a weight updating circuit. It has the merits of simplicity,programmability, speedness,low power-consumption and high density. A novel neuron circuit with pro grammable parameters has been proposed. It generates not only the sigmoidal function but also its derivative. HSPICE simulations are done to a neuron circuit with level 47 transistor models as a standard 1.2tμm CMOS process. The results show that both functions are matched with their respec ive ideal functions very well. The non-linear partition problem is used to verify the operation of the network. The simulation result shows the superior performance of this BP neural network with on-chip learning.     

Parameters extraction and modeling for planar spiral inductor on Si-SiO/sub 2/ substrates by DDM for conformal modules

In this paper, the domain decomposition method (DDM) for conformal modules is used to get simple analytic expressions for parameters of planar spiral inductors on Si-SiO/sub 2/ substrates. The conductor and substrate losses are considered in the expressions. The quality factor of the spiral inductor is computed with a transmission-line mode and compared with previously published experimental results, showing that DDM model is accurate and efficient for modeling an on-chip spiral inductor on Si-SiO/sub 2/ substrates.     

Parallel,self-organizing,hierarchical neural networks with forward-backward training

A forward-backward training algorithm for parallel, self-organizing hierarchical neural networks (PSHNNs) is described. Using linear algebra, it is shown that the forward-backward training of ann-stage PSHNN until convergence is equivalent to the pseudo-inverse solution for a single, total network designed in the least-squares sense with the total input vector consisting of the actual input vector and its additional nonlinear transformations. These results are also valid when a single long input vector is partitioned into smaller length vectors. A number of advantages achieved are: small modules for easy and fast learning, parallel implementation of small modules during testing, faster convergence rate, better numerical error-reduction, and suitability for learning input nonlinear transformations by other neural networks. The backpropagation (BP) algorithm is proposed for learning input nonlinearitics. Better performance in terms of deeper minimum of the error function and faster convergence rate is achieved when a single BP network is replaced by a PSHNN of equal complexity in which each stage is a BP network of smaller complexity than the single BP network.     

Recent VLSI neural networks in Japan

In this article, recent research activities on the development of electronic neural networks in Japan are reviewed. Most of the largest Japanese electronic companies have developed VLSI neural chips using analog, digital or optoelectronic circuits. They have run various neural networks on them. Recently, in Japan, digital approach becomes active. Several fully-digital VLSI chips for on-chip BP learning have been developed, and 2.3 GCUPS (Giga Connection Updates per Second) learning speed has already been attained. Although the numbers of neurons and synapses containable in single digital chips are small, a large neural network can be developed by cascading the chips. By cascading 72 chips, a fully interconnected PDM (Pulse Density Modulating) digital neural network system has been developed. The behavior of the system follows simultaneous nonlinear differential equations and the processing speed amounts to 12 GCPS (Giga Connections per Second).Intensive researches on analog and optoelectronic approaches have also been carried out in Japan. An analog VLSI neural chip attains 28 GCUPS on-chip learning speed and 1 TCPS (Tera Connections per Second) processing speed for Boltzmann machine with 1 bit digital output. For the optoelectronic approach, although the network size is small, 640 MCUPS BP learning speed has been attained.     

An On-Chip BP Learning Neural Network with Ideal Neuron Characteristics and Learning Rate Adaptation

An on-chip BP(Back-Propagation) learning neural network with ideal neuron characteristics and learning rate adaptation is designed. A prototype LSI has been fabricated with a 1.2 m CMOS double-poly double-metal technology. A novel neuron circuit with ideal characteristics and programmable parameters is proposed. It can generate not only the sigmoid function but also its derivative. The test results of this neuron circuit show that both functions match with their ideal values very accurately. A learning rate adaptation circuit is also presented to accelerate the convergence speed. The 2-D binary classification and sin(x) function fitness experiments are done to the chip. Both experiments verify the superior performance of this BP neural network with on-chip learning.     

基于主成分分析与BP神经网络的识别方法研究

利用BP神经网络对红外目标进行识别之前,若不对原始样本数据进行预处理与特征提取,一方面使识别结果准确性降低,另一方面使BP神经网络的结构复杂化,采用主成分分析法可解决这些问题。主成分分析法能较好地提取表征样本的少数几个主分量,由该方法的特点可知,这几个主分量彼此不相关,非常符合特征优化的要求。研究结果表明,用该方法处理后的结果数据输入BP神经网络．提高了识别正确率,减少了训练时间,同时也简化了网络结构。将两种常见的模式识别方法结合用于红外目标识别：先由主成分分析法对原始样本数据进行精简处理,然后再由BP神经网络法进行分类识别,与传统的单一识别方法相比,准确度得到提高,计算量大为减少。     

一种基于JTAG接口的片上调试与性能分析方法

介绍了一种复用JTAG标准接口来实现处理器片上调试和性能分析的方法.以SuperV DSP处理器为研究对象,通过设计调试和性能分析模块以及相应指令,实现了运行控制,断点设置等调试功能以及统计执行周期数,Cache缺失率等性能分析数据的功能,极大地方便软件开发和应用程序优化,同时对处理器性能和功耗影响甚微.     

片上网络交换机制的研究

随着半导体技术进入超深亚微米时代,人们已经可以将越来越多的器件集成到单一芯片上来。运用传统的片上总线结构进行通信将面临诸多问题,如可扩展性差、定时困难和无法提供并行通信能力等,所以要运用片上网络来满足片上通信的带宽和能耗要求。本文研究了片上网络中的一项关键技术——交换机制。交换机制定义了消息在网络中交换的方式,并规定了沿输出端口将消息转发出去的时机。文章对片上网络中常用的电路交换、分组交换、虫孔交换和虚切通交换等进行了分析,并从能耗、面积、时延以及吞吐等性能方面进行了对比,给出了有益于片上网络沿用的结论。