MCM—C倒装焊工艺技术研究

简要介绍了主要倒装焊技术，重点研究了实用性强、可行性好的超声热压倒装焊、导电环氧粘接倒装、ACA粘接倒装以及MCM—C基板上的芯片倒装焊区制作、倒装后芯片的下填充等工艺技术，总结了芯片倒装互连质量的主要检验要求。     

助焊剂残留对底部填充粘接强度的影响

随着封装工艺的不断发展,芯片I/O数越来越多,高密度芯片封装必须采用倒装焊的形式。底部填充作为芯片倒装焊封装后的加固工艺,填充胶与倒装焊使用的助焊剂的兼容性对于研究倒装焊电路的长期可靠性至关重要。分析了底部填充胶与助焊剂的兼容性,以及助焊剂的残留对底部填充胶加固效果的影响。若助焊剂清洗不干净,会导致底部填充胶的粘接力下降,影响器件的质量。     

倒装焊陶瓷封装失效模式分析及失效机理研究

随着封装技术的发展,倒装焊技术得到广泛的应用,倒装焊的研究也越来越广泛深入。文章阐述了倒装焊封装的失效模式,主要有焊点疲劳失效、填充胶分层开裂失效、电迁移失效、腐蚀失效、机械应力失效等。并分析了陶瓷基板倒装焊温度循环试验后的失效模式,陶瓷倒装焊封装失效的机理主要是倒装芯片焊点与UBM界面金属间化合物应力开裂失效。根据失效机理分析,进行陶瓷倒装焊工艺优化改进,试验达到了JESD22-A104C标准规定的温度循环:-65℃～+150℃、500次循环、3只样品无失效的要求。     

GaN基功率型LED芯片散热性能测试与分析

与正装LED相比,倒装焊芯片技术在功率型LED的散热方面具有潜在的优势.对各种正装和倒装焊功率型LED芯片的表面温度分布进行了直接测试,对其散热性能进行了分析.研究表明,焊接层的材料、焊接接触面的面积和焊接层的质量是制约倒装焊LED芯片散热能力的主要因素;而对于正装LED芯片,由于工艺简单,减少了中间热沉,通过结构的优化,工艺的改进,完全可以达到与倒装焊LED芯片相同的散热能力.     

倒装芯片及封装技术

介绍了倒装芯片的发展过程，其中主要对制造技术、封装方法及倒装焊焊点的可靠性进行了评述。     

倒装焊后清洗工艺及其对底部填充的影响

倒装焊封装是通过将整个芯片有源面进行管脚阵列排布并预制焊料凸点,通过倒装焊工艺进行互连,与传统引线键合技术相比具有更高的组装密度及信号传输速率,是实现电子产品小型化、轻量化、多功能化的关键技术之一.对于小尺寸微节距的倒装焊芯片来说,焊后清洗的难度相对更大,因此清洗技术也是影响倒装焊工艺的重要因素.针对不同清洗方式及参数...     

基于小波分析的倒装芯片主动红外缺陷检测

随着微电子技术的需求和发展,倒装芯片技术在高密度微型化封装领域得到了快速发展和广泛应用,而现有的一些倒装芯片检测方法存在一定的不足之处。为此,研究了主动红外的倒装芯片缺陷检测方法。实验中使用激光加热对倒装样片施加非接触热激励,通过红外热像仪获取样片温度分布。采用小波分析方法提取包括小波熵在内的信号特征,采用自组织神经网络对不同类型焊球进行聚类识别。研究表明,通过自组织神经网络可以有效地将不同缺陷焊球与参考焊球通过距离映射法映射到不同区域从而区分开,并且可以将未知焊球信号映射到相应的区域实现聚类识别。因此该方法可以有效实现倒装芯片的缺陷检测。     

高加速应力试验用于倒装焊领域

倒装焊技术已被广泛地用于电子领域.对倒装焊而言,其焊点的可靠性、密封填充物与芯片或基板间的分层一直是特别重要的课题.介绍了一种加速环境试验--HAST,用于快速评价倒装焊接在FR-4基板上面阵列分布焊点的可靠性,试验结果说明HAST能够作为一个有效的可靠性试验评价工具用于倒装焊技术领域.     

倒装焊技术及应用

随着集成电路封装密度的提高,传统引线键合技术已经无法满足要求,倒装焊技术的发展能够解决该问题,并且得到了广泛的应用。文章介绍了倒装焊中的4种关键工艺技术,即UBM制备技术、凸点制备方法、倒装和下填充技术。其中凸点制备技术直接决定着倒装焊技术的好坏,为满足不同产品的需求,出现了不同的凸点制备技术,使倒装焊技术具备了好的发展前景。文章对各工艺技术的应用特点进行了阐述,并对倒装焊技术的发展前景进行了展望。     

微波倒装焊互连技术及特性分析

随着应用频率的提高,微波芯片与基板间的互连更多地采用了倒装焊。文中用HFSS（高频结构仿真器）有限元软件对凸点变换及倒装互连结构进行建模、仿真和优化,提取了凸点变换的等效集总电路模型,介绍了凸点制作工艺和倒装焊结构互连的微组装过程,并完成了试验样品的测试。最后,对微波倒装焊的前景进行了展望。     

气密性陶瓷封装内热应力的ANSYS分析

采用有限元方法,运用ANSYS软件,分析计算了气密性陶瓷封装管壳内温度及热应力分布,比较了4种粘接剂对芯片温度及热应力分布的影响。热分析表明,芯片中心处温度最高,边角处最低;不同粘接剂都因为厚度较薄,对芯片温度的分布无较大影响。热应力分析表明,由于热分布不均匀,使芯片与粘接剂的接触处有较大的热应力,主要集中在粘接剂与芯片的下底面,此处也是最容易导致芯片脱落失效的部分。对比4种粘接剂的结果发现:采用H35作粘接剂时,应力峰值为17.0MPa,但芯片与粘接剂和底座之间的热应力较大;采用PbSnAg焊料作粘接剂时,应力峰值为41.9MPa,但芯片与粘接剂和底座之间的热应力较小。     

Integrated electro-thermomechanical analysis of nonuniformly chip-powered microelectronic system

An integrated electrical, fluid flow and thermomechanical analysis is presented to study a product reliability and thermal management solution in an actual or nonuniform chip power distribution of an integrated circuit device in a realistic system application environment. This study aims to improve the existing limitations both on electrothermal analysis where simplified thermal boundary conditions is mostly used and on the current thermal and fluid flow analysis where uniform chip power is widely used to calculate the temperature. In this approach, the localized on-chip power distribution is obtained by using a transistor-level circuit model for simulating the interaction between the macro and functional blocks. A computational fluid dynamics analysis is used to calculate the fluid flow and heat transfer solution with a realistic thermal boundary conditions. To address the ultimate thermal induced mechanical stress and reliability effects on the chip-packaged assembly due to the nonuniform chip power distribution, finite element model is employed for the sequential steady-state heat transfer and mechanical analysis. The results are then discussed and specifically compared with the solutions based on the uniform chip power conditions.     

Thermal distribution calculations for block level placement in embedded systems

Reliability is a very important concern for the embedded systems. Thermal distribution has become an important reliability concern for today’s integrated circuits and these circuits are being used increasingly in embedded systems. In traditional design flows, the temperature of the chip is assumed to be uniform across the substrate. However, non-uniform thermal distribution can be a major source of inaccuracy in delay and clock skew computations, and can have an impact on elctromigration reliability and self-heating effects for today’s very deep submicron technology. Hence, it has become necessary to obtain design with uniform temperature distribution to ensure minimum temperature gradient and avoid hot spots across the chip area. This will minimise reliability problems during the operation of the chip. The uniform temperature distribution can be achieved by appropriate placement of circuit blocks during the physical design. In this paper, thermal distribution of single chip embedded system on silicon is discussed. The thermal distribution calculations require evaluation of switching activity factor of circuit blocks. This factor is determined by computing activities of the blocks based on the application software of embedded system.     

Thermal–mechanical behavior of the bonding wire for a power module subjected to the power cycling test

Two analytical methods were proposed in this research, coupled electro-thermal finite element (FE) analysis and thermal–mechanical FE analysis, to analyze the mechanical behavior of bonding wire of power module under cyclic power loads, and the International Electrotechnical Commission standard is adopted in conducting a power cycling test. The exterior temperature distribution was measured by an infrared thermometer. Moreover, the junction temperature is calculated from the given thermal impedance of the semiconductor chip, chip power loss, and case temperature. Subsequently, the simulated temperature distribution via electro-thermal FE analysis is compared with experimental results to validate the methodology used in the aforementioned analysis. The analysis shows compressive stress at the wire/chip interface due to CTE mismatch between the aluminum and the chip. Moreover, the major driving force contributing to the shear stress at the interface is the self-expansion of the wire bump.     

热应力影响下SCSP器件的界面分层

通过有限元方法研究了堆叠芯片尺寸封装(SCSP)器件在回流焊工艺过程中的热应力分布,采用修正J积分方法计算其热应力集中处应变能释放率。结果表明:堆叠封装器件中最大热应力出现在Die3芯片悬置端。J积分最大值出现在位于Die3芯片的上沿与芯片粘结剂结合部,达到1.35×10–2J/mm2,表明该位置的裂纹处于不稳定状态;在Die3芯片下缘的节点18,19和顶层节点27三个连接处的J积分值为负值,说明该三处裂纹相对稳定,而不会开裂处于挤压状态。     

Bus-driven floorplanning with thermal consideration

As the increasing number of buses in multi-core SoC designs, bus planning problems become a dominant factor in determining the chip performance. To cope with these issues, it is desirable to consider them in the early floorplanning stage. Recently, many bus-driven floorplanners have been proposed in the literature. However, these proposed algorithms only consider the bus planning problem without the thermal effect. As a result, there are hotspots, which result in high chip temperature, on the chip. In this paper, a thermal-driven bus-driven floorplanning algorithm is proposed to separate hotspots during the perturbation stage and to keep buses away from hotspots during the routing stage. To avoid time-consuming thermal simulations, the superposition of thermal profiles, which are the thermal distribution of each module, is adopted to efficiently estimate the module temperature. Compared with the state-of-the-art bus-driven floorplanner, experimental results demonstrate that the proposed algorithm can effectively separate hotspots and reduce the chip temperature.     

超薄芯片叠层封装器件热可靠性分析

采用通用有限元软件MSC.Marc,模拟分析了一种典型的多层超薄芯片叠层封装器件在经历回流焊载荷后的热应力及翘曲分布情况,研究了部分零件厚度变化对器件中叠层超薄芯片翘曲、热应力的影响。结果表明:在整个封装体中,热应力最大值(116.2 MPa)出现在最底层无源超薄芯片上,结构翘曲最大值(0.028 26 mm)发生于模塑封上部边角处。适当增大模塑封或底层无源芯片的厚度或减小底充胶的厚度可以减小叠层超薄芯片组的翘曲值;适当增大底层无源超薄芯片的厚度(例如0.01 mm),可以明显减小其本身的应力值10 MPa以上。     

一种高分子聚合物PCR芯片的设计及有限元分析

设计了一种以PDMS为基底的微型PCR芯片，并用有限元软件对芯片做了详细的温度场分析，主要分析了微型PCR芯片温度场的均匀性和分布以及芯片升、降温的效率。分析结果表明设计的聚合物芯片温度分布均匀，有较高的升、降温速率，可以满足PCR反应的要求。通过一维热传导理论分析，得到的结论与有限元分析的结果是一致的。     

Thermal properties of power HBT's

Simulations of the thermal behavior of AlGaAs/GaAs HBT power transistors have been carried out to establish the quantitative tradeoff between power density, chip layout and junction temperatures. Numerical programs were used to model different aspects of HBT thermal behavior. These programs provide a dynamic solution for temperature distribution using a three-dimensional model which is very general in its ability to model composite chip cross sections. A model was developed to calculate threshold power densities for thermal instability. Standard and novel methods of controlling maximum temperatures in the devices are explored and evaluated. These methods include flip chip bonding and the use of partial vias. The prevention of thermal instability is described. The thermal time constants are found to have a fast component, on order of a few microseconds, and a slower component that depends on substrate thickness     

用模拟退火算法实现集成电路热布局优化

介绍了一种综合考虑集成电路电学性能指标以及热效应影响的布局优化方法 .在保证传统设计目标 (如芯片面积、连线长度、延迟等 )不被恶化的基础上 ,通过降低或消除芯片上的热点来优化集成电路芯片的温度分布情况 ,进而优化整个电路性能 .并将改进的模拟退火算法应用于集成电路的热布局优化 ,模拟结果表明该方法与传统布局方法相比在保持了较好的延迟与连线长度等设计目标的同时 ,很好地改善了芯片表面的热分配情况