Numerical analysis of the self-heating effect in SGOI with a double step buried oxide

To reduce the self-heating effect of strained Si grown on relaxed SiGe-on-insulator(SGOI) n-type metal-oxide-semiconductor field-effect transistors(nMOSFETs),this paper proposes a novel device called double step buried oxide(BOX) SGOI,investigates its electrical and thermal characteristics,and analyzes the effect of self-heating on its electrical parameters.During the simulation of the device,a low field mobility model for strained Si MOSFETs is established and reduced thermal conductivity resulting from phonon boundary scattering is considered.A comparative study of SGOI nMOSFETs with different BOX thicknesses under channel and different channel strains has been performed.By reducing moderately the BOX thickness under the channel,the channel temperature caused by the self-heating effect can be effectively reduced.Moreover,mobility degradation,off state current and a short-channel effect such as drain induced barrier lowering can be well suppressed.Therefore,SGOI MOSFETs with a thinner BOX under the channel can improve the overall performance and long-term reliability efficiently.     

Fabrication and Simulation of Silicon-on-Insulator Structure with Si3N4 as a Buried Insulator

In order to minimize the self-heating effect of the classic SOI devices,SOI structures with Si3N4 film as a buried insulator (SOSN) are successfully formed using epitaxial layer transfer technology for the first time.The new SOI structures are investigated with high-resolution cross-sectional transmission electron microscopy and spreading resistance profile.Experiment results show that the buried Si3N4 layer is amorphous and the new SOI material has good structural and electrical properties.The output current characteristics and temperature distribution are simulated and compared to those of standard SOI MOSFETs.Furthermore,the channel temperature and negative differential resistance are reduced during high-temperature operation,suggesting that SOSN can effectively mitigate the self-heating penalty.The new SOI device has been verified in two-dimensional device simulation and indicated that the new structures can reduce device self-heating and increase drain current of the SOI MOSFET.     

掺杂硅微通道板的帕尔贴效应

The Seebeck coefficient is determined from silicon microchannel plates (Si MCPs) prepared by photo-assisted electrochemical etching at room temperature (25 ℃). The coefficient of the sample with a pore size of 5 × 5 μm², spacing of 1 μm and thickness of about 150 μm is -852 μV/K along the edge of the square pore. After doping with boron and phosphorus, the Seebeck coefficient diminishes to 256 μV/K and -117 μV/K along the edge of the square pore, whereas the electrical resistivity values are 7.5 × 10^-3 Ω·cm and 1.9 × 10^-3 Ω·cm, respectively. Our data imply that the Seebeck coefficient of the Si MCPs is related to the electrical resistivity and is consistent with that of bulk silicon. Based on the boron and phosphorus doped samples, a simple device is fabricated to connect the two type Si MCPs to evaluate the Peltier effect. When a proper current passes through the device, the Peltier effect is evidently observed. Based on the experimental data and the theoretical calculation, the estimated intrinsic figure of merit ZT of the unicouple device and thermal conductivity of the Si MCPs are 0.007 and 50 W/(m·K), respectively.     

Peltier effect in doped silicon microchannel plates

The Seebeck coefficient is determined from silicon microchannel plates（Si MCPs） prepared by photoassisted electrochemical etching at room temperature（25℃）.The coefficient of the sample with a pore size of 5×5μm²,spacing of 1μm and thickness of about 150μm is -852μV/K.along the edge of the square pore.After doping with boron and phosphorus,the Seebeck coefficient diminishes to 256μV/K and -117μV/K along the edge of the square pore,whereas the electrical resistivity values are 7.5×10^-3Ω·cm and 1.9×10^-3Ω·cm,respectively. Our data imply that the Seebeck coefficient of the Si MCPs is related to the electrical resistivity and is consistent with that of bulk silicon.Based on the boron and phosphorus doped samples,a simple device is fabricated to connect the two type Si MCPs to evaluate the Peltier effect.When a proper current passes through the device,the Peltier effect is evidently observed.Based on the experimental data and the theoretical calculation,the estimated intrinsic figure of merit ZT of the unicouple device and thermal conductivity of the Si MCPs are 0.007 and 50 W/（m·K）, respectively.     

Nanoscale strained-Si MOSFET physics and modeling approaches: a review

In this paper, an attempt has been made to give a detailed review of strained silicon technology. Various device models have been studied in this paper that consider the effect of strain on the devices and their comparisons have been drawn. A review of some modeling issues in strained silicon technology has also been outlined. The review indicates that this technology is very much required in nanoscale MOSFETs due to its several potential benefits and there is a strong need of an analytical model which describes the complete physics of the strain technology.     

中文题目：考虑共面波导电容的AlGaN/GaN HEMTs小信号建模研究

Given the coplanar waveguide(CPW) effect on AlGaN/GaN high electron mobility transistors at a high frequency, the traditional equivalent circuit model cannot accurately describe the electrical characteristics of the device. The admittance of CPW capacitances is large when the frequency is higher than 40 GHz; its impact on the device cannot be ignored. In this study, a small-signal equivalent circuit model considering CPW capacitance is provided. To verify the model, S-parameters are obtained from the modeling and measurements. A good agreement is observed between the simulation and measurement results, indicating the reliability of the model.     

深亚微米PDSOI的热阻提取

Deep submicron partially depleted silicon on insulator (PDSOI) MOSFETs with H-gate were fabricated based on the 0.35 μm SOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences. Because the self-heating effect (SHE) has a great influence on SOI, extractions of thermal resistance were done for accurate circuit simulation by using the body-source diode as a thermometer. The results show that the thermal resistance in an SOI NMOSFET is lower than that in an SOI PMOSFET; and the thermal resistance in an SOI NMOSFET with a long channel is lower than that with a short channel. This offers a great help to SHE modeling and parameter extraction.     

Complementary charge islands structure for a high voltage device of partial-SOI

A new partial-SOI(PSOI) high voltage device structure named CNCI PSOI(complementary n~+-charge islands PSOI) is proposed.CNCI PSOI is characterized by equidistant high concentration n~+ -regions on the top and bottom interfaces of a dielectric buried layer of a PSOI device.When a high voltage is applied to the device,complementary holes and electron islands are formed on the two n~+-regions on the top and bottom interfaces,therefore effectively enhancing the electric field of the dielectric buried layer(E_I) and increasing the breakdown voltage (BV),alleviating the self-heating effect(SHE) by the silicon window under the source.An analytical model of the vertical interface electric field for the CNCI PSOI is presented and the analytical results are in good agreement with the 2D simulation results.BV and E_I,of the CNCI PSOI LDMOS increase to 591 V and 512 V/μm from 216 V and 81.4 V/μm of the conventional PSOI with a lower SHE,respectively.The influence of structure parameters on the device characteristics is analyzed for the proposed device in detail.     

Averaged hole mobility model of biaxially strained Si

We aim to establish a model of the averaged hole mobility of strained Si grown on（001）,（101）,and （111） relaxed Si_1-xGe_x substrates.The results obtained from our calculation show that their hole mobility values corresponding to strained Si（001）,（101） and（111） increase by at most about three,two and one times,respectively, in comparison with the unstrained Si.The results can provide a valuable reference to the understanding and design of strained Si-based device physics.     

Enhancement of Crystalline Quality of Strained Straind InAs／InP Quantum Well Structures by Rapid Thermal Annealing

The effect of rapid thermal annealing of the optical properties of a strained InAs/InP single quantum well structrure has investigated in this paper.The luminescence intensity of the quantum well at 8K was increased by a factor of 4 and 1.55meV blue shoft of the quantum well photoluminescence peak was observed af-ter annealing at the optimal condition of 700℃ for 5s.Furthermoer,we found that the luminescence efficiency of the deep radiative levels in the samples was also affected by rapid thermal annealing.Our experimental results have demonstrated that Rapid thermal annealing significantly improves the erystalline quality of strained quantum well struc-tures after growth and is an important way for enhancement of the performance of the laser device.     

A comparative study of self-heating effect of nMOSFETs fabricated on SGOI and SGSOAN substrates

In this work, for the first time, the electrical and thermal characteristics of strained Si/SiGe nanoscale n type metal–oxide–silicon field-effect transistors (MOSFETs) with silicon-on-aluminum nitride (SOAN) substrate are investigated by ISE TCAD. This novel structure is named as SGSOAN nMOSFET. A comparative study of self-heating effect (SHE) of nMOSFETs fabricated on SGOI and SGSOAN are presented in this paper. Numerical study results show that this novel SGSOAN structure can greatly eliminate excessive self-heating in devices, which gives a more promising application for SGOI to work at high temperature.     

Ultrathin body SiGe-on-insulator pMOSFETs with high-mobility SiGe surface channels

A novel concept and a fabrication technique of strained SiGe-on-insulator (SGOI) pMOSFET are proposed and demonstrated. This device has an ultrathin strained SiGe channel layer, which is directly sandwiched by gate oxide and buried oxide layers. The mobility enhancement of 2.3 times higher than the universal mobility of conventional universal Si pMOSFETs was obtained for a pMOSFET with 19-nm-thick Si/sub 0.58/Ge/sub 0.42/ channel layer, which is formed by high-temperature oxidation of a Si/sub 0.9/Ge/sub 0.1/ layer grown on a Si-on-insulator (SOI) substrate. A fully depleted SGOI MOSFET with this simple single-layer body structure is promising for scaled SOI p-MOSFET with high current drive.     

Electron mobility enhancement in strained-Si n-MOSFETs fabricatedon SiGe-on-insulator (SGOI) substrates

We demonstrate electron mobility enhancement in strained-Si n-MOSFETs fabricated on relaxed Si_1-xGe_x-on-insulator (SGOI) substrates with a high Ge content of 25%. The substrates were fabricated by wafer bonding and etch-back utilizing a 20% Ge layer as an etch stop. Epitaxial regrowth was used to produce the upper portion of the Si_0.75Ge_0.26 and the surface strained Si layer. Large-area strained-Si n-MOSFETs were fabricated on this SGOI substrate. The measured electron mobility shows significant enhancement over both the universal mobility and that of co-processed bulk-Si MOSFETs. This SGOI process has a low thermal budget and thus is compatible with a wide range of Ge contents in Si_1-xGe_x layer     

Oxygen segregation and Ge diffusion in annealed oxygen ion-implanted relaxed SiGe/Si heterostructures

Relaxed SiGe-on-insulator (SGOI) is a suitable material to fabricate strained Si structures. Separation-by-implantation-of-oxygen (SIMOX) is a competing method to synthesize SGOI materials. In this work, SiGe/Si samples were implanted with 3×10¹⁷ cm⁻² oxygen ions at 60 kV, followed by high-temperature annealing. Oxygen segregation and Ge diffusion during the annealing process were investigated using Rutherford backscattering spectroscopy/channeling (RBS/C), high-resolution x-ray diffraction (HRXRD), and high-resolution transmission electron microscopy (HRTEM). Our results show that the sample structure strongly depends on the thermal history and Ge diffuses mainly at the beginning stage of the high-temperature process. The process can be improved by introducing an annealing step at a medium temperature before high-temperature annealing, and sharper interfaces and good crystal quality can be obtained. Our results indicate that the SIMOX process for silicon-on-insulator (SOI) fabrication can be adopted to produce SGOI.     

Strained Si/SiGe MOS technology: Improving gate dielectric integrity

Strained Si is recognised as a necessary technology booster for the nanoelectronics regime. This work shows that high levels of stress attainable from globally strained Si/SiGe platforms can benefit gate leakage and reliability in addition to MOSFET channel mobility. Device self-heating due to the low thermal conductivity of SiGe is shown to be the dominating factor behind compromised performance gains in short channel strained Si/SiGe MOSFETs. Novel thin virtual substrates aimed at reducing self-heating effects are investigated. In addition to reducing self-heating effects, the thin virtual substrates provide further improvements to gate oxide integrity, reliability and lifetime compared with conventional thick virtual substrates. This is attributed to the lower surface roughness of the thin virtual substrates which arises due to the reduced interactions of strain-relieving misfit dislocations during thin virtual substrate growth. Good agreement between experimental data and physical models is demonstrated, enabling gate leakage mechanisms to be identified. The advantages and challenges of using globally strained Si/SiGe to advance MOS technology are discussed.     

Fabrication and analysis of deep submicron strained-Si n-MOSFET's

Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si_0.8Ge_0.2 heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 μm) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects     

双应变SiGe/Si异质结CMOS的设计及其电学特性的Medici模拟

本文提出一种沟道长度为0.125 μm的异质结CMOS(HCMOS)器件结构.在该结构中,压应变的SiGe与张应变的Si分别作为异质结PMOS(HPMOS)与异质结NMOS(HNMOS)的沟道材料,且HPMOS与HNMOS为垂直层叠结构;为了精确地模拟该器件的电学特性,修正了应变SiGe与应变Si的空穴与电子的迁移率模型;利用Medici软件对该器件的直流与交流特性,以及输入输出特性进行了模拟与分析.模拟结果表明,相对于体Si CMOS器件,该器件具有更好的电学特性,正确的逻辑功能,且具有更短的延迟时间,同时,采用垂直层叠的结构此类器件还可节省约50%的版图面积,有利于电路的进一步集成.     

New opportunities for SiGe and Ge channel p-FETs

A thin body (fully depleted) strained SGOI device structure (FDSGOI), and a strained SiGe channel layer on SOI, were fabricated using scaled high-κ gate dielectrics and metal gate technology. The uniaxial strain effect and corresponding drive current enhancement reported by Irisawa et al. [1] for narrow-width devices was investigated on these structures. Although the strained FDSGOI device structure exhibited reduced off-state leakage compared to thicker body devices, and long-channel drive current enhancement under uniaxial strain, the loss of drive current enhancement at short channel length led to uncompetitive I_ON-I_OFF characteristics. The SiGe on SOI structure showed the highest long-channel drive current enhancement (nearly 3×) in the narrowest devices, and also showed a significant reduction in off-state current. This trend was maintained down to the shortest channel lengths studied here and resulted in I_ON-I_OFF characteristics that were competitive with contemporary uniaxial strained Si channel devices.